CDC536DLR [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS; 具有三态输出的3.3V锁相环时钟驱动器
| 型号： | CDC536DLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总14页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
FEATURES
DB OR DL PACKAGE
(TOP VIEW)
•
Low-Output Skew for Clock-Distribution and
Clock-Generation Applications
•
•
•
Operates at 3.3-V VCC
AV
AV
CC
1
2
3
4
5
6
7
8
9
28
27
CC
AGND
CLKIN
SEL
OE
GND
1Y1
AGND
Distributes One Clock Input to Six Outputs
26 FBIN
One Select Input Configures Three Outputs to
Operate at One-Half or Double the Input
Frequency
TEST
CLR
25
24
23
22
V
CC
•
•
No External RC Network Required
2Y1
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
V
CC
21 GND
20
19 2Y2
GND
1Y2 10
V
CC
•
•
Application for Synchronous DRAM,
High-Speed Microprocessor
V
CC
GND
11
12
13
14
18
17
16
GND
1Y3
V
CC
Negative-Edge-Triggered Clear for
Half-Frequency Outputs
2Y3
V
CC
15 GND
•
•
TTL-Compatible Inputs and Outputs
Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines
•
•
•
State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation
Distributed VCC and Ground Pins Reduce
Switching Noise
Packaged in Plastic 28-Pin Shrink Small
Outline Package
DESCRIPTION
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely
align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically
designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to
100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V
VCC and is designed to drive a 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input
configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed
back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty
cycle at the input clock.
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass
the PLL. TEST should be strapped to GND for normal operation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-IIB is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application of a
fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback
signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of
all outputs via OE.
The CDC536 is characterized for operation from 0°C to 70°C.
DETAILED DESCRIPTION OF OUTPUT CONFIGURATIONS
The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice the
operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to
provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0
and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN, the
VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or one-half
the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the
CLKIN frequency.
Output Configuration A
Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to the
FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output
configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs
configured as 1× outputs operate at the same frequency as the CLKIN input.
Table 1. Output Configuration A
INPUTS
SEL
OUTPUTS
1/2×
FREQUENCY
1×
FREQUENCY
L
None
1Yn
All
H
2Yn
Output Configuration B
Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B.
Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs
operate at double the frequency of the CLKIN input.
Table 2. Output Configuration B
INPUTS
SEL
OUTPUTS
1×
2×
FREQUENCY
FREQUENCY
L
All
None
2Yn
H
1Yn
2
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM
5
OE
24
26
3
CLR
FBIN
B2
Phase-Lock Loop
B2
CLKIN
TEST
25
4
SEL
7
10
13
1Y1
1Y2
1Y3
22
19
2Y1
2Y2
16
2Y3
3
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
FUNCTIONAL BLOCK DIAGRAM (continued)
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Clock input. CLKIN provides the clock signal to be distributed by the CDC536 clock-driver circuit. CLKIN is
used to provide the reference signal to the integrated phase-lock loop that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain
phase lock. Once the circuit is powered up and a valid CLKIN signal is applied, a stabilization time is
required for the phase-lock loop to phase lock the feedback signal to its reference signal.
CLKIN
3
I
CLR
24
26
I
I
CLR is used for testing purposes only. Connect CLR to GND for normal operation.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of
the six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to
obtain zero phase delay between the FBIN and differential CLKIN inputs.
FBIN
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE
is high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is
taken directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop;
therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is
required before the phase-lock loop obtains phase lock.
OE
5
I
Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or
2×).(see Tables 1 and 2).
SEL
4
I
I
TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low,
all outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that
bypasses the PLL circuitry. TEST should be grounded for normal operation.
TEST
25
These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The
relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle
of the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal.
1Y1-1Y3
7, 10, 13
O
O
These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency
and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty
cycle of the Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal.
2Y1-2Y3 22, 19, 16
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
-0.5 V to 4.6 V
-0.5 V to 7 V
-0.5 V to 5.5 V
64 mA
Supply voltage range, VCC
(2)
Input voltage range, VI (see
)
(2)
Voltage range applied to any output in the high state or power-off state, VO(see
Current into any output in the low state, IO
Input clamp current, IIK(VI < 0)
)
-20 mA
Output clamp current, IOK(VO < 0)
-50 mA
Maximum power dissipation at TA = 55°C (in still air) (see (3)):
DB package
DL package
0.68 W
0.7 W
Operating free-air temperature range, TA
Storage temperature range, Tstg
0°C to 70°C
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For
more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book,
literature number SCBD002.
4
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
(1)
RECOMMENDED OPERATING CONDITIONS (SEE
)
MIN
3
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
2
0.8
5.5
32
32
70
V
0
0
V
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
(1) Unused inputs must be held high or low.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
II = -18 mA
UNIT
V
MIN MAX
VIK
VCC = 3 V,
1.2
VCC = MIN to MAX(1)
VCC = 3 V,
,
IOH = -100 µA
IOH = -32 mA
IOL = 100 µA
IOL = 32 mA
VI = 3.6 V
VCC-0.2
VOH
V
2
VCC = 3 V,
0.2
0.5
±10
±1
10
10
2
VOL
V
VCC = 3 V,
VCC = 0 or MAX(1)
,
II
µA
VCC = 3.6 V,
VI = VCC or GND
VO = 3 V
IOZH
IOZL
VCC = 3.6 V,
µA
µA
VCC = 3.6 V,
VO = 0
Outputs high
Outputs low
ICC
VCC = 3.6 V, IO = 0, VI = VCC or GND
2
mA
Outputs disabled
2
Ci
VI = VCC or GND
VO = VCC or GND
6
pF
pF
Co
9
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
MIN
MAX UNIT
When VCO is operating at four times the CLKIN frequency
When VCO is operating at double the CLKIN frequency
25
50
50
MHz
100
fclock
Clock frequency
Input clock duty cycle
40%
60%
50
After SEL
After OE↓
50
µs
50
Stabilization time(1)
After power up
After CLKIN
50
(1) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to
be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristics table are not applicable.
5
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, CL = 30 pF (see (1) and Figure 1 and
Figure 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
fmax
Duty cycle
100
45%
500
MHz
55%
Y
Y
Y
(2)
tphase error
CLKIN↑
CLKIN↑
+500
200
0.5
1
ps
ps
ns
ns
ns
ns
Jitter(pk-pk)
(2)
tsk(o)
tsk(pr)
tr
tf
1.4
1.4
(1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
(2) The propagation delay, tphase error, is dependent on the feedback path from any output to FBIN. The tphase error, tsk(o), and tsk(pk)
specifications are only valid for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
1.5 V
1.5 V
t
phase error
From Output
Under Test
V
V
OH
2 V
0.8 V
2 V
Output
500 W
1.5 V
0.8 V
C
= 30 pF
L
OL
(see note A)
t
r
t
f
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR OUTPUTS
A. NOTES: . CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR≤ 100 MHz, ZO = 50 Ω, tr≤ 2.5 ns,
tf≤ 2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
CLKIN
t
t
phase error 1
Outputs
Operating
at 1/2 CLKIN
Frequency
phase error 2
t
t
phase error 3
t
phase error 4
phase error 7
Outputs
Operating
at CLKIN
t
t
t
phase error 5
phase error 8
Frequency
t
phase error 9
phase error 6
A. NOTES: . Output skew, tsk(o), is calculated as the greater of:
•
•
The difference between the fastest and slowest of tphase error n (n = 1, 2, . . . 6)
The difference between the fastest and slowest of tphase error n (n = 7, 8, 9)
B. Process skew, tsk(pr), is calculated as the greater of:
•
The difference between the maximum and minimum tphase error n (n = 1, 2, . . . 6) across multiple devices under
identical operating conditions.
•
The difference between the maximum and minimum tphase
identical operating conditions.
(n = 7, 8, 9) across multiple devices under
n
error
Figure 2. Skew Waveforms and Calculations
7
CDC536
www.ti.com
SCAS378G–APRIL 1994–REVISED JULY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
CLKIN
t
phase error 10
Outputs
Operating
at CLKIN
t
phase error 11
Frequency
t
t
phase error 12
phase error 13
Outputs
Operating
at 2× CLKIN
Frequency
t
phase error 14
phase error 15
t
A. NOTES: . Output skew, tsk(o), is calculated as the greater of:
The difference between the fastest and slowest of tphase error n (n = 10, 11, . . . 15)
B. Process skew, tsk(pr), is calculated as the greater of:
•
•
The difference between the maximum and minimum tphase
under identical operating conditions.
(n = 10, 11, . . . 15) across multiple devices
n
error
Figure 3. Waveforms for Calculation of tsk(o) and tsk(pr)
8
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
CDC536DB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDC536DBG4
CDC536DBR
SSOP
SSOP
SSOP
DB
DB
DB
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDC536DBRG4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CDC536DL
OBSOLETE
OBSOLETE
SSOP
SSOP
DL
DL
28
28
TBD
TBD
Call TI
Call TI
Call TI
Call TI
CDC536DLR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CDC536DBR
SSOP
DB
28
2000
330.0
16.4
8.1
10.4
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SSOP DB 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
CDC536DBR
2000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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logic.ti.com
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相关型号：
CDC5801ADBQG4
Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignment 24-SSOP -40 to 85
TI
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