CDC303D [TI]
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TEXAS INSTRUMENTS 
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS303
Maximum Output Skew Between Same
Phase Outputs of 1 ns
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q2
Q1
CLR
Q3
Q4
GND
GND
GND
Q5
Maximum Pulse Skew of 1 ns
TTL-Compatible Inputs and Outputs
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
V
CC
CC
V
CC
CLK
PRE
Q8
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
Q6
Q7
description
The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six
in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC303 has output and pulse-skew parameters t
when a divide-by-two function is required.
and t
to ensure performance as a clock driver
sk(o)
sk(p)
The CDC303 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
PRE
H
CLK Q1–Q6 Q7–Q8
X
X
X
↑
L
H
L
H
L
H
†
L
†
L
L
L
H
H
Q
Q
Q
Q
0
0
0
0
H
H
L
†
This configuration does not persist when
PRE or CLR returns to its inactive (high)
level.
‡
logic symbol
15
Q1
16
Q2
1
10
11
PRE
CLK
S
T
Q3
2
Q4
6
Q5
7
Q6
8
14
CLR
R
Q7
9
Q8
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
logic diagram (positive logic)
15
16
Q1
Q2
1
2
Q3
Q4
10
PRE
S
R
11
14
C1
CLK
CLR
6
7
8
9
Q5
Q6
Q7
Q8
1D
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Maximum power dissipation at T = 55°C (in still air) (see Note 1): D package . . . . . . . . . . . . . . . . . . 0.77 W
A
N package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input clock frequency
Operating free-air temperature
V
IH
0.8
–24
48
V
IL
I
I
f
mA
mA
MHz
°C
OH
OL
clock
80
T
A
0
70
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
I = –18 mA
–1.2
V
IK
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
I
= –2 mA
= –24 mA
= 48 mA
V
–2
2
OH
OH
OL
CC
V
OH
OL
2.8
0.3
= 4.5 V,
0.5
0.1
V
I
I
I
I
I
= 5.5 V,
V = 7 V
I
mA
µA
I
= 5.5 V,
V = 2.7 V
I
20
IH
IL
= 5.5 V,
V = 0.4 V
I
–0.5
–150
70
mA
mA
mA
‡
= 5.5 V,
V
O
= 2.25 V
–50
O
= 5.5 V,
See Note 2
40
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
NOTE 2:
I
is measured with CLK and PRE grounded, then with CLK and CLR grounded.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
0
MAX
UNIT
f
t
t
Clock frequency
80
MHz
clock
w
CLR or PRE low
CLK high
5
Pulse duration
4
ns
ns
CLK low
6
Setup time before CLK↑
CLR or PRE inactive
6
su
switching characteristics over recommended operating free-air temperature range (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
§
f
t
t
t
t
80
2
MHz
max
9
9
PLH
PHL
PLH
PHL
CLK
R
R
= 500 Ω,
= 500 Ω,
C
C
= 50 pF
= 50 pF
ns
ns
Q, Q
Q, Q
L
L
L
L
2
3
12
12
1
PRE or CLR
3
Q
R
= 500 Ω,
C
C
= 10 pF to 30 pF,
= 10 pF to 30 pF
L
L
L
t
CLK
CLK
Q
1
ns
sk(o)
See Figure 2
Q, Q
Q, Q
2
t
t
t
R
= 500 Ω,
L
1
ns
ns
ns
sk(p)
4.5
3.5
r
f
§
f
minimum values are at C = 0 to 30 pF.
L
max
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test Point
R
L
C
L
(see Note A)
LOAD CIRCUIT
3.5 V
CLR
or
PRE
1.3 V
0 V
t
su
t
w
3.5 V
CLK
1.3 V
1.3 V
0.3 V
t
PLH
t
PHL
V
OH
Q
1.3 V
1.3 V
V
OL
NOTES: A.
C includes probe and jig capacitance.
L
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = 2.5 ns, t = 2.5 ns.
r
f
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
0
CLR, PRE
CLK
t
PHL1
t
PLH1
Q1
Q2
t
t
t
t
t
t
t
PLH2
PLH3
PLH4
PHL2
PHL3
PHL4
PHL5
Q3
Q4
t
t
PLH5
PLH6
Q5
Q6
t
PHL6
t
t
PHL7
PHL8
t
t
PLH7
PLH8
Q7
Q8
NOTES: A. t
sk(o)
, CLK to Q, is calculated as the greater of:
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
( n = 1, 2, 3, 4, 5, 6)
( n = 1, 2, 3, 4, 5, 6)
PLHn
PHLn
B.
C. t
t
, CLK to Q, is calculated as the greater of: | t
PLH7 PLH8
, CLK to Q and Q, is calculated as the greater of:
– t
| and | t
– t
|.
sk(o)
sk(o)
PHL7 PHL8
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
( n = 1, 2, 3, 4, 5, 6), t
( n = 1, 2, 3, 4, 5, 6), t
, and t
PHL7
, and t
PLH7
PLHn
PHLn
PHL8
PLH8
D.
t
is calculated as the greater of | t
– t | ( n = 1, 2, 3, . . ., 8 ).
PLHn PHLn
sk(p)
Figure 2. Waveforms for Calculation of t
and t
sk(p)
sk(o)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2005
PACKAGING INFORMATION
Orderable Device
CDC303D
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPD
Level-1-260C-UNLIM
CDC303DR
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPD
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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相关型号：
CDC303N
LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PDIP16, 0.300 INCH, PLASTIC, DIP-16
TI
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