CDC305D [TI]
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER; 八路除以2电路/时钟驱动器
| 型号： | CDC305D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER |
| 文件： | 总7页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS305
Maximum Output Skew of 1 ns
Maximum Pulse Skew of 1ns
TTL-Compatible Inputs and Outputs
Q2
Q3
Q4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
CLR
V
V
CLK
PRE
Q8
GND
GND
GND
Q5
Q6
Q7
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
CC
CC
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
description
The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four
in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters t
when a divide-by-two function is required.
and t
to ensure performance as a clock driver
sk(o)
sk(p)
The CDC305 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
PRE
H
CLK Q1–Q4 Q5–Q8
X
X
X
L
↑
L
H
L
H
L
H
†
L
†
L
L
L
H
H
Q
Q
Q
Q
0
0
0
0
H
H
†
This configuration does not persist when
PRE or CLR returns to its inactive (high)
level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
†
logic symbol
14
S
R
CLR
10
11
PRE
CLK
C1
15
16
1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
2
6
7
8
9
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
15
16
1
Q1
Q2
Q3
Q4
10
11
14
PRE
S
R
2
CLK
CLR
C1
6
7
8
9
Q5
Q6
Q7
Q8
1D
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Maximum power dissipation at T = 55°C (in still air) (see Note 1): D package . . . . . . . . . . . . . . . . . . 0.77 W
A
N package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–24
48
V
IL
I
I
mA
mA
°C
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
I = –18 mA
–1.2
V
IK
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
I
= –2 mA
= –24 mA
= 48 mA
V
–2
2
OH
OH
OL
CC
V
OH
OL
2.8
0.3
= 4.5 V,
0.5
0.1
V
I
I
I
I
I
= 5.5 V,
V = 7 V
I
mA
µA
I
= 5.5 V,
V = 2.7 V
I
20
IH
IL
= 5.5 V,
V = 0.4 V
I
–0.5
–150
70
mA
mA
mA
‡
= 5.5 V,
V
O
= 2.25 V
–50
O
= 5.5 V,
See Note 2
40
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
NOTE 2:
I
is measured with CLK and PRE grounded, then with CLK and CLR grounded.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
0
MAX
UNIT
f
t
t
Clock frequency
80
MHz
clock
w
CLR or PRE low
CLK high
5
Pulse duration
4
ns
ns
CLK low
6
Setup time before CLK↑
CLR or PRE inactive
6
su
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
‡
f
t
t
t
t
80
2
MHz
max
6
6
7
7
9
9
PLH
PHL
PLH
PHL
CLK
R
R
= 500 Ω,
= 500 Ω,
C
C
= 50 pF
= 50 pF
ns
ns
Q, Q
Q, Q
L
L
L
L
2
3
12
12
1
PRE or CLR
3
Q
R
= 500 Ω,
C
C
= 10 pF to 30 pF,
= 10 pF to 30 pF
L
L
L
t
CLK
CLK
Q
1
ns
sk(o)
See Figure 2
Q1–Q8
Q1, Q8
Q2–Q7
1.5
1.5
2
t
R
= 500 Ω,
ns
sk(p)
L
t
t
4.5
3.5
ns
ns
r
f
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
L
CC
minimum values are at C = 0 to 30 pF.
f
max
PARAMETER MEASUREMENT INFORMATION
From Output
Test Point
Under Test
R
L
C
L
(see Note A)
LOAD CIRCUIT
3.5 V
CLR
or
1.3 V
PRE
0.3 V
3.5 V
t
su
t
w
CLK
1.3 V
1.3 V
0.3 V
t
PLH
t
PHL
V
OH
Q
1.3 V
1.3 V
V
OL
NOTES: A.
C includes probe and jig capacitance.
L
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = 2.5 ns, t = 2.5 ns.
r
f
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
0
CLR, PRE
CLK
t
PHL1
t
PLH1
Q1
Q2
t
t
t
t
t
PLH2
PLH3
PHL2
PHL3
PHL4
Q3
Q4
t
PLH4
t
PHL5
t
PLH5
Q5
Q6
t
t
PHL6
PHL7
t
t
PLH6
PLH7
Q7
Q8
t
PHL8
t
PLH8
NOTES: A. t
B. t
CLK to Q are calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, 3, 4)
(n = 1, 2, 3, 4)
PLHn
PHLn
CLK to Q are calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 5, 6, 7, 8)
(n = 5, 6, 7, 8)
PLHn
PHLn
C. t
CLK to Q and Q are calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, 3, 4), t
(n = 1, 2, 3, 4), t
(n = 5, 6, 7, 8)
(n = 5, 6, 7, 8)
PLHn
PHLn
PHLn
PLHn
D.
t
is calculated as the greater of | t
– t | (n = 1, 2, 3, . . . , 8).
PLHn PHLn
sk(p)
Figure 2. Waveforms for Calculation of t
and t
sk(p)
sk(o)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PDIP
SOIC
SOIC
PDIP
Drawing
CDC305-1N
CDC305D
CDC305DR
CDC305N
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
N
D
D
N
16
16
16
16
TBD
TBD
TBD
TBD
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(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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