CDC304 [TI]
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER; 八路除以2电路/时钟驱动器
| 型号： | CDC304 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER |
| 文件： | 总6页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
D OR N PACKAGE
(TOP VIEW)
Replaces SN74AS304
Maximum Output Skew of 1 ns
Maximum Pulse Skew of 1.5 ns
TTL-Compatible Inputs and Outputs
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q2
Q1
CLR
Q3
Q4
GND
GND
GND
Q5
Center-Pin V
Minimize High-Speed Switching Noise
and GND Configurations
CC
V
CC
V
CC
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
CLK
PRE
Q8
Q6
Q7
description
The CDC304 contains eight flip-flops designed to have low skew between outputs. The eight outputs (in-phase
with CLK) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q
outputs high or low independent of the clock (CLK) input.
The CDC304 has output and pulse-skew parameters t
when a divide-by-two function is required.
and t
to ensure performance as a clock driver
sk(o)
sk(p)
The CDC304 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
Q1–Q8
CLR
L
PRE
H
CLK
X
L
H
L
X
H
†
L
L
L
X
H
H
↑
Q
Q
0
0
H
H
L
†
This configuration does not persist
when PRE or CLR returns to its
inactive (high) level.
‡
logic symbol
15
Q1
16
Q2
1
10
11
PRE
CLK
S
T
Q3
2
Q4
6
Q5
7
Q6
14
8
CLR
R
Q7
9
Q8
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
logic diagram (positive logic)
15
16
1
Q1
Q2
Q3
10
PRE
CLK
S
R
11
14
2
C1
Q4
Q5
CLR
6
1D
7
8
9
Q6
Q7
Q8
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Maximum power dissipation at T = 55°C (in still air) (see Note 1): D package . . . . . . . . . . . . . . . . . . 0.77 W
A
N package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input clock frequency
Operating free-air temperature
V
IH
0.8
–24
48
V
IL
I
I
f
mA
mA
MHz
°C
OH
OL
clock
80
T
A
0
70
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
–1.2
V
IK
I
I
I
I
= –2 mA
= –24 mA
= 48 mA
V
–2
2
OH
OH
OL
CC
V
OH
OL
2.8
0.3
0.5
0.1
V
I
I
I
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.5
–150
75
mA
mA
mA
‡
V
O
= 2.25 V
–50
O
See Note 2
45
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
NOTE 2:
I
is measured with CLK and PRE grounded, then with CLK and CLR grounded.
CC
timing requirements
MIN
0
MAX
UNIT
f
t
t
Clock frequency
80
MHz
clock
w
CLR or PRE low
CLK high
5
Pulse duration
4
ns
CLK low
6
Setup time before CLK↑
CLR or PRE inactive
6
ns
su
switching characteristics over recommended operating free-air temperature range (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
§
f
t
t
t
t
80
2
MHz
max
6
6
7
7
9
9
PLH
PHL
PLH
PHL
CLK
Q
R
= 500 Ω,
C
= 50 pF
ns
L
L
2
3
12
12
Q
Q
R
R
= 500 Ω,
= 500 Ω,
C
C
= 50 pF
ns
ns
ns
PRE or CLR
CLK
L
L
L
L
3
= 10 pF to 30 pF,
t
t
1
sk(o)
See Figure 2
Q1, Q8
Q2–Q7
1
1.5
4.5
3.5
CLK
R
= 500 Ω,
C
= 10 pF to 30 pF
sk(p)
L
L
t
t
ns
ns
r
f
†
§
All typical values are at V
= 5 V, T = 25°C.
A
L
CC
minimum values are at C = 0 to 30 pF.
f
max
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test Point
R
L
C
L
(see Note A)
LOAD CIRCUIT
3.5 V
CLR
or
PRE
1.3 V
0.3 V
3.5 V
t
su
t
w
CLK
1.3 V
1.3 V
0.3 V
t
PLH
t
PHL
V
OH
Q
1.3 V
1.3 V
V
OL
NOTES: A.
C includes probe and jig capacitance.
L
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, t = 2.5 ns, t = 2.5 ns.
r
f
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
0
CLR, PRE
CLK
t
PHL1
t
PLH1
Q1
Q2
t
t
t
t
PLH2
PHL2
PHL3
PLH3
Q3
Q4
t
t
t
PHL4
PHL5
PLH4
t
t
PLH5
PLH6
Q5
Q6
Q7
Q8
t
t
PHL6
PHL7
t
t
PLH7
PLH8
t
PHL8
NOTES: A. t
sk(o)
, CLK to Q, is calculated as the greater of the following:
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
( n = 1, 2, 3 . . ., 8 )
( n = 1, 2, 3 . . ., 8 )
PLHn
PHLn
B.
t
is defined at the greater of | t
– t | ( n = 1, 2, 3, . . ., 8 ).
PLHn PHLn
sk(p)
Figure 2. Waveforms for Calculation of t
and t
sk(p)
sk(o)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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