54ACT163LMX [TI]
ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20, CERAMIC, LCC-20;
| 型号： | 54ACT163LMX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20, CERAMIC, LCC-20 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1995
54AC/74AC163 54ACT/74ACT163
#
Synchronous Presettable Binary Counter
General Description
Features
Y
CC
I
reduced by 50%
The ’AC/’ACT163 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for ap-
plication in programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output for versa-
tility in forming synchronous multistage counters. The ’AC/
’ACT163 has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
Y
Y
Y
Y
Y
Y
Synchronous counting and loading
High-speed synchronous expansion
Typical count rate of 125 MHz
Outputs source/sink 24 mA
’ACT163 has TTL-compatible inputs
Standard Military Drawing (SMD)
Ð ’AC163: 5962-89582
Ð ’ACT163: 5962-90575
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP, Flatpak and SOIC
IEEE/IEC
TL/F/9932–1
TL/F/9932–3
Pin Assignment
for LCC
TL/F/9932–2
Pin Names
Description
CEP
CET
CP
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
SR
Synchronous Reset Input
Parallel Data Inputs
P –P
0
3
PE
Parallel Enable Input
Flip-Flop Outputs
Q –Q
0
3
TC
Terminal Count Output
TL/F/9932–4
FACTTM is a trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/9932
RRD-B30M16/Printed in U. S. A.
Functional Description
The ’AC/’ACT163 counts in modulo-16 binary sequence.
From state 15 (HHHH) it increments to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs occur as a
result of, and synchronous with, the LOW-to-HIGH transition
of the CP input signal. The circuits have four fundamental
modes of operation, in order of precedence: synchronous
reset, parallel load, count-up and hold. Four control inputsÐ
Synchronous Reset (SR), Parallel Enable (PE), Count En-
able Parallel (CEP) and Count Enable Trickle (CET)Ðdeter-
mine the mode of operation, as shown in the Mode Select
Table. A LOW signal on SR overrides counting and parallel
loading and allows all outputs to go LOW on the next rising
edge of CP. A LOW signal on PE overrides counting and
there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock
period is the CP to TC delay of the first stage plus the CEP
to CP setup time of the last stage. The TC output is subject
to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchro-
nous reset for flip-flops, registers or counters.
e
Logic Equations: Count Enable
e
CEP CET PE
#
#
CET
TC
Q
Q
Q
Q
#
#
#
#
3
0
1
2
Mode Select Table
Action on the Rising
SR
PE
CET
CEP
Clock Edge (L)
allows information on the Parallel Data (P ) inputs to be
n
L
H
H
H
H
X
L
X
X
H
L
X
X
H
X
L
Reset (Clear)
loaded into the flip-flops on the next rising edge of CP. With
PE and SR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
Load (Pn x Q )
n
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
X
The ’AC/’ACT163 uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is in
either state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising
edge of CP, are observed.
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
State Diagram
The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC
delay of the first stage, plus the cumulative CET to TC de-
lays of the intermediate stages, plus the CET to CP setup
time of the last stage. This total delay plus setup time sets
the upper limit on clock frequency. For faster clock rates,
the carry lookahead connections shown in Figure 2 are rec-
ommended. In this scheme the ripple delay through the in-
termediate stages commences with the same clock that
causes the first stage to tick over from max to min in the Up
mode, or min to max in the Down mode, to start its final
cycle. Since this final cycle takes 16 clocks to complete,
TL/F/9932–5
TL/F/9932–8
FIGURE 1
TL/F/9932–9
FIGURE 2
2
Block Diagram
3
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
’AC
’ACT
)
CC
2.0V to 6.0V
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
DC Input Diode Current (I
)
IK
Input Voltage (V )
I
0V to V
0V to V
CC
e b
b
a
V
I
V
I
0.5V
a
20 mA
20 mA
Output Voltage (V
)
O
CC
e
V
CC
0.5V
Operating Temperature (T )
A
74AC/ACT
54AC/ACT
b
b
a
0.5V
DC Input Voltage (V )
I
0.5V to V
0.5V to V
CC
b
b
a
40 C to 85 C
§
55 C to 125 C
§
§
DC Output Diode Current (I
)
a
OK
§
e b
b
a
V
V
0.5V
a
20 mA
20 mA
O
O
Minimum Input Edge Rate (DV/Dt)
’AC Devices
e
V
CC
0.5V
a
DC Output Voltage (V
DC Output Source
)
O
0.5V
50 mA
50 mA
CC
V
V
from 30% to 70% of V
@
IN
CC
3.3V, 4.5V, 5.5V
125 mV/ns
125 mV/ns
CC
g
g
or Sink Current (I
)
O
Minimum Input Edge Rate (DV/Dt)
’ACT Devices
DC V
or Ground Current
CC
per Output Pin (I or I
CC
)
V
V
from 0.8V to 2.0V
@
GND
)
IN
4.5V, 5.5V
b
a
65 C to 150 C
CC
Storage Temperature (T
§
§
STG
Junction Temperature (T )
J
CDIP
PDIP
175 C
§
140 C
§
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACTTM circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
74AC
54AC
74AC
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
A
25 C
§
Units
Conditions
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.1
2.1
2.1
V
IH
OUT
b
2.25
2.75
3.15
3.85
3.15
3.85
3.15
3.85
V
V
V
or V
0.1V
CC
e
Maximum Low Level 3.0
1.5
0.9
0.9
0.9
V
OUT
0.1V
IL
b
Input Voltage
4.5
5.5
2.25
2.75
1.35
1.65
1.35
1.65
1.35
1.65
or V
0.1V
CC
e b
OUT
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
12 mA
V
V
I
24 mA
24 mA
OH
e
e
V
OL
Maximum Low Level 3.0
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
Output Voltage
4.5
5.5
*V
IN
V or V
IL IH
3.0
4.5
5.5
0.36
0.36
0.36
0.50
0.50
0.50
0.44
0.44
0.44
12 mA
V
I
24 mA
24 mA
OL
e
I
Maximum Input
Leakage Current
V
I
V , GND
CC
IN
g
g
g
1.0
5.5
0.1
1.0
mA
*All outputs loaded; thresholds on input associated with output under test.
4
DC Characteristics for ’AC Family Devices (Continued)
74AC
54AC
74AC
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
A
25 C
§
Units
Conditions
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
²
I
I
I
Minimum Dynamic
5.5
5.5
50
75
mA
mA
V
V
V
1.65V Max
OLD
OHD
CC
OLD
Output Current
b
b
e
3.85V Min
OHD
50
75
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
4.0
80.0
40.0
mA
or GND
²
Maximum test duration 2.0 ms, one output loaded at a time.
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
Note: I and I
IN
.
CC
CC
@ @
for 54AC 25 C is identical to 74AC 25 C.
§ §
I
CC
DC Characteristics for ’ACT Family Devices
74ACT
54ACT
74ACT
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
55 C to 125 C
b
a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
0.1V
IL
b
or V
CC
0.1V
e b
OUT
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
I
50 mA
OH
e
*V
IN
V
IL
or V
IH
b
b
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
24 mA
24 mA
V
V
I
OH
e
e
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
50 mA
OUT
*V
IN
V
or V
IL IH
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
24 mA
V
I
OL
24 mA
e
e
I
I
Maximum Input
Leakage Current
V
V
V
, GND
IN
I
CC
g
g
g
1.0
5.5
5.5
0.1
1.0
mA
mA
b
2.1V
Maximum
V
I
CCT
CC
0.6
1.6
50
1.5
75
I
/Input
CC
e
²
I
I
I
Minimum Dynamic
5.5
5.5
mA
mA
V
V
V
1.65V Max
e
3.85V Min
OLD
OHD
CC
OLD
Output Current
b
b
50
75
OHD
e
Maximum Quiescent
Supply Current
V
CC
IN
5.5
4.0
80.0
40.0
mA
or GND
*All outputs loaded; thresholds on input associated with output under test.
²
Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25 C is identical to 74ACT 25 C.
§ §
Note: I
CC
5
AC Electrical Characteristics
74AC
54AC
e b
74AC
e b
T
55 C
T
40 C
§
§
A
A
e a
A
V
*
T
25 C
§
50 pF
CC
a
a
Symbol
Parameter
to 125 C
to 85 C
Units
§
50 pF
§
50 pF
e
(V)
C
L
e
e
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
t
t
t
t
t
Maximum Clock
3.3
5.0
70
95
55
90
60
95
max
PLH
PHL
PLH
PHL
PLH
PHL
MHz
ns
Frequency
110
140
Propagation Delay, CP to Q
(PE Input HIGH or LOW)
3.3
5.0
2.0
1.5
7.5
5.5
12.5
9.0
1.0
1.5
13.5
9.5
1.5
1.0
13.5
9.5
n
Propagation Delay, CP to Q
(PE Input HIGH or LOW)
3.3
5.0
1.5
1.5
8.5
6.0
12.0
9.5
1.0
1.5
12.5
9.5
1.5
1.5
13.0
10.0
n
ns
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.5
7.0
15.0
10.5
1.0
1.5
16.5
11.0
2.5
1.5
16.5
11.5
ns
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
11.0
8.0
14.0
11.0
1.0
1.5
15.0
11.0
2.5
2.0
15.5
11.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
7.5
5.5
9.5
6.5
1.0
1.5
11.0
7.5
1.5
1.0
11.0
7.5
ns
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
8.5
6.0
11.0
8.5
1.0
1.5
12.0
9.0
2.0
1.5
12.5
9.5
ns
g
*Voltage Range 3.3 is 3.3V 0.3V
g
Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
74AC
e a
54AC
74AC
e b
e b
T
55 C
T
40 C
§
to 125 C
§
A
A
V
*
T
25 C
§
CC
A
a
a
Symbol
Parameter
to 85 C
§
Units
§
50 pF
e
(V)
C
50 pF
L
e
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
t
t
t
t
t
t
t
Setup Time, HIGH or LOW
3.3
5.0
5.5
4.0
13.5
8.5
17.0
11.0
16.0
10.5
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P
n
to CP
b
b
b
b
b
0.5
Hold Time, HIGH or LOW
to CP
3.3
5.0
7.0
5.0
1.0
0.5
h
s
P
0
0
0
n
Setup Time, HIGH or LOW
SR to CP
3.3
5.0
5.5
4.0
14.0
9.5
17.0
12.0
16.5
11.0
b
b
b
b
b
b
0.5
Hold Time, HIGH or LOW
SR to CP
3.3
5.0
7.5
5.5
1.0
0.5
0.5
h
s
0
0
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
5.5
4.0
11.5
7.5
16.0
9.5
14.0
8.5
b
b
b
b
b
b
0.5
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
7.5
5.0
1.0
0.5
0.5
h
s
0
0
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.5
2.5
6.0
8.0
5.5
7.0
5.0
4.5
b
b
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
4.5
3.0
0
0
0
0
h
w
w
0.5
0.5
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
3.0
3.5
2.5
5.0
5.0
4.0
3.0
2.0
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
3.0
2.0
4.0
3.0
5.0
5.0
4.5
3.5
g
*Voltage Range 3.3 is 3.3V 0.3V
g
Voltage Range 5.0 is 5.0V 0.5V
6
AC Electrical Characteristics
74ACT
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
e a
A
V
*
T
25 C
§
50 pF
CC
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
(V)
C
L
C
C
L
L
Min
Typ
Max
Min
Max
Min
Max
f
t
t
t
t
t
t
Maximum Clock
max
PLH
PHL
PLH
PHL
PLH
PHL
5.0
5.0
5.0
5.0
5.0
5.0
5.0
120
140
5.5
6.0
7.0
8.0
5.5
6.0
90
10.5
MHz
ns
Frequency
Propagation Delay, CP to Q
(PE Input HIGH or LOW)
n
1.5
1.5
2.5
3.0
2.0
2.0
10.0
11.0
11.5
13.5
9.0
1.5
1.5
1.5
1.5
1.5
1.5
10.5
10.5
12.5
13.0
9.5
1.5
1.5
2.0
2.0
1.5
2.0
11.0
12.0
13.5
15.0
10.5
11.0
Propagation Delay, CP to Q
(PE Input HIGH or LOW)
n
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
10.0
9.5
ns
g
*Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
74ACT
e a
54ACT
e b
74ACT
e b
40 C
T
55 C
T
§
to 125 C
§
A
A
V *
CC
(V)
T
25 C
§
A
a
e
a
Symbol
Parameter
to 85 C
Units
§
50 pF
§
e
C
50 pF
L
e
50 pF
C
C
L
L
Typ
Guaranteed Minimum
t
t
t
t
t
t
t
t
t
t
Setup Time, HIGH or LOW
s
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
4.0
10.0
13.5
12.0
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P
n
to CP
Hold Time, HIGH or LOW
to CP
h
s
b
5.0
0.5
0.5
13.5
0.0
P
n
Setup Time, HIGH or LOW
SR to CP
4.0
10.0
11.5
Hold Time, HIGH or LOW
SR to CP
h
s
b
b
b
0.5
5.5
5.5
3.0
0.5
Setup Time, HIGH or LOW
PE to CP
4.0
8.5
11.5
0.0
10.5
0
Hold Time, HIGH or LOW
PE to CP
h
s
b
b
0.5
Setup Time, HIGH or LOW
CEP or CET to CP
2.5
5.5
7.0
6.5
0.5
3.5
3.5
Hold Time, HIGH or LOW
CEP or CET to CP
h
w
w
b
0
0.5
Clock Pulse Width (Load)
HIGH or LOW
2.0
3.5
3.5
5.0
Clock Pulse Width
2.0
5.0
(Count) HIGH or LOW
g
*Voltage Range 5.0 is 5.0V 0.5V
7
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
e
C
C
Input Capacitance
4.5
pF
V
OPEN
5.0V
IN
CC
CC
Power Dissipation
Capacitance
PD
45.0
pF
V
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT 163
P
C
QR
Temperature Range Family
e
Special Variations
e
e
74AC
54AC
Commercial
Military
X
QR
Devices shipped in 13 reels
×
Commercial grade device with
burn-in
e
e
e
74ACT
54ACT
Commercial TTL-Compatible
Military TTL-Compatible
e
QB
Military grade device with
environmental and burn-in
processing shipped in tubes
Device Type
Package Code
Temperature Range
e
e
e
e
e
P
D
F
L
Plastic DIP
Ceramic DIP
Flatpak
Leadless Ceramic Chip Carrier (LCC)
Small Outline (SOIC)
e
e
b a
C
M
Commercial ( 40 C to 85 C)
§
§
b a
Military ( 55 C to 125 C)
§
§
S
Physical Dimensions inches (millimeters)
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
8
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
16-Lead Small Outline Integrated Circuit (S)
NS Package Number M16A
9
Physical Dimensions inches (millimeters) (Continued)
16-Lead Plastic Dual-In-Line Package (P)
NS Package Number N16E
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
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a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
54ACT16475WD
ACT SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, CDFP56, FINE PITCH, CERAMIC, FP-56
TI
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