54ACT16474 [TI]
18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 具有三态输出的18位寄存总线收发器![54ACT16474](http://pdffile.icpdf.com/pdf2/p00207/img/icpdf/54ACT1_1170787_icpdf.jpg)
型号: | 54ACT16474 |
厂家: | ![]() |
描述: | 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
文件: | 总7页 (文件大小:142K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢅ ꢉ ꢊꢋꢌ ꢄ ꢍꢎꢏ ꢌ ꢐꢄ ꢎꢍꢎꢑ ꢋꢒꢐ ꢄ ꢍꢂꢓꢐꢃ ꢎ ꢌꢔ ꢎ ꢍ
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SCAS238A − MAY 1992 − REVISED APRIL 1996
54ACT16474 . . . WD PACKAGE
74ACT16474 . . . DL PACKAGE
(TOP VIEW)
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
1OEAB
1CLKAB
1A1
1OEBA
1CLKBA
1
56
55
2
Flow-Through Architecture Optimizes
PCB Layout
3
54 1B1
53 GND
52 1B2
GND
1A2
4
D
Distributed V
and GND Pin
CC
5
Configurations Minimize High-Speed
Switching Noise
6
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1A3
1B3
7
V
V
CC
CC
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
8
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16474 are noninverting 18-bit registered
bus transceivers composed of two 9-bit sections
with separate control signals. For either 9-bit
transceiver section, data flow in the A-to-B mode
is controlled by output-enable (1OEAB or 2OEAB)
and clock (1CLKAB or 2CLKAB) inputs. When
1OEAB or 2OEAB is low, the corresponding
outputs are active (high or low) and take on either
the current data on low-to-high transition of
1CLKAB or 2CLKAB or the previously stored data
if 1CLKAB or 2CLKAB is low.
V
V
CC
CC
2A7
2A8
GND
2A9
2B7
2B8
GND
2B9
2CLKBA
2OEBA
2CLKAB
2OEAB
When 1OEAB or 2OEAB is high, the corresponding outputs are in the high-impedance state. 1OEAB or 2OEAB
does not affect the operation on the internal registers. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
Data flow from B to A is similar, but uses 1OEBA and/or 2OEBA and 1CLKBA and/or 2CLKBA.
The 74ACT16474 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16474 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16474 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
ꢒ ꢓ ꢚꢎꢐꢐ ꢘ ꢄꢖ ꢎꢍꢕ ꢌꢐ ꢎ ꢓ ꢘꢄꢎꢑ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢙꢍ ꢘ ꢑ ꢒ ꢃꢄ ꢌꢘ ꢓ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢁ ꢇꢁ ꢈ ꢇ ꢁꢂꢃ ꢄꢅ ꢆ ꢁ ꢇ ꢁ
ꢅꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢐꢄ ꢎꢍꢎ ꢑ ꢋꢒ ꢐ ꢄꢍ ꢂꢓ ꢐꢃ ꢎꢌ ꢔ ꢎ ꢍꢐ
ꢕꢌ ꢄ ꢖ ꢗ ꢊꢐꢄꢂꢄ ꢎ ꢘꢒꢄ ꢙ ꢒꢄꢐ
SCAS238A − MAY 1992 − REVISED APRIL 1996
†
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKAB
OEAB
A
X
X
H
L
X
L
↑
↑
H
L
L
L
Z
‡
B
0
H
L
†
A-to-B data flow is shown: B-to-A flow is
similar but uses CLKBA, and OEBA.
Output level before the indicated steady-
state input conditions were established
‡
§
logic symbol
2
1CLKAB
1OEAB
C1
EN2
C3
1
55
56
27
28
30
29
1CLKBA
1OEBA
EN4
C5
2CLKAB
EN6
C7
2OEAB
2CLKBA
EN8
2OEBA
1A1
3
54
1D
4
1
1
2
1B1
5D
5
52
51
49
48
47
45
44
43
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
6
8
9
10
12
13
14
15
42
2A1
5D
8
1
1
2B1
6
7D
16
17
19
20
21
23
24
26
41
40
38
37
36
34
33
31
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS238A − MAY 1992 − REVISED APRIL 1996
logic diagram (positive logic)
55
1CLKBA
56
1OEBA
1
1OEAB
2
1CLKAB
C1
1D
54
3
1A1
1B1
C1
1D
To Eight Other Channels
30
2CLKBA
29
2OEBA
28
2OEAB
27
2CLKAB
C1
1D
42
15
2A1
2B1
C1
1D
To Eight Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢁ ꢇꢁ ꢈ ꢇ ꢁꢂꢃ ꢄꢅ ꢆ ꢁ ꢇ ꢁ
ꢅꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢐꢄ ꢎꢍꢎ ꢑ ꢋꢒ ꢐ ꢄꢍ ꢂꢓ ꢐꢃ ꢎꢌ ꢔ ꢎ ꢍꢐ
ꢕꢌ ꢄ ꢖ ꢗ ꢊꢐꢄꢂꢄ ꢎ ꢘꢒꢄ ꢙ ꢒꢄꢐ
SCAS238A − MAY 1992 − REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mA
Maximum package power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16474
MIN NOM
74ACT16474
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
10
0
10
T
−55
125
−40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
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ꢅ ꢉ ꢊꢋꢌ ꢄ ꢍꢎꢏ ꢌ ꢐꢄ ꢎꢍꢎꢑ ꢋꢒꢐ ꢄ ꢍꢂꢓꢐꢃ ꢎ ꢌꢔ ꢎ ꢍ
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SCAS238A − MAY 1992 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16474
74ACT16474
PARAMETER
TEST CONDITIONS
= −50 µA
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
OH
5.4
5.4
5.4
3.94
4.94
3.8
3.8
V
V
OH
I
I
= −24 mA
OH
4.8
4.8
†
= −75 mA
3.85
3.85
OH
0.1
0.1
0.1
0.1
0.44
0.44
1.65
1
0.1
0.1
0.44
0.44
1.65
1
I
= 50 µA
OL
0.36
0.36
V
V
OL
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
Control inputs
V = V
or GND
0.1
0.5
8
µA
µA
µA
I
I
CC
‡
A or B ports
V
= V
or GND
5
5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
80
I
CC
One input at 3.4 V,
Other inputs at V
§
5.5 V
0.9
1
1
mA
∆I
CC
or GND
CC
or GND
C
C
Control inputs
A or B ports
V = V
I CC
5 V
5 V
3
pF
pF
i
V = V
O CC
or GND
11.5
io
†
‡
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
54ACT16474
74ACT16474
A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
Pulse duration
75
75
75
MHz
clock
CLK high
4
4
4
ns
w
CLK low
6.6
5.5
1
6.6
5.5
1
6.6
5.5
1
t
t
Setup time
Hold time
Data before CLK↑
Data after CLK↑
ns
ns
su
h
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
54ACT16474
74ACT16474
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
75
4
TYP
MAX
MIN
75
4
MAX
MIN
75
4
MAX
f
t
t
t
t
t
t
MHz
max
PLH
PHL
PZH
PZL
PHZ
PLZ
8
8
10.2
10.2
10.3
11.6
8.8
11.5
11.4
11.7
13.1
9.5
11.5
11.4
11.7
13.1
9.5
CLK
OE
A or B
A or B
A or B
ns
ns
ns
4.2
3
4.2
3
4.2
3
7.8
9.2
7.1
6.6
3.7
4.8
4.4
3.7
4.8
4.4
3.7
4.8
4.4
OE
8.4
9
9
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ꢃ
ꢄ
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ꢍ
ꢎ
ꢔ
ꢌ
ꢎ
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ꢥ
ꢧ
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ꢡ ꢜꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢁ ꢇꢁ ꢈ ꢇ ꢁꢂꢃ ꢄꢅ ꢆ ꢁ ꢇ ꢁ
ꢅꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢐꢄ ꢎꢍꢎ ꢑ ꢋꢒ ꢐ ꢄꢍ ꢂꢓ ꢐꢃ ꢎꢌ ꢔ ꢎ ꢍꢐ
ꢕꢌ ꢄ ꢖ ꢗ ꢊꢐꢄꢂꢄ ꢎ ꢘꢒꢄ ꢙ ꢒꢄꢐ
SCAS238A − MAY 1992 − REVISED APRIL 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
61
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
= 50 pF,
L
f = 1 MHz
pF
pd
37
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
Open
GND
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
Timing Input
Data Input
1.5 V
0 V
3 V
0 V
t
w
t
h
t
3 V
su
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
[ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
V
OL
OL
t
PHZ
t
PLH
t
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
80% V
CC
50% V
50% V
CC
CC
CC
[ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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