54ACT16475 [TI]
18-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS; 18位寄存收发器，三态输出
| 型号： | 54ACT16475 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢅ ꢉ ꢊꢋꢌ ꢄ ꢍꢎꢏ ꢌ ꢐꢄ ꢎꢍꢎꢑ ꢄ ꢍꢂꢒꢐ ꢃꢎ ꢌ ꢓꢎ ꢍ
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SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
54ACT16475 . . . WD PACKAGE
74ACT16475 . . . DL PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Inverting Outputs
1OEAB
1OEBA
1CLKBA
1B1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Flow-Through Architecture Optimizes
PCB Layout
1CLKAB
1A1
2
3
GND
1A2
GND
1B2
4
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
5
1A3
1B3
6
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
V
V
7
CC
CC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
8
9
125°C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Packaged in Plastic 300-mil Shrink
Small-Outline (DL) Packages Using 25-mil
Center-to-Center Pin Spacings and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Pin Spacings
description
The ’ACT16475 are 18-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. They can be used as two 9-bit
transceivers or one 18-bit transceiver. Separate
clock (CLKAB and CLKBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
V
V
CC
CC
2A7
2A8
GND
2A9
2B7
2B8
GND
2B9
2CLKBA
2OEBA
2CLKAB
2OEAB
Data at the A inputs meeting the setup time
requirements is transferred to the B outputs on the
positive-going edge of CLKAB. With OEAB low,
the 3-state B outputs are enabled and reflect the
inverted A data. Data flow from B to A is similar but
requires the use of the CLKBA and OEBA inputs.
The 74ACT16475 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16475 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16475 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
ꢘ ꢒ ꢚꢎꢐꢐ ꢗ ꢄꢕ ꢎꢍꢔ ꢌꢐ ꢎ ꢒ ꢗꢄꢎꢑ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢙꢍ ꢗ ꢑ ꢘ ꢃꢄ ꢌꢗ ꢒ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢁ ꢇꢀ ꢈ ꢇ ꢁꢂꢃ ꢄꢅ ꢆ ꢁ ꢇ ꢀ
ꢅꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢐꢄ ꢎꢍꢎ ꢑ ꢄꢍ ꢂꢒ ꢐꢃ ꢎꢌ ꢓ ꢎ ꢍꢐ
ꢔꢌ ꢄ ꢕ ꢖ ꢊꢐꢄꢂꢄ ꢎ ꢗꢘꢄ ꢙ ꢘꢄꢐ
SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
CLKAB
A
X
X
L
H
L
L
L
X
L
↑
↑
Z
‡
B
0
H
L
H
†
‡
A-to-B data flow is shown: B-to-A flow is
similar but uses CLKBA and OEBA.
Output level before the indicated
steady-state
established
input
conditions
were
§
logic symbol
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢔ ꢌꢄ ꢕ ꢖ ꢊꢐꢄꢂꢄ ꢎ ꢗ ꢘꢄ ꢙ ꢘꢄ
SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
2
1CLKAB
1OEAB
C1
EN2
C3
EN4
C5
EN6
C7
EN8
1
55
56
27
28
30
29
1CLKBA
1OEBA
2CLKAB
2OEAB
2CLKBA
2OEBA
1A1
3
54
1D
4
1
1
2
1B1
3D
5
52
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1B2
51
6
1B3
49
8
1B4
48
9
1B5
47
10
12
13
14
1B6
45
1B7
44
1B8
43
1B9
15
42
2A1
5D
8
1
1
2B1
6
7D
16
17
19
20
21
23
24
26
41
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2B2
40
2B3
38
2B4
37
2B5
36
2B6
34
2B7
33
2B8
31
2B9
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢁ ꢇꢀ ꢈ ꢇ ꢁꢂꢃ ꢄꢅ ꢆ ꢁ ꢇ ꢀ
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ꢔꢌ ꢄ ꢕ ꢖ ꢊꢐꢄꢂꢄ ꢎ ꢗꢘꢄ ꢙ ꢘꢄꢐ
SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
55
1CLKBA
56
1OEBA
1
1OEAB
2
1CLKAB
C1
1D
54
3
1A1
1B1
C1
1D
To Eight Other Channels
30
2CLKBA
29
2OEBA
28
2OEAB
27
2CLKAB
C1
1D
42
15
2A1
2B1
C1
1D
To Eight Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mA
Maximum power package dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 2)
54ACT16475
MIN NOM
74ACT16475
MIN NOM
UNIT
MAX
MAX
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
mA
mA
ns/V
°C
OH
OL
∆t/∆v
0
10
0
10
T
−55
125
−40
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄ ꢅꢆ ꢁ ꢇꢀ ꢈ ꢇ ꢁꢂꢃ ꢄꢅ ꢆ ꢁ ꢇ ꢀ
ꢅꢉ ꢊꢋꢌ ꢄ ꢍ ꢎꢏꢌ ꢐꢄ ꢎꢍꢎ ꢑ ꢄꢍ ꢂꢒ ꢐꢃ ꢎꢌ ꢓ ꢎ ꢍꢐ
ꢔꢌ ꢄ ꢕ ꢖ ꢊꢐꢄꢂꢄ ꢎ ꢗꢘꢄ ꢙ ꢘꢄꢐ
SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
54ACT16475
74ACT16475
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
I
= −50 µA
OH
5.4
5.4
5.4
3.94
4.94
3.8
3.8
V
V
OH
I
I
= −24 mA
OH
4.8
4.8
†
= −75 mA
3.85
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
0.36
0.36
0.44
0.44
1.65
1
0.44
0.44
1.65
1
V
V
OL
I
I
= 24 mA
OL
†
= 75 mA
OL
I
I
I
Control inputs V = V
or GND
0.1
0.5
8
µA
µA
µA
mA
I
I
CC
V
= V
or GND
O
CC
‡
A or B ports
5
80
1
5
80
1
OZ
5.5 V
5.5 V
V = V
or GND,
I
O
= 0
CC
I
CC
One input at 3.4 V,
Other inputs at V
§
5.5 V
0.9
∆I
CC
or GND
CC
or GND
C
C
Control inputs V = V
CC
5 V
5 V
4.5
12
pF
pF
i
I
A or B ports
V
= V or GND
CC
io
O
†
‡
§
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
For I/O ports, the parameter I includes the input leakage current.
OZ
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
timing requirements over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
54ACT16475
74ACT16475
A
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
Pulse duration
Setup time
75
75
75
MHz
ns
clock
CLK high or low
Data before CLK↑
Data after CLK↑
6.5
5.5
1.5
6.5
5.5
1.5
6.5
5.5
1.5
w
ns
su
h
Hold time
ns
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
54ACT16475
74ACT16475
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
75
TYP
MAX
MIN
75
MAX
MIN
75
MAX
f
t
t
t
t
t
t
MHz
max
PLH
PHL
PZH
PZL
PHZ
PLZ
3.8
4.2
2.8
3.4
5.2
4.5
7.9
8.1
7.3
7.4
6.5
6.6
11.1
11.4
11.4
13.1
9.8
3.8
4.2
2.8
3.4
5.2
4.5
12.5
12.6
12.8
14.8
10.5
9.8
3.8
4.2
2.8
3.4
5.2
4.5
12.5
12.6
12.8
14.8
10.5
9.8
CLKAB or CLKBA
OEAB or OEBA
OEAB or OEBA
B or A
B or A
B or A
ns
ns
ns
9.1
ꢙ
ꢍ
ꢗ
ꢑ
ꢘ
ꢃ
ꢄ
ꢙ
ꢍ
ꢎ
ꢓ
ꢌ
ꢎ
ꢔ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢛ
ꢞ
ꢟ ꢤ ꢞ ꢝ ꢰ ꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢱ ꢤ ꢫ ꢠꢩ ꢣꢤ ꢥ ꢛꢬ ꢃ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢱ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢰ
ꢥ
ꢰ
ꢠ
ꢦ
ꢫ
ꢞ
ꢬ
ꢄ
ꢤ
ꢭ
ꢦ
ꢞ
ꢌ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢛ
ꢞ
ꢨ
ꢡ ꢜ ꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢤ
ꢞ
ꢤ
ꢨ
ꢱ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢇ
ꢀ
ꢈ
ꢇ
ꢅ ꢉ ꢊꢋꢌ ꢄ ꢍꢎꢏ ꢌ ꢐꢄ ꢎꢍꢎꢑ ꢄ ꢍꢂꢒꢐ ꢃꢎ ꢌ ꢓꢎ ꢍ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢁ
ꢇ
ꢀ
ꢐ
ꢐ
ꢔ ꢌꢄ ꢕ ꢖ ꢊꢐꢄꢂꢄ ꢎ ꢗ ꢘꢄ ꢙ ꢘꢄ
SCAS198A − OCTOBER 1990 − REVISED APRIL 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
27
9
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per transceiver
C
= 50 pF,
L
f = 1 MHz
pF
pd
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
TEST
S1
S1
t
/t
Open
PLH PHL
/t
500 Ω
Open
GND
From Output
Under Test
t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
Timing Input
Data Input
1.5 V
0 V
3 V
0 V
t
w
t
h
t
3 V
su
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
[ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
V
OL
OL
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
80% V
CC
50% V
50% V
CC
CC
CC
[ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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相关型号：
54ACT16475WD
ACT SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, CDFP56, FINE PITCH, CERAMIC, FP-56
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