STW81103_技术文档

STW81103

Multi-band RF frequency synthesizer with integrated VCOs

Features

■ Integer-N frequency synthesizer

■ Dual differential integrated VCOs with

automatic center frequency calibration:

– 2500 - 3050 MHz (direct output)

– 4350 - 5000 MHz (direct output)

– 1250 - 1525 MHz (internal divider by 2)

– 2175 - 2500 MHz (internal divider by 2)

– 625 - 762.5 MHz (internal divider by 4)

– 1087.5 - 1250 MHz (internal divider by 4)

Applications

■ 2.5G and 3G Cellular infrastructure equipment

■ CATV equipment

■ Excellent integrated phase noise

■ Fast lock time: 150µs

■ Instrumentation and test equipment

■ Other wireless communication systems

■ Dual modulus programmable prescaler

(16/17 or 19/20)

■ 2 programmable counters to achieve a

feedback division ratio from 256 to 65551

(prescaler 16/17) and from 361 to 77836

(prescaler 19/20).

Description

The STMicroelectronics STW81103 is an

integrated RF synthesizer with voltage controlled

oscillators (VCOs). Showing high performance,

high integration, low power, and multi-band

performances, STW81103 is a low cost one chip

alternative to discrete PLL and VCOs solutions.

■ Programmable reference frequency divider

(10 bits)

■ Phase frequency comparator and charge pump

■ Programmable charge pump current

■ Digital lock detector

■ Dual digital bus interface: SPI and I²C bus (fast

mode) with 3 bit programmable address

(1100A₂A₁A₀)

STW81103 includes an Integer-N frequency

synthesizer and two fully integrated VCOs

featuring low phase noise performance and a

noise floor of -155dBc/Hz. The combination of

wide frequency range VCOs (thanks to center-

frequency calibration over 32 sub-bands) and

multiple output options (direct output, divided by 2

or divided by 4) allows to cover the

■ 3.3 V power supply

■ Power down mode (hardware and software)

■ Small size exposed pad VFQFPN28 package

625 MHz-762.5 MHz, the 1087.5 MHz-1525 MHz,

the 2175 MHz-3050 MHz and the

4350 MHz-5000 MHz bands.

5 mm x 5 mm x 1.0 mm

■ Process: BICMOS 0.35 µm SiGe

The STW81103 is designed with

STMicroelectronics advanced 0.35 µm SiGe

process.

March 2008

Rev 3

1/53

www.st.com

1

Contents

STW81103

Contents

1

Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1

2.2

2.3

2.4

2.5

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3

4

5

Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.8.1

5.8.2

5.8.3

VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.9

Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.9.1 Output buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.10 External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2

6

I C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1

General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/53

STW81103

Contents

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2

6.3

Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2

I C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3.1

6.3.2

6.3.3

Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4

VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7

SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1

7.2

7.3

General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3.1

VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4

8

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1

8.2

8.3

8.4

Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9

Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10

11

12

3/53

List of tables

STW81103

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Phase noise specification ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13}

Current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VCO A performances versus amplitude setting (Freq = 2.8 GHz) . . . . . . . . . . . . . . . . . . . 24

VCO B performances vs. amplitude setting (Freq = 4.7 GHz) . . . . . . . . . . . . . . . . . . . . . . 25

EXT_PD pin function setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Data and clock timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Write-only registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Address decoder and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Bits at 00h and ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Bits at 01h and ST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

4/53

STW81103

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

VCO A (direct output) closed loop phase noise at 2.775 GHz

(FSTEP=200 kHz; FPFD=200 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. VCO B (direct output) closed loop phase noise at 4.675 GHz

(FSTEP=200 kHz; FPFD=200 kHz; ICP=3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz

(FSTEP=200 kHz; FPFD=400 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz

(FSTEP=200 kHz; FPFD=400 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz

(FSTEP=200 kHz; FPFD=800 kHz; ICP=1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz

(FSTEP=200 kHz; FPFD=800 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. PFD frequency spurs (direct output; FPFD=200 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 14. Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA) . . . . . . . . . . . . . . . 17

Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21. START and STOP conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 26. SPI input and output bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41

Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42

Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43

Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43

Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44

Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44

Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45

Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46

Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 38. Application diagram with external VCO (LO output from STW81103) . . . . . . . . . . . . . . . . 49

Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49

Figure 40. VFQFPN28 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5/53

Block diagram and pin configuration

STW81103

1

Block diagram and pin configuration

1.1

Block diagram

Figure 1.

Block diagram

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6/53

STW81103

Block diagram and pin configuration

1.2

Pin configuration

Figure 2.

Pin connection (top view)

VDD_VCOA

VDD_DIV2

DBUS_SEL

VDD_BUFVCO

VDD_OUTBUF

OUTBUFP

EXTVCO_INP

EXTVCO_INN

QFN 28

VDD_PLL

REF_CLK

TEST2

OUTBUFN

VDD_DIV4

VDD_VCOB

Table 1.

Pin No

Pin description

Name

Description

Observation

1

2

3

4

5

6

7

8

9

VDD_VCOA

VDD_DIV2

VDD_OUTBUF

OUTBUFP

OUTBUFN

VDD_DIV4

VDD_VCOB

VDD_ESD

VCTRL

VCO A power supply

Divider by 2 power supply

Output buffer power supply

LO buffer positive output

LO buffer negative output

Divider by 4 power supply

VCO B power supply

Open collector

ESD positive rail power supply

VCO control voltage

7/53

Block diagram and pin configuration

STW81103

Table 1.

Pin No

Pin description (continued)

Name Description

ICP PLL charge pump output

Observation

10

11

12

External resistance connection for PLL

charge pump

REXT

VDD_CP

Power supply for charge pump

For test purposes only;

must be connected to

GND

13

14

15

TEST1

Test input 1

CMOS output

(I_OUT=4mA)

LOCK_DET

TEST2

Lock detector

Test input 2

For test purposes only;

must be connected to

GND

16

17

REF_CLK

VDD_PLL

Reference clock input

PLL digital power supply

For test purposes only;

must be connected to

GND

18

19

EXTVCO_INN

EXTVCO_INP

External VCO negative input

External VCO positive input

For test purposes only;

must be connected to

GND

20

21

22

VDD_BUFVCO VCO buffer power supply

DBUS_SEL

VDD_DBUS

Digital Bus Interface select

CMOS input

SPI and I²C bus power supply

Power down hardware

23

24

EXT_PD

CMOS input

‘0’ device ON; ‘1’ device OFF

CMOS Bidir Schmitt

triggered (I_OUT=4mA)

SDA/DATA

I2CBUS/SPI data line

CMOS input Schmitt

triggered

25

26

SCL/CLK

I2CBUS/SPI clock line

ADD0/LOAD

I2CBUS address select pin/ SPI load line

CMOS input

CMOS input; must be

connected to GND in SPI

mode

27

28

ADD1

ADD2

I2CBUS address select pin

CMOS input; must be

connected to GND in SPI

mode

8/53

STW81103

Electrical specifications

2

Electrical specifications

2.1

Absolute maximum ratings

Table 2.

Symbol

Absolute maximum ratings

Parameter

Values

Unit

AV_CC

DV_CC

T_stg

Analog supply voltage

Digital supply voltage

Storage temperature

0 to 4.6

+150

V

°C

Electrical static discharge

- HBM⁽¹⁾

4

ESD

- CDM-JEDEC standard

- MM

1.5

0.2

kV

1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800 V.

2.2

Operating conditions

Table 3.

Symbol

Operating conditions ⁽¹⁾

Parameter

Test conditions

Min.

Typ.

Max.

Units

AV_CC

DV_CC

Analog supply voltage

Digital supply voltage

3.0

3.3

3.6

V

V_DD1current

consumption

I_VDD1

I_VDD2

T_amb

T_j

90

12

mA

°C

V_DD2current

consumption

Operating ambient

temperature

-40

85

Maximum junction

temperature

125

°C

Junction to ambient

package thermal

resistance

R_{th j-a}

R_{th j-b}

R_{th j-c}

Multilayer JEDEC board

44

26.3

6.3

°C/W

Junction to board

package thermal

resistance

Junction to case

package thermal

resistance

1. Refer to Figure 36: Typical application diagram.

9/53

Electrical specifications

STW81103

2.3

Digital logic levels

Table 4.

Symbol

Digital logic levels

Parameter

Test conditions

Min.

Typ.

Max.

Units

V_il

Low-level input voltage

High-level input voltage

Schmitt trigger hysteresis

Low-level output voltage

High-level output voltage

0.2*Vdd

V

V_ih

0.8*Vdd

0.8

V_hyst

V_ol

0.4

V_oh

0.85*Vdd

2.4

Electrical specifications

All electrical specifications are intended for a 3.3 V supply voltage.

l

Table 5.

Symbol

Electrical specifications

Parameter

Condition

Min.

Typ.

Max.

Unit

Output frequency range

Direct output

2500

1250

625

3050

1525

762.5

5000

2500

1250

MHz

Output frequency range with

VCOA

F_OUTA

Divider by 2

Divider by 4

Direct output

Divider by 2

Divider by 4

4350

2175

1087.5

Output frequency range with

VCOB

F_OUTB

VCO dividers

VCO divider ratio

Prescaler 16/17

Prescaler 19/20

256

361

65551

77836

N

Reference clock and phase frequency detector

F_ref

Reference input frequency

Reference input sensitivity⁽¹⁾

Reference divider ratio

PFD input frequency

10

0.35

2

200

1.5

MHz

1

Vpeak

R

1023

16

F_PFD

MHz

F_OUT

65551

/

F_OUT

256

/

Prescaler 16/17

Prescaler 19/20

Hz

F_STEP

Frequency step⁽²⁾

F_OUT

/

F_OUT

/

77836

361

10/53

STW81103

Electrical specifications

Table 5.

Symbol

Electrical specifications (continued)

Parameter Condition

Min.

Typ.

Max.

Unit

Charge pump

I_CP

ICP sink/source⁽³⁾

3-bit programmable

5

mA

V

Output voltage compliance

range

V_OCP

0.4

V

_dd-0.3

Direct output (F_PFD=200 kHz)

Divider by 2 (F_PFD=400 kHz)

Divider by 4 (F_PFD=800 kHz)

-76

-82

-88

dBc

Spurious⁽⁴⁾

VCOs

Lower frequency range

Intermediate frequency range

Higher frequency range

Lower frequency range

Intermediate frequency range

Higher frequency range

VCO A

45

60

65

80

85

105

145

85

MHz/V

°C

K_VCOA

VCOA sensitivity⁽⁵⁾

VCOB sensitivity⁽⁵⁾

85

105

65

45

K_VCOB

60

80

100

130

85

100

Maximum temperature

variation for continuous

lock^{(5) (6)}

125

ΔT_LK

VCO B

95

°C

VCOA pushing⁽⁵⁾

4

7

21

3

MHz/V

V

VCOB pushing⁽⁵⁾

15

V_CTRL

VCO control voltage⁽⁵⁾

LO harmonic spurious⁽⁵⁾

0.4

-20

dBc

mA

F

_VCO=2.8 GHz; amplitude[11]

30

16

24

13

15

17

14

I_VCOA

VCOA current consumption

VCOB current consumption

F_VCO=2.8 GHz; amplitude[00]

mA

F

_VCO=4.7 GHz; amplitude[11]

_VCO=4.7 GHz; amplitude[00]

mA

I_VCOB

mA

I_VCOBUFVCO buffer consumption

mA

I_DIV2

I_DIV4

Divider by 2 consumption

Divider by 4 consumption

mA

LO output buffer

P_LO

R_L

Output level

Return loss

0

dBm

dB

Matched to 50 ohms

DIV4 Buff

15

26

23

39

mA

I_OUTBUFCurrent consumption

DIV2 Buff

Direct output

11/53

Electrical specifications

STW81103

Unit

Table 5.

Symbol

Electrical specifications (continued)

Parameter

Condition

Min.

Typ.

Max.

External VCO

Frequency range

0.625

-10

5.0

+6

GHz

dBm

mA

Input level

Current consumption

VCO internal buffer

28

PLL miscellaneous

Input buffer, prescaler, digital

dividers, misc.

I_PLL

t_lock

Current consumption

Lockup time^{(5) (7)}

12

mA

25 kHzPLLbandwidth;within

1 ppm of frequency error

150

μs

1. In order to achieve best phase noise performance 1 V peak level is suggested.

2. The frequency step is related to the PFD input frequency as follows:

- F

= F

for direct output

/2 for divided by 2 output

/4 for divided by 4 output

step

PFD

3. See relationship between ICP and REXT in Section 5.7: Charge pump.

4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop

BW.

5. Guaranteed by design and specification.

6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range

for the VCO covering the desired frequency. Once programmed at the initial temperature T inside the operating

0

temperature range (-40 ° C to +85 ° C), the synthesizer is able to maintain the lock status only if the temperature drift (in

either direction) is within the limit specified by ΔT , provided that the final temperature T is still inside the nominal range.

LK

1

If higher ΔT are required the ”VCO calibration auto-restart“ feature can be enabled, thus allowing to re-start the VCO

calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal).

7. Frequency jump from 2250 to 2400 MHz; it includes the time required by the VCO calibration procedure (7 F

cycles with

PFD

F

=400 kHz).

PFD

12/53

STW81103

Electrical specifications

2.5

Phase noise specification

Table 6.

Phase noise specification ⁽¹⁾

Parameter

Test conditions

Min.

Typ.

Max.

Unit

In-band phase noise floor – closed loop⁽²⁾

Normalized inband phase noise

floor

-222

dBc/Hz

Inband phase noise floor

direct output

-222+20log(N)+10log(F_PFD

-228+20log(N)+10log(F_PFD

-234+20log(N)+10log(F_PFD

)

ICP=4 mA, PLL BW=50 kHz;

including reference clock contribution

Inband phase noise floor

divider by 2

Inband phase noise floor

divider by 4

PLL integrated phase noise – direct output

-34.6

1.5

dBc

F

_OUT=4.675 GHz,

Integrated phase noise

100 Hz to 40 MHz

F_PFD=200 kHz, F_STEP=200 kHz,

PLL BW = 15 kHz, ICP=3 mA

° rms

PLL integrated phase noise – divider by 2

F

_OUT=2.3376 GHz,

-42.6

0.6

dBc

Integrated phase noise

100 Hz to 40 MHz

F_PFD=400 kHz, F_STEP=200 kHz,

PLL BW=25 kHz, ICP=2 mA

° rms

PLL integrated phase noise – divider by 4

F_OUT=1.1688 GHz,

F_PFD=800 kHz, F_STEP=200 kHz,

PLL BW=35 kHz, ICP=1.5 mA

-49.5

0.27

dBc

Integrated phase noise

100 Hz to 40 MHz

° rms

VCO A direct (2500 MHz-3050 MHz) – open loop⁽³⁾

Phase noise @ 1 kHz

Phase noise @ 10 kHz

Phase noise @ 100 kHz

Phase noise @ 1 MHz

Phase noise @ 10 MHz

Phase noise @ 40 MHz

-59

-87

dBc/Hz

-109

-131

-151

-161

VCO B direct (4350 MHz-5000 MHz) – open loop⁽³⁾

Phase noise @ 1 kHz

Phase noise @ 10 kHz

Phase noise @ 100 kHz

Phase noise @ 1 MHz

Phase noise @ 10 MHz

Phase noise @ 40 MHz

-54

-82

dBc/Hz

-105

-127

-147

-157

13/53

Electrical specifications

STW81103

Table 6.

Phase noise specification ⁽¹⁾(continued)

Parameter Test conditions

Min.

Typ.

Max.

Unit

VCO A with divider by 2 (1250 MHz-1525 MHz) – open loop⁽³⁾

Phase noise @ 1 kHz

-65

-93

dBc/Hz

Phase noise @ 10 kHz

Phase noise @ 100 kHz

-115

-137

-153

-155

Phase noise @ 1 MHz

Phase noise @ 10 MHz

Phase noise floor @ 40 MHz

VCO B with divider by 2 (2175 MHz-2500 MHz) – open loop⁽³⁾

Phase noise @ 1 kHz

-60

-88

dBc/Hz

Phase noise @ 10 kHz

Phase noise @ 100 kHz

-111

-132

-150

-154

Phase noise @ 1 MHz

Phase noise @ 10 MHz

Phase noise floor @ 40 MHz

VCO A with divider by 4 (625 MHz-762.5 MHz) – open loop⁽³⁾

Phase noise @ 1 kHz

-71

-99

dBc/Hz

Phase noise @ 10 kHz

Phase noise @ 100 kHz

-121

-142

-154

-155

Phase noise @ 1 MHz

Phase noise @ 10 MHz

Phase noise floor @ 40 MHz

VCO B with divider by 4 (1087.5 MHz-1250 MHz) – open loop⁽³⁾

Phase noise @ 1 kHz

-66

-94

dBc/Hz

Phase noise @ 10 kHz

Phase noise @ 100 kHz

-117

-138

-153

-154

Phase noise @ 1 MHz

Phase noise @ 10 MHz

Phase noise floor @ 40 MHz

1. Phase Noise SSB. VCO amplitude setting to value [11]. All closed-loop performances are specified using a reference clock

signal at 76.8 MHz with a phase noise of -135 dBc/Hz @1 kHz offset, -145dBc/Hz @10kHz offset and -149.5 dBc/Hz of

noise floor.

2. Normalized PN = Measured PN – 20log(N) – 10log(F

comparison frequency at the PFD input.

), where N is the VCO divider ratio (N=B*P+A) and F

is the

PFD

3. Typical phase noise at centre band frequency.

An evaluation kit is available upon request, including a powerful simulation tool

(STWPLLSim) that allows a very accurate estimation of the device’s phase noise according

to the desired project parameters (VCO frequency, selected output stage, reference clock,

frequency step, and so on); refer to Section 8: Application information for more details.

14/53

STW81103

Typical performance characteristics

3

Typical performance characteristics

Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop

measurements are done with F_STEP=200 kHz, with the F_PFDand charge pump current

properly set. The loop filter configuration is depicted in Figure 36: Typical application

diagram, and the reference clock signal is at 76.8 MHz with a phase noise of -135 dBc/Hz

@1 kHz offset, -145 dBc/Hz @10 kHz offset and -149.5 dBc/Hz of noise floor.

Figure 3.

VCO A (direct output) open loop

phase noise

Figure 4.

VCO B (direct output) open loop

phase noise

Figure 5.

VCO A (direct output) closed loop Figure 6.

phase noise at 2.775 GHz

VCO B (direct output) closed loop

phase noise at 4.675 GHz

(F_STEP=200 kHz; F_PFD=200 kHz;

I_CP=2 mA)

I_CP=3 mA)

1.5° rms

1.0° rms

15/53

Typical performance characteristics

STW81103

Figure 7.

VCO A (div. by 2 output) closed

loop phase noise at 1.3876 GHz

(F_STEP=200 kHz; F_PFD=400 kHz;

Figure 8.

VCO B (div. by 2 output) closed

loop phase noise at 2.3376 GHz

(F_STEP=200 kHz; F_PFD=400 kHz;

I_CP=1.5 mA)

I_CP=2 mA)

0.6° rms

0.4° rms

Figure 9.

VCO A (div. by 4 output) closed

loop phase noise at 693.8 MHz

(F_STEP=200 kHz; F_PFD=800 kHz;

Figure 10. VCO B (div. by 4 output) closed

loop phase noise at 1168.8 MHz

(F_STEP=200 kHz; F_PFD=800 kHz;

I_CP=1 mA)

I_CP=1.5 mA)

0.19° rms

0.27° rms

16/53

STW81103

Typical performance characteristics

Figure 11. PFD frequency spurs (direct

output; F_PFD=200 kHz)

Figure 12. PFD frequency spurs (div. by 2

output; F_PFD=400 kHz)

-84 dBc

@400KHz

-76 dBc

@200KHz

Figure 13. PFD frequency spurs (div. by 4

output; F_PFD=800 kHz)

Figure 14. Settling time (final frequency=2.4

GHz; F_PFD=400 kHz; I_CP=2.5 mA)

< -90 dBc

@800KHz

17/53

General description

STW81103

4

General description

Figure 1: Block diagram shows the separate blocks that, when integrated, form an Integer-N

PLL frequency synthesizer.

The STW81103 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a

divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit

programmable reference divider, two programmable counters and a programmable dual-

modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual-

modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P

+A. The division ratio of both reference and VCO dividers is controlled through the selected

digital interface (I²C bus or SPI).

The digital interface type is selected through the proper hardware connection of pin

DBUS_SEL (0 V for I²C bus, 3.3 V for SPI).

All devices operate with a power supply of 3.3 V, and can be powered down when not in use.

18/53

STW81103

Circuit description

5

Circuit description

5.1

Reference input stage

The reference input stage is shown in Figure 15. The resistor network feeds a DC bias at the

_refinput, while the inverter used as the frequency reference buffer is AC coupled.

F

Figure 15. Reference frequency input buffer

VDD

F

ref

INV

BUF

Power Down

5.2

5.3

Reference divider

The 10-bit programmable reference counter allows division of the input reference frequency

to produce the input clock to the PFD. The division ratio is programmed through the digital

interface.

Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it

down to a manageable frequency for the CMOS A and B counters. The modulus P is

programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5

core whose division ratio depends on the state of the modulus input.

19/53

Circuit description

STW81103

5.4

A and B counters

The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus

(16/17 or 19/20) prescaler, allow the generation of output frequencies that are spaced only

by the reference frequency divided by the reference division ratio. The division ratio and the

VCO output frequency are given by the following formulas:

N = B x P + A

(B × P + A)

-----------------------------

× F

F

=

VCO

ref

R

where

F

_VCO: output frequency of VCO

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface)

B: division ratio of the main counter

A: division ratio of the swallow counter

F_ref: input reference frequency

R: division ratio of the reference counter

N: division ratio of the PLL

For the VCO divider to work correctly, B absolutely must be greater than A, which can take

any value ranging from 0 to 31. The value range of N is either from 256 to 65551 (if P=16) or

from 361 to 77836 (P=19).

Figure 16. VCO divider diagram

VCOBUF-

Prescaler

16/17 or 19/20

VCOBUF+

To PFD

modulus

5-bit

12-bit

A-counter

B-counter

20/53

STW81103

Circuit description

5.5

Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output

proportional to the phase error. The PFD includes a delay gate that controls the width of the

anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer

function.

Figure 17 is a simplified schematic of the PFD.

Figure 17. PFD diagram

VDD

Up

D FF

R

F

ref

Delay

R

F

ref

VDD

D FF

Down

ABL

5.6

5.7

Lock detect

This signal indicates that the difference between rising edges of both UP and DOWN PFD

signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is

high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes

current only during PLL transients.

Charge pump

This block drives two matched current sources, I_UPand I_DOWN, which are controlled

respectively by UP and DOWN PFD outputs. The nominal value of the output current is

controlled by an external resistor (connected to the REXT input pin) and a 3-bit word that

allows selection among 8 different values.

The minimum value of the output current is: I_MIN= 2*VBG/REXT (VBG~1.17 V)

21/53

Circuit description

Table 7.

STW81103

Current value vs. selection

CPSEL2

CPSEL1

CPSEL0

Current

Value for REXT=4.7 KΩ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I_MIN

0.5 mA

1.0 mA

1.5 mA

2.0 mA

2.5 mA

3.0 mA

3.5 mA

4.0 mA

2*I_MIN

3*I_MIN

4*I_MIN

5*I_MIN

6*I_MIN

7*I_MIN

8*I_MIN

Note:

The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are

forced to VDD/2.

Figure 18. Loop filter connection

VDD

VCTRL

BUF

C3

R3

Charge

Pump

ICP

R1

C1

C2

BUF

Cal bit

22/53

STW81103

Circuit description

5.8

Voltage controlled oscillators

5.8.1

VCO selection

The STW81103 integrates two low-noise VCOs to cover a wide band from:

●

2500 MHz to 3050 MHz and from 4350 MHz to 5000 MHz (direct output)

1250 MHz to 1525 MHz and from 2175 MHz to 2500 MHz (selecting divider by 2)

625 MHz to 762.5 MHz and from 1087.5 MHz to 1250 MHz (selecting divider by 4)

The frequency range is 2500 MHz-3050 MHz for VCO A, and 4350 MHz-5000 MHz for VCO

B.

5.8.2

VCO frequency calibration

Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting

capacitors from the resonator. These frequency ranges are intended to cover the wide band

of operation and compensate for process variation on the VCO center frequency.

The range is automatically selected when the SERCAL bit is set to 1. The charge pump is

inhibited, and the ICP and VCTRL pins are at VDD/2 volts. The ranges are then tested with

this VCO input voltage to select the one nearest to the desired output frequency

(F_OUT= N*F_ref/R).

After this selection, the SERCAL bit is automatically reset to 0 and the charge pump is once

again enabled. To enable a fast settle, the PLL needs only to perform fine adjustments

around VDD/2 on the loop filter to reach F_OUT

.

Figure 19. VCO sub-bands frequency characteristics

23/53

Circuit description

STW81103

The SERCAL bit should be set to “1” at each division ratio change. The VCO calibration

procedure takes approximately 7 periods of the PFD frequency.

The maximum allowed F_PFDto perform the calibration process is 1 MHz. When using a

higher F_PFD, follow the steps below:

1. Calibrate the VCO at the desired frequency with an F_PFDless than 1 MHz.

2. Set the ratio of the A, B and R dividers for the desired F_PFD

.

VCO calibration auto-restart feature

The VCO calibration auto-restart feature, once activated, allows to restart the calibration

procedure when the lock detector reports that the PLL has moved to an unlock condition

(trigger on ‘1’ to ‘0’ transition of lock detector signal).

This situation could happen if the device experiences a significant temperature variation.

Once programmed at the initial temperature T₀inside the operating temperature range

(-40 °C to +85 °C), the synthesizer is able to maintain the lock status only if the temperature

drift (in either direction) is within the limit specified by the ΔT_LKparameter, provided that the

final temperature T₁is still inside the nominal range.

Each VCO featured by STW81103 has its specific ΔT_LKparameter reported in Table 5, that

is typically lower than the maximum allowable drift (ΔT_MAX=125; from -40 °C to +85 °C and

vice versa).

By enabling the VCO calibration auto-restart feature (through the CAL_AUTOSTART_EN

bit), the part will be able to select again the proper VCO frequency sub-range if the

temperature drift exceeds the ΔT_LKlimit, without any external user command.

5.8.3

VCO voltage amplitude control

The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated

programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise,

whereas lower amplitudes save power.

Table 8 gives the voltage swing level expected on the resonator nodes, the current

consumption, and the phase noise at 1 MHz.

Table 8.

VCO A performances versus amplitude setting (Freq = 2.8 GHz)

Differential

voltage swing (Vp)

Current

consumption (mA)

PLL_A[1:0]

PN @1 MHz (dBc/Hz)

00

01

10

11

1.1

1.3

1.9

2.1

16

19

27

30

-126

-127

-130

-131

24/53

STW81103

Circuit description

Table 9.

VCO B performances vs. amplitude setting (Freq = 4.7 GHz)

Differential

voltage swing (Vp)

Current

consumption (mA)

PN at 1 MHz

(dBc/Hz)

PLL_A[1:0]

00

01

10

11

1.1

1.3

1.9

2.1

13

15

22

24

-121

-122

-126

-127

5.9

Output stage

The differential output signal of the synthesizer can be selected by software among three

different signal paths (direct, divider by 2 and divider by 4) providing multi-band capability.

The selection of the output stage is done by programming properly the PD[4:0] bits.

The output stage is an open-collector structure which is able to meet different requirements

over the desired output frequency range by proper connections on the PCB. Refer to

Section 8: Application information for more details on PCB connections.

5.9.1

Output buffer control mode

This control mode allows to enable/disable the output stage by a hardware control pin

(EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very

fast switching time is achieved.

This feature can be useful in designing a ping-pong architecture saving the cost of an

external RF switch.

The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in

Table 10.

Table 10. EXT_PD pin function setting

OUTBUF_CTRL_EN

Function of the EXT_PD pin

EXT_PD pin settings

EXT_PD = 0 V Î Device ON

0

Device hardware power down

EXT_PD = 3.3 V Î Device OFF

EXT_PD = 0 V Î Output Stage ON

EXT_PD = 3.3 V Î Output Stage OFF

1

Output Buffer control

25/53

Circuit description

STW81103

5.10

External VCO buffer

Although the main benefits of the STW81103 are the two wideband and low-noise VCOs,

the capability to use an external VCO is also provided.

The external VCO buffer is able to manage a signal coming from an external VCO in order to

build a synthesizer using the STW81103 only as PLL IC. The output signal of the

synthesizer can also be taken from the output section of the STW81103 (direct, divided by 2

or divided by 4 by) by properly setting the PD[4:0] bits, thus providing additional flexibility.

The external VCO signal can range from 625 MHz up to 5 GHz and its minimum power level

must be -10 dBm.

26/53

STW81103

I²C bus interface

6

I²C bus interface

The I²C bus interface is selected by hardware connection of pin #21 (DBUS_SEL) to 0 V.

Data is transmitted from microprocessor to the STW81103 through the 2-wire (SDA and

SCL) I²C bus interface. The STW81103 is always a slave device.

The I²C bus protocol defines any device that sends data on the bus as a transmitter, and

any device that reads the data as a receiver. The device controlling the data transfer is the

master, and the others are slaves. The master always initiates the transfer and provides the

serial clock for synchronization.

The STW81103 I²C bus supports Fast Mode operation (clock frequency up to 1MHz).

6.1

General features

6.1.1

Data validity

Data changes on the SDA line must only occur when the SCL is low. SDA transitions while

the clock is high are used to identify a START or STOP condition.

Figure 20. Data validity

SDA

SCL

Data line

Stable data

Valid

Change

data

allowed

6.1.2

START and STOP conditions

START condition

A START condition is identified by a transition of the data bus SDA from high to low while the

clock signal SCL is stable in the high state. A START condition must precede any data

transfer command.

STOP condition

A STOP condition is identified by a transition of the data bus SDA from low to high while the

clock signal SCL is stable in the high state. A STOP condition terminates communications

between the STW81103 and the bus master.

27/53

I²C bus interface

Figure 21. START and STOP conditions

STW81103

SCL

SDA

START

STOP

6.1.3

Byte format and acknowledge

Every byte put on the SDA line must be 8 bits long, starting with the most significant bit

(MSB), and be followed by an acknowledge bit to indicate a successful data transfer.

The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock

pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data.

Figure 22. Byte format and acknowledge

SCL

SDA

1

2

3

7

8

9

//

MSB

Acknowledgement

from receiver

START

6.1.4

Device addressing

The master must first initiate with a START condition to communicate with the STW81103,

and then send 8 bits (MSB first) on the SDA line which correspond to the device select

address and the read or write mode.

The first seven MSBs are the device address identifier, which corresponds to the I²C bus

definition. For the STW81103, the address is set at “1100A₂A₁A₀”, 3 bits programmable.

The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and

to 0 in write mode.

Following a START condition, the STW81103 identifies the device address on the bus and, if

matched, acknowledges the identification on the SDA bus during the 9th clock pulse.

28/53

STW81103

I²C bus interface

6.1.5

Single-byte write mode

Following a START condition, the master sends a device select code with the RW bit set to

0. The STW81103 sends an acknowledge and waits for the 1-byte internal sub-address that

provides access to the internal registers.

After receiving the sub-address internal byte, the STW81103 again responds with an

acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE

register, a single-byte write with sub-address 04H changes the CONTROL register, and so

on.

Table 11. Single-byte write mode

S

1100A₂A₁A₀

0

ack

sub-address byte

ack

DATA IN

ack

P

6.1.6

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data

bytes, and each one is acknowledged. The master terminates the transfer by generating a

STOP condition.

The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H

and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H),

and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81103

registers.

Table 12. Multi-byte write mode

S

1100A₂A₁A₀

0

ack sub-address byte ack DATA IN ack ……. DATA IN ack

P

6.1.7

Current byte address read mode

In the current byte address read mode, following a START condition, the master sends the

device address with the RW bit set to 1. Note that no sub-address is needed since there is

only one read register. The STW81103 acknowledges this and outputs the data byte. The

master does not acknowledge the received byte, and terminates the transfer with a STOP

condition.

Table 13. Current byte address read mode

S

1100A₂A₁A₀

1

ack

DATA OUT

No ack

P

29/53

I²C bus interface

STW81103

6.2

Timing specification

Figure 23. Data and clock

SDA

SCL

t

cwl

ch

t

cs

cwh

Table 14. Data and clock timing specifications

Symbol

Parameter

Data to clock setup time

Minimum time

Units

t_cs

t_ch

t_cwh

t_cwl

2

ns

Data to clock hold time

Clock pulse width high

Clock pulse width low

10

5

Figure 24. Start and stop

SDA

SCL

t

start

stop

30/53

STW81103

I²C bus interface

Table 15. Start and stop timing specifications

Symbol

Parameter

Clock to data start time

Minimum time

Units

t_start

t_stop

2

ns

Data to clock down stop time

Figure 25. Ack

SDA

8

9

SCL

t

d2

d1

Table 16. Ack timing specifications

Symbol

Parameter

Minimum time

Units

t_d1

t_d2

Ack begin delay

Ack end delay

2

ns

31/53

I²C bus interface

2

STW81103

6.3

I C registers

The STW81103 has 6 write-only registers and 1 read-only register.

6.3.1

Write-only registers

Table 17 gives a short description of the write-only registers.

Table 17. Write-only registers

HEX code

DEC code

Description

FUNCTIONAL_MODE

0x00

0x01

0x02

0x03

0x04

0x05

0

1

2

3

4

5

B_COUNTER

A_COUNTER

REF_DIVIDER

CONTROL

CALIBRATION

FUNCTIONAL_MODE

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

PD0

b0

OUTBUF_CTRL_EN CAL_AUTOSTART_EN PD4

PD3

PD2

PD1

B11

OUTBUF_CTRL_EN:

Output buffer control mode enable (0 = Off; 1 = ON)

CAL_AUTOSTART_EN: VCO calibration auto-restart enable (0 = Off; 1 = ON)

The bits PD[4:0] allow to select different functional modes for the STW81103 synthesizer

according to the Table 18.

Table 18. Functional modes

Decimal value PD[6:0] Description

0

1

2

3

4

5

6

7

8

9

Power down mode

Enable VCO A, output frequency divided by 2

Enable VCO B, output frequency divided by 2

Enable external VCO, output frequency divided by 2

Enable VCO A, output frequency divided by 4

Enable VCO B, output frequency divided by 4

Enable external VCO, output frequency divided by 4

Enable VCO A, direct output

Enable VCO B, direct output

Enable external VCO, direct output

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STW81103

I²C bus interface

B_COUNTER

MSB

LSB

b7

b6

b5

b4

B7

b3

B6

b2

B5

b1

b0

B3

B10

B9

B8

B4

B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register)

A_COUNTER

MSB

LSB

b7

B2

b6

b5

b4

A4

b3

A3

b2

A2

b1

b0

A0

B1

B0

A1

Bits B[2:0] for B_COUNTER, A_COUNTER values.

REF_DIVIDER

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

b0

R9

R8

R7

R6

R5

R4

R3

R2

Reference clock divider ratio R[9:1] (bits R1, R0 in the next register).

CONTROL

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

b0

R1

R0

PLL_A1

PLL_A0

CPSEL2

CPSEL1

CPSEL0 PSC_SEL

The CONTROL register is used to set the charge pump current, the VCO output voltage

amplitude and the prescaler modulus:

PLL_A[1:0]: VCO amplitude

CPSEL[2:0]: charge pump output current

PSC_SEL:

prescaler modulus select ('0' for P=16, '1' for P=19)

The LO output frequency is programmed by setting the proper values for A, B and R

according to the following formula:

F

REF – CLK

----------------------------------

F

= D × (B × P + A) ×

OUT

R

1

for direct output

where D_Requals

0.5 for output divided by 2

0.25 for output divided by 4

{

and P is the selected prescaler modulus.

33/53

I²C bus interface

CALIBRATION

STW81103

LSB

MSB

b7

b6

b5

b4

b3

b2

b1

b0

INITCAL SERCAL SELEXTCAL

CAL4

CAL3

CAL2

CAL1

CAL0

This register controls the VCO calibrator using the following values:

INITCAL:

SERCAL:

for test purposes only, must be set to 0

at 1 starts the VCO auto-calibration (automatically reset to 0 at the end of calibration)

SELEXTCAL: for test purposes only; must be set to 0

CAL[4:0]: for test purposes only; must be set to 0

6.3.2

Read-only register

MSB

LSB

b7

b6

b5

b4

b3

b2

b1

b0

DEV_ID1 DEV_ID0 LOCK_DET INTCAL4 INTCAL3 INTCAL2 INTCAL1 INTCAL0

This register is automatically addressed in the ‘current byte address read mode’, using the

following values:

DEV_ID[1:0]: device identifier bits; returns ‘10’

LOCK_DET: 1 when PLL is locked

INTCAL[4:0]: internal value of the VCO control word

6.3.3

Default configuration

At power on, all the bits are set to '0'. Consequently the part starts in power down mode.

34/53

STW81103

I²C bus interface

6.4

VCO calibration procedure

Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION

register bit[6]) is set to 1.

To program the device properly while ensuring VCO calibration, perform the following steps

before every channel change:

1. Program all the registers using a multi-byte write sequence with the desired settings

(functional mode, B and A counters, R counter, VCO amplitude, charge pump,

prescaler modulus), and all the bits of the CALIBRATION register (05H) set to 0.

2. Program the CALIBRATION register using a single-byte write sequence (subaddress

05H) with the SERCAL bit set to 1.

The maximum allowed PFD frequency (F_PFD) during calibration is 1 MHz; if you want a F_PFD

higher than 1 MHz, perform the following additional steps:

●

Perform all the steps of the calibration procedure, making sure to program the desired

VCO frequency with proper settings for the R, B and A counters so that F_PFDis ≤1 MHz.

●

Program the device with the desired VCO and PFD frequency settings according to

step 1) above.

6.4.1

VCO calibration auto-restart feature

The VCO calibration auto-restart feature can be enabled in two steps:

1. set the desired frequency ensuring VCO calibration as described above (section 6.4)

2. program the FUNCTIONAL_MODE register (sub-address 00H) using a single-byte

write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged

the others.

35/53

SPI digital interface

STW81103

7

SPI digital interface

7.1

General features

The SPI digital interface is selected by hardware connection of pin #21 (DBUS_SEL) to

3.3 V.

The STW81103 IC is programmed by means of a high-speed serial-to-parallel interface with

write option only. The 3-wire bus can be clocked at a frequency as high as 100 MHz to allow

fast programming of the registers containing the data for RF IC configuration.

The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs

represent the address of the registers, and the 24 LSBs represent the value of the registers.

Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.

The outputs of the selected register are sent to the device on the rising edge of the LOAD

signal.

Figure 26. SPI input and output bit order

Last bit sent

(LSB)0

2

23

25(MSB)

24

1

DATA

A1

LOAD

Address

decoder

D23 (MSB)

LOAD #4

D0 (LSB)

Reg.#0

Reg.#1

Reg.#4

36/53

STW81103

SPI digital interface

LSB

Table 19. SPI data structure (MSB is sent first)

MSB

Address

Data for register (24 bits)

A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 20. Address decoder and outputs

Address

Outputs

Function

A1

A0

DATABITS D23-D0 No

Name

Reference divider, VCO amplitude, VCO calibration,

charge pump current, prescaler modulus

0

24

0

ST1

0

1

0

1

24

1

2

3

ST2

ST3

ST4

Functional modes, VCO dividers

Reserved

7.2

Timing specification

Figure 27. SPI timing specification

tsetup thold

MSB

MSB-1

LSB

Data

t

clk_loadf

Clock

tdk

Load

t

clk_loadr

tload

Table 21. SPI timing specification

Symbol Parameter

t_setupDATA to CLOCK setup time

Min.

Typ.

Max.

Units

0.8

0.2

10

3

ns

t_hold

DATA to CLOCK hold time

CLOCK cycle period

t_clk

t_load

LOAD pulse width

t_{clk_loadr}

t_{clk_loadf}

CLOCK to LOAD rising edge

CLOCK to LOAD falling edge

2

0.5

37/53

SPI digital interface

STW81103

7.3

Bit tables

Table 22. Bits at 00h and ST1

Serial interface address = 00h

Register name = ST1

Description

Bit

Name

[23]

[22]

[21]

[20]

[19]

[18]

[17]

[16]

[15]

[14]

[13]

[12]

[11]

[10]

[9]

R9

R8

R7

R6

R5

Reference clock divider ratio

R4

R3

R2

R1

R0

PLL_A1

PLL_A0

CPSEL2

CPSEL1

CPSEL0

PSC_SEL

INITCAL

SERCAL

SELEXTCAL

CAL4

CAL3

CAL2

CAL1

CAL0

VCO amplitude control

Charge pump output current control

[8]

Prescaler modulus select (0 for P=16, 1 for P=19)

For test purposes only; must be set to 0

Enable VCO calibration (see Section 7.4)

For test purposes only; must be set to ‘0’

[7]

[6]

[5]

[4]

[3]

[2]

For test purposes only; must be set to ‘0’

[1]

[0]

38/53

STW81103

SPI digital interface

Table 23. Bits at 01h and ST2

Serial interface address = 01h

Register name = ST2

Bit

[23]

[22]

[21]

[20]

[19]

[18]

Name

Description

OUTBUF_CTRL_EN

Output buffer control mode enable (0 = Off, 1 = On)

VCO calibration auto restart enable (0 = Off, 1 = On)

CAL_AUTOSTART_EN

Device functional modes:

PD4

PD3

PD2

PD1

0. Power down

1. Enable VCO A, output frequency divided by 2

2. Enable VCO B, output frequency divided by 2

3. Enable external VCO, output frequency divided by 2

4. Enable VCO A, output frequency divided by 4

5. Enable VCO B, output frequency divided by 4

6. Enable external VCO, output frequency divided by 4

7. Enable VCO A, direct output

[17]

PD0

8. Enable VCO B, direct output

9. Enable external VCO, direct output

[16]

[15]

[14]

[13]

[12]

[11]

[10]

[9]

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

A4

A3

A2

A1

A0

B_COUNTER bits

[8]

[7]

[6]

[5]

[4]

[3]

[2]

A_COUNTER bits

[1]

[0]

39/53

SPI digital interface

STW81103

The LO output frequency is programmed by setting the proper value for A, B and R

according to the following formula:

F

REF – CLK

----------------------------------

= D × (B × P + A) ×

F

OUT

R

1

for direct output

where D equals

0.5 for output divided by 2

0.25 for output divided by 4

R

{

and P is the selected prescaler modulus.

7.3.1

Default configuration

At power on, all the bits are set to '0'. Consequently the part starts in power down mode.

7.4

VCO calibration procedure

Calibration of the VCO center frequency is activated when the SERCAL bit (ST1 register

bit[6]) is set to 1.

To program the device properly while ensuring VCO calibration, perform the following steps

before every channel change:

1. Program the ST2 register with the desired settings (functional mode, B and A

counters).

2. Program the ST1 register with the desired settings (R counter, VCO amplitude, charge

pump, prescaler modulus) and with the SERCAL bit set to 1.

The maximum allowed PFD frequency (F_PFD) during calibration is 1 MHz; if you want a F_PFD

higher than 1 MHz, perform the following additional steps:

●

Perform all the steps (step 1 and 2 above) of the calibration procedure, making sure to

program the desired VCO frequency with proper settings of the R, B and A counters so

that F_PFDis ≤1 MHz.

Program the device with the desired VCO and PFD frequency settings as per steps 1

and 2 above with SERCAL bit set to 0.

7.4.1

VCO calibration auto-restart feature

The VCO calibration auto-restart feature can be enabled in two steps:

1. Set the desired frequency ensuring VCO calibration as described above (Section 7.4)

2. Program the ST2 register with the CAL_AUTOSTART_EN bit set to '1' while keeping

unchanged the others.

40/53

STW81103

Application information

8

Application information

The STW81103 features three different alternately selectable bands: direct output (2.5 to

3.05 GHz and 4.35 to 5.0 GHz), divided by 2 (1.25 to 1.525 GHz and 2.175 to 2.5 GHz) and

divided by 4 (625 to 762.5 MHz and 1087.5 to 1250 MHz). To achieve a suitable power level,

a good matching network is necessary to adapt the output stage to a 50Ω load. Moreover,

since most commercial RF components have single-ended input and output terminations, a

differential to single-ended conversion may be required.

The different matching configurations shown below for each of the three bands are

suggested as a guideline when designing your own application board.

Inside the evaluation kit is the ADS design for each matching configuration suggested in this

chapter. The name of the corresponding ADS design is given in each figure.

The ADS designs provide only a first indication of the output stage matching, and should be

reworked according to the choices of layout, board substrate, components and so on.

The ADS designs of the evaluation boards are provided with a complete electromagnetic

modelling (board, components, and so on).

8.1

Direct output

If you do not need a differential to single conversion, you can match the output buffer of the

STW81103 in the simple way shown in Figure 28. This illustrates the differential to single-

ended output network in the 2.5 - 5.0 GHz range (MATCH_LC_LUMP_4G_DIFF.dsn).

Figure 28. Differential/single-ended output network

(MATCH_LC_LUMP_4G_DIFF.dsn)

Vcc

100 ohm

5.5nH

50 ohm

10pF

RF

OUTP

RF

OUTN

50 ohm

100 ohm

5.5nH

Vcc

Since most discrete components for microwave applications are single-ended, you can

easily use one of the two outputs and terminate the other one to 50Ωwith a 3 dB power loss.

41/53

Application information

STW81103

Alternatively, you can combine the two outputs in other ways. A first topology for the direct

output (2.5 to 5.0 GHz) is suggested in Figure 29. It basically consists of a simple LC balun

and a matching network to adapt the output to a 50Ωload. The two LC networks shift output

signal phase of -90° and +90°, thus combining the two outputs. This topology, designed for a

center frequency of 4 GHz, is intrinsically narrow-band since the LC balun is tuned at a

single frequency. If the application requires a different sub-band, the LC combiner can be

easily tuned to the frequency of interest.

Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn)

Vcc

0.8pF

50 ohm

1.9nH

RF

OUTP

0.8pF

1.9nH

2.5pF

50 ohm

RF

OUTN

0.8pF

50 ohm

1.9nH

0.8pF

Vcc

The 1.9 nH shunt inductor works as a DC feed for one of the open collector terminals as well

as a matching element along with the other components. The 1.9 nH series inductors are

used to resonate the parasitic capacitance of the chip.

For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and

0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths

to minimize losses and undesired impedance shift.

An alternative topology that permits a more broadband matching as well as balanced to

unbalanced conversion, is shown in Figure 30.

42/53

STW81103

Application information

Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn)

Vcc

50 ohm

5.5nH

12pF

4.7pF

RF

OUTP

2:1

12pF

1pF

1.2pF

50 ohm

RF

OUTN

50 ohm

5.5nH

Vcc

For differential to single conversion, the 50 to 100Ω Johanson balun is recommended

(3700BL15B100).

8.2

Divided by 2 output

If your application does not require a balanced to unbalanced conversion, the output

matching reduces to the simple circuit shown below (Figure 31), which illustrates a

differential to single-ended output network in the 1.25 - 2.5 GHz range

(MATCH_LC_LUMP_2G_DIFF.dsn). You can easily use this solution to provide one single-

ended output that terminates the other output at 50Ω with a 3 dB power loss.

Figure 31. Differential/single-ended output network

(MATCH_LC_LUMP_2G_DIFF.dsn)

Vcc

50 ohm

22nH

50 ohm

10pF

RF

OUTP

RF

OUTN

50 ohm

22nH

Vcc

43/53

Application information

STW81103

A first solution to combine the differential outputs is the lumped LC type balun tuned in the

2 GHz band (Figure 32).

Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn)

Vcc

2pF

50 ohm

2.7nH

RF

OUTP

2pF

3pF

2.7nH

50 ohm

3nH

RF

OUTN

2pF

50 ohm

2.7nH

2pF

Vcc

The same recommendation for the SMD components also applies to the divided by 2 output.

Another topology suited to combining the two outputs for the divided by 2 frequencies is

represented in Figure 33.

Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn)

Vcc

50 ohm

5.5nH

22pF

1.9nH

RF

OUTP

2:1

22pF

1.2pF

50 ohm

RF

OUTN

50 ohm

5.5nH

Vcc

44/53

STW81103

Application information

For differential to single conversion, the 50 to 100Ω Johanson balun (1600BL15B100) is

recommended.

8.3

Divided by 4 output

The topology, components, values and considerations of Figure 31 also apply to the divided

by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn).

As for the previous sections, a solution to combine the differential outputs is the lumped LC

type balun tuned in the 1 GHz band (Figure 34).

Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn)

Vcc

25 ohm

4pF

5.5nH

RF

OUTP

4pF

6pF

5.5nH

14nH

50 ohm

RF

OUTN

4pF

25 ohm

4pF

5.5nH

Vcc

If you prefer to use an RF balun, you can adapt the topology depicted in Figure 33, and

change the balun and the matching components (Figure 35). The suggested balun for the

0.625 - 1.25 GHz frequency range is the 1:1 Johanson 900BL15C050.

45/53

Application information

STW81103

Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn)

Vcc

25 ohm

18nH

8.2pF

22pF

2.1nH

RF

OUTP

1:1

8.2pF

18nH

0.5pF

50 ohm

RF

OUTN

25 ohm

Vcc

8.4

Evaluation kit

An evaluation kit can be delivered upon request, including the following:

●

Evaluation board

GUI (graphical user interface) to program the device

Measured S parameters of the RF output

ADS2005 schematics providing guidelines for application board design

STWPLLSim software for PLL loop filter design and noise simulation

Application programming interface (API)

Three different evaluation kits are available, each optimized for one of the following

frequency ranges:

●

1 GHz

2 GHz

4 GHz

When ordering, please specify one of the following order codes:

Table 24. Order code of the evaluation kit

Part number

STW81103-EVB1G

Description

1 GHz frequency range - divider by 4 output optimized

2 GHz frequency range - divider by 2 output optimized

4 GHz frequency range - direct output optimized

STW81103-EVB2G

STW81103-EVB4G

The three evaluation kits differ only for the output stage network and can be adapted from

one frequency band variant to a different one replacing properly the matching components

and the balun.

46/53

STW81103

Application diagram

9

Application diagram

Figure 36. Typical application diagram

From/to microcontroller

100

15p

I2C

VDD

1

1n

22p

10P

VDD_VCOA

VDD_DIV2

DBUS_SEL

VDD_BUFVCO

SPI

VDD

2

VDD

1

VDD_OUTBUF

OUTBUFP

EXTVCO_INP

EXTVCO_INN

RF Out

1n

22p

10P

STW81103

VDD_PLL

OUTBUFN

ref clk

REF_CLK

VDD_DIV4

VDD

1.8n

51

1

VDD_VCOB

TEST2

VDD

1

1n

22p

10P

4.7K

VDD

1

2.2K

2.7n

8.2K

68p

1n

22p

10µ

270p

loop filter

to microcontroller

Note:

1

See Section 8: Application information for further information on output matching topology.

2

EXT_PD, ADD2, ADD1 (and ADD0 when the I²C bus is selected) can be hard wired directly

on the board.

3

4

Loop filter values are for F_STEP= 200 kHz.

For best performance VDD₁must be a low noise supply (20 µV_RMSin 10 Hz-100 kHz BW).

47/53

Application diagram

Figure 37. Ping-pong architecture diagram

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2

See Section 8: Application information for further information on output matching topology.

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on the board.

3

4

Loop filter values are for F_STEP= 200 kHz.

For best performance VDD_{1_1}and VDD_{1_2}must be low noise supplies

(20 μV_RMSin 10 Hz-100 KHz BW).

48/53

STW81103

Application diagram

Figure 38. Application diagram with external VCO (LO output from STW81103)

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49/53

Package mechanical data

STW81103

10

Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK^®

packages, which have a lead-free second level interconnect. The category of second level

interconnect is marked on the package and on the inner box label, in compliance with

JEDEC standard JESD97. The maximum ratings related to soldering conditions are also

marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: http://www.st.com.

Figure 40. VFQFPN28 mechanical drawing

Note:

1

2

VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.

(Very thin: A=1.00 Max)

Details of the terminal 1 identifier are optional, but if given, must be located on the top

surface of the package by using either a mold or marked features.

50/53

STW81103

Package mechanical data

Table 25. Package dimensions

Ref.

Min.

Typ.

Max.

Unit

A

A1

A2

A3

b

0.800

0.900

0.020

0.650

0.200

0.250

5.000

4.750

3.100

5.000

4.750

3.100

0.500

0.550

1.000

0.050

1.000

mm

0.180

4.850

0.300

5.150

mm

D

mm

D1

D2

E

mm

2.950

4.850

3.250

5.150

mm

E1

E2

e

mm

2.950

0.350

3.250

mm

L

0.750

0.600

14

mm

P

mm

K

degrees

mm

ddd

0.080

51/53

Ordering information

STW81103

11

Ordering information

Table 26. Order codes

Part number

Temp range, ° C

Package

VFQFPN28

Packing

STW81103AT

-40 to 85

Tray

Tape and reel

STW81103ATR

12

Revision history

Table 27. Document revision history

Date

Revision

Changes

18-Jul-2007

1

Initial release.

Added Chapter 8: Application information. Modified Section 6.4:

VCO calibration procedure, and pin #23 description in Table 1.

14-Aug-2007

2

Updated Table 1: Pin description.

Updated Table 2: Absolute maximum ratings, Table 3: Operating

conditions, Table 5: Electrical specifications and Table 6: Phase

noise specification.

Updated Section 5.8.2: VCO frequency calibration.

Added VCO calibration auto-restart feature.

Updated Section 5.8.3: VCO voltage amplitude control.

Added Section 5.9: Output stage and Section 5.10: External VCO

buffer.

Updated FUNCTIONAL_MODE and CALIBRATION registers.

Added Section 6.3.3: Default configuration.

28-Mar-2008

3

Updated Section 6.4: VCO calibration procedure and added

Section 6.4.1: VCO calibration auto-restart feature.

Updated Table 23: Bits at 01h and ST2.

Added Section 7.3.1: Default configuration.

Updated Section 7.4: VCO calibration procedure and added

Section 7.4.1: VCO calibration auto-restart feature.

Added ‘Application program interface API’ item in Section 8.4.

Modified notes after Figure 36.

Added Figure 37, Figure 38 and Figure 39.

Modified Figure 40.

52/53

STW81103

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53/53


型号：	STW81103
厂家：	ST
描述：	Multi-band RF frequency synthesizer with integrated VCOs 多频段RF频率合成器与集成的VCO
文件：	总53页 (文件大小：1344K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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