STW82100B_技术文档

STW82100B

RF down converter with embedded integer-N synthesizer

Datasheet −production data

Features

■ High linearity:

– IIP3: +25.5 dBm

– 2FRF-2FLO spurious rejection: 77 dBc

VFQFPN-44

■ Noise figure:

Applications

– NF: 10.5 dB

■ Cellular infrastructure equipment:

– IF sampling receivers

■ Conversion gain

– CG: 8 dB

– Digital PA linearization loops

■ RF range: 1620 MHz to 2400 MHz

■ Other wireless communication systems.

■ Wide IF amplifier frequency range: 70 MHz to

400 MHz

Table 1.

Device summary

■ Integrated RF balun with internal matching

Part number

Package

Packaging

Tray

Tape and reel

■ Dual differential integrated VCOs with

STW82100B

VFQFPN-44

automatic center frequency calibration:

STW82100BTR

– LOA: 1650 to 1950 MHz

– LOB: 2050 to 2370 MHz

Description

■ Embedded integer-N synthesizer

– Dual modulus programmable prescaler

(16/17 or 19/20)

– Programmable reference frequency divider

(10 bits)

The STMicroelectronics STW82100B is an

integrated down converter providing 8 dB of gain,

10.5 dB NF, and a very high input linearity by

means of its passive mixer.

– Adjustable charge pump current

– Digital lock detector

– Excellent integrated phase noise

– Fast lock time: 150 µs

Embedding two wide band auto calibrating VCOs

and an integer-N synthesizer, the STW82100B is

suitable for both Rx and Tx requirements for

Cellular infrastructure equipment.

The integrated RF balun and internal matching

permit direct 50 ohm single-ended interface to RF

port. The IF output is suitable for driving 200-ohm

impedance filters.

■ Integrated DAC with dual current output

■ Supply: 3.3 V and 5 V analog,

3.3 V Digital

2

■ Dual digital bus interface: SPI and I C bus (fast

By embedding a DAC with dual current output to

drive an external PIN diode attenuator, the

STW82100B replaces several costly discrete

components and offers a significant footprint

reduction.

mode) with 3 bit programmable address

(1101A A A )

2

1 0

■ Process: 0.35 µm BICMOS SiGe

o

■ Operating temperature range -40 to +85 C

The STW82100B device is designed with

STMicroelectronics advanced 0.35 µm

SiGe process. Its performance is specified over a

-40 °C to +85 °C temperature range.

■ 44-lead exposed pad VFQFPN

package7x7x1.0 mm

May 2012

Doc ID 018355 Rev 5

1/67

This is information on a product in full production.

www.st.com

1

Contents

STW82100B

Contents

1

2

3

4

5

6

7

8

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1

Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8.1.1

8.1.2

8.1.3

8.1.4

8.1.5

8.1.6

8.1.7

8.1.8

8.1.9

Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mute until lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1.10 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.11 External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1.12 Mixer and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1.13 Dual output current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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9

I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1

I²C general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.1.7

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.2

I²C timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9.2.1

9.2.2

9.2.3

Data and clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2

I C START and STOP timing specification . . . . . . . . . . . . . . . . . . . . . . 36

2

I C acknowledge timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.3

9.4

I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2

9.3.1

I C register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2

9.3.2

I C register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Device calibration through the I²C interface . . . . . . . . . . . . . . . . . . . . . . . 45

2

9.4.1

9.4.2

9.4.3

VCO calibration procedure (I C interface) . . . . . . . . . . . . . . . . . . . . . . . 45

2

Power ON sequence (I C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2

VCO calibration auto-restart procedure (I C interface) . . . . . . . . . . . . . 46

10

SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 SPI general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 SPI timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.2.1 Data, clock and load timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.3 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.1 SPI register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3.2 SPI register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.4 Device calibration through the SPI interface . . . . . . . . . . . . . . . . . . . . . . 53

10.4.1 VCO calibration procedure (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . 53

10.4.2 Power ON sequence (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.4.3 VCO calibration auto-restart procedure (SPI interface) . . . . . . . . . . . . . 54

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Contents

STW82100B

11

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.2 Standard Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.3 Diversity mode operation with same LO frequency . . . . . . . . . . . . . . . . . 58

11.4 Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . 59

11.5 External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.6 External VCO diversity mode operation with same LO . . . . . . . . . . . . . . 61

12

13

14

Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Down converter mixer and IF amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . 15

Pin diode attenuator driver (dual output current DAC) electrical characteristics. . . . . . . . . 16

Integer-N synthesizer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Phase noise performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Current values for CPSEL[2:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

VCOA performance against amplitude setting (frequency = 3.6 GHz) . . . . . . . . . . . . . . . . 30

VCOB performance against amplitude setting (frequency = 4.3 GHz) . . . . . . . . . . . . . . . . 30

Suggested CAP[2:0] values for LO Frequency range mixer. . . . . . . . . . . . . . . . . . . . . . . . 31

Linearity performance against IFAMP[1:0] configuration (typical condition). . . . . . . . . . . . 32

2

I C data and clock timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2

I C START and STOP timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2

I C acknowledge timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2

I C register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Address decoder and outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

SPI register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Application circuit component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Evaluation kit order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

VFQFPN-44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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List of figures

STW82100B

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

STW82100B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

STW82100B pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Conversion gain against RF frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Noise figure against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

IIP3 against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2RF-2LO response against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

LOA (VCOA div. by 2) closed-loop phase noise at 1.8 GHz

(F

= 200 kHz, I = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STEP

CP

Figure 8.

LOB (VCOB div. by 2) closed-loop phase noise at 2.2 GHz

(F = 200 kHz, I = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

STEP

CP

Figure 9.

Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 12. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13. VCO typical sub-band characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. Data validity waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 15. START and STOP condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 16. Byte format and acknowledge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2

Figure 17. I C data and clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2

Figure 18. I C START and STOP timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2

Figure 19. I C acknowledge timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2

Figure 20. I C first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 21. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22. SPI data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 23. SPI timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 24. SPI first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. Typical STW82100B application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 26. Standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27. Diversity mode operation with same LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 28. Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29. External VCO standard mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 30. External VCO diversity mode operation with same LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 31. VFQFPN-44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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1

Block diagram

Figure 1.

STW82100B block diagram

VDD_RFESD

VSS_RFESD

DAC

IF_OUTP

IF_OUTN

RF_IN

IF

AMP

RF_VSS

RF_CT

MIXDRV_CT

DBUS_SEL

VDD_MIXDRV

VSS_MIXDRV

MIX

DRV

SDA/DATA

SCL/CLK

DBUS

VDD_DIV

VSS_DIV

LOAD

ADD0

ADD1

ADD2

VCO

calibrator

VDD_OUTBUF

VSS_OUTBUF

LO

DIV2

OUT

CAL_VCO

VDD_DIG

VSS_DIG

OUTBUFN

OUTBUFP

LOCK_DET

LO/2xLO

OUT

VCO

divider

UP

DN

EXTVCO_INP

EXTVCO_INN

EXT

LO/VCO

BUF

PFD

CHP

ICP

REF

divider

VDD_VCO

VSS_VCO

VCO

BUFF

VDD_PLL

VSS_PLL

VDD_IO

VSS_IO

BUF

CAL_VCO

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Pin description

STW82100B

2

Pin description

Figure 2.

STW82100B pin configuration

44 43 42 41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

VDD_DAC

REXT_DAC

VDD_DIV

VDD_IFAMP

1

2

IF_OUTP

IF_OUTN

NC

3

VDD_VCO

4

EXTVCO_INN

EXTVCO_INP

EXT_PD

ADD2

LOAD

5

STW82100B

VFQFPN44

SCL/CLK

SDA/DATA

VDD_DIG

DBUS_SEL

VDD_PLL

REF_CLK

6

7

8

9

ADD1

10

11

ADD0

VDD_IO

12

13

14

15

16

17

18

19

20

21

22

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Pin description

Table 2.

Pin list

Name

Pin No

Description

DAC power supply

Observation

1

2

3

4

VDD_DAC

REXT_DAC

VDD_DIV

Vsupply analog1= 3.3 V

External resistance connection for DAC

Divider by 2 power supply

-

Vsupply analog1= 3.3 V

VDD_VCO

VCOs and External VCO Buffer power supply Vsupply analog1= 3.3 V

Diversity Slave Mode and External

5

EXTVCO_INN

External VCO (LO) negative input

VCO Modes; otherwise it must be

connected to GND

Diversity Slave Mode and External

VCO Modes; otherwise it must be

connected to GND

6

7

EXTVCO_INP

EXT_PD

External VCO (LO) positive input

Hardware power down:

CMOS Input

‘0’ device ON; ‘1’ device OFF

8

ADD2

I²CBUS address select pin

Digital IO power supply

CMOS Input

9

ADD1

CMOS Input

10

11

12

13

14

15

16

17

18

19

ADD0

CMOS Input

VDD_IO

VDD_PSCBUF

NC

Vsupply digital = 3.3 V

Prescaler input buffer power supply

Not connected

Vsupply analog1= 3.3 V

-

NC

Not connected

-

VDD_OUTBUF

OUTBUFN

OUTBUFP

VCTRL

ICP

Power supply for LO buffer

LO Output buffer negative output

LO Output buffer positive output

Control voltage for VCOs

PLL charge pump output

Vsupply analog1=3.3 V

Open collector @3.3 V

Open collector @ 3.3 V

-

External resistance connection for PLL charge

pump current

20

REXT_CP

-

21

22

23

24

25

26

27

28

29

30

31

VDD_CP

LOCK_DET

REF_CLK

VDD_PLL

DBUS_SEL

VDD_DIG

SDA/DATA

SCL/CLK

LOAD

Power supply for charge pump

Lock detector

Vsupply analog1= 3.3 V

CMOS Output

Reference frequency input

PLL digital power supply

Digital Bus Interface select

Power supply for digital bus interface

I²CBUS /SPI data line

I²CBUS /SPI clock line

SPI load line

-

Vsupply analog1= 3.3 V

CMOS Input

Vsupply digital = 3.3 V

CMOS Bidir Schmitt triggered

CMOS Input Schmitt triggered

-

NC

Not connected

IF_OUTN

IF amplifier negative output

Open collector @ 5 V⁽¹⁾

Doc ID 018355 Rev 5

9/67

Pin description

STW82100B

Table 2.

Pin list (continued)

Name

IF_OUTP

Pin No

32

Description

IF Amplifier positive output

Observation

Open collector @ 5 V⁽¹⁾

33

VDD_IFAMP

TEST2

IF Amplifier power supply

Test input 2

Vsupply analog1 = 3.3 V

Test purpose only; it must be

connected to GND

34

35

36

Test purpose only; it must be

connected to GND

TEST1

Test input 1

Test output

Test purpose only; it must be

connected to GND

TEST_ALC

37

38

39

40

41

42

RF_CT

RF balun central tap

-

RF_IN

RF input

-

VDD_RFESD

MIXDRV_CT

VDD_ALC

VDD_MIXDRV

RF ESD positive rail power supply

Mixer driver balun central tap

ALC power supply

Vsupply analog1 = 3.3 V

Vsupply analog2 = 5 V⁽¹⁾

Vsupply analog1 = 3.3 V

Mixer driver power supply

DAC current output for external PIN Diode

attenuator

43

44

I_PINDRV1

I_PINDRV2

PMOS Open drain

DAC current output for external PIN Diode

attenuator

1. Supply voltage @ 3.3 V in low-current mode operation

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Doc ID 018355 Rev 5

STW82100B

3

Absolute maximum ratings

Table 3.

Absolute maximum ratings

Symbol

Parameter

Analog Supply voltage

Values

0 to 4.6

0 to 6

0 to 4.6

+150

0.8

Unit

AVCC1

AVCC2

DVCC

Tstg

V

Analog Supply voltage

V

Digital Supply voltage

V

Storage temperature

°C

HBM on pins 16, 17, 31, 32, 37, 40

HBM on pin 38

1

HBM on all remaining pins

CDM-JEDEC Standard on pin 38

CDM-JEDEC Standard on all remaining pins

MM

2

ESD

kV

(Electro-static discharge)

0.25

0.5

0.2

Doc ID 018355 Rev 5

11/67

Operating conditions

STW82100B

4

Operating conditions

Table 4.

Symbol

Operating conditions

Parameter

Test conditions

Min

Typ

Max

Unit

AVCC1

AVCC2

DVCC

Analog Supply voltage

Digital Supply voltage

-

3.15

3.3

5

3.45

5.25

3.45

V

4.75

V

3.15

3.3

130

110

105

155

Standard mode

-

150 mA

130 mA

120 mA

180 mA

External VCO standard mode

Diversity slave mode

Diversity master mode

I_CC3.3V

Current Consumption at 3.3 V

Current Consumption

External VCO diversity master

mode

-

140

160 mA

High current mode at 5 V

-

170

100

195 mA

115 mA

I_CC5V

Low current mode at 3.3 V

T_A

T_J

Operating ambient temperature

Maximum junction temperature

-

-40

-

85

°C

125 °C

Junction to ambient package thermal

resistance⁽¹⁾

Θ

Multi-layer JEDEC board

-

33

19

3

-

°C/W

JA

Junction to board package thermal

resistance⁽¹⁾

Θ

°C/W

JB

Junction to case package thermal

resistance⁽¹⁾

Θ

JC

Thermal characterization parameter

junction to board⁽¹⁾

Ψ

18

0.3

JB

Thermal characterization parameter

junction to top case⁽¹⁾

Ψ

JT

1. Refer to JEDEC standard JESD 51-12 for a detailed description of the thermal resistances and thermal parameters.

Data here presented are referring to a Multi-layer board according to JEDEC standard.

T_J= T_A+ Θ_JA* Pdiss (in order to estimate T_Jif ambient temperature T_Aand dissipated power Pdiss are known)

T_J= T_B+ ΨJ_B* Pdiss (in order to estimate T_Jif board temperature T_Band dissipated power Pdiss are known)

T_J= T_T+ ΨJ_T* Pdiss (in order to estimate T_Jif top case temperature T_Tand dissipated power Pdiss are known)

12/67

Doc ID 018355 Rev 5

STW82100B

Operating conditions

T

Table 5.

Digital logic levels

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Vil

Low level input voltage

High level input voltage

Schmitt trigger hysteresis

Low level output voltage

High level output voltage

-

0.8*Vdd

0.8

-

0.2*Vdd

V

Vih

-

V

Vhyst

Vol

-

0.4

-

Voh

0.85*Vdd

Doc ID 018355 Rev 5

13/67

Test conditions

STW82100B

5

Test conditions

Unless otherwise specified the following test conditions are applied:

●

Vsupply digital = 3.3 V

Vsupply analog1 = 3.3 V

Vsupply analog2 = 5 V

F

= 150 MHz

IF

MIX = 0111

T ambient = 27 °C

Refer also to Section 11: Application information.

14/67

Doc ID 018355 Rev 5

STW82100B

Electrical characteristics

6

Electrical characteristics

Note:

Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, F = 2100 MHz,

RF

F

= 1950 MHz, T = +25 *C, RF power = 0 dBm, unless otherwise specified.

LO

A

)

(1)

Table 6.

Down converter mixer and IF amplifier electrical characteristics

Parameter Conditions

RF Frequency

Symbol

Min Typ Max Unit

F_RF

-

1620

1650

2050

70

-

2400 MHz

1950 MHz

2370 MHz

400 MHz

VCOA divided by 2

VCOB divided by 2

F_IF= ABS(F_LO-F_RF)

F_LO

LO Frequency

F_IF

IF Center Frequency⁽²⁾

Power Conversion Gain

Rin = 50 ohm, Rout = 200 ohm

RFin = 0 dBm

CG

7.5

-

8

8.5 dB

Power Conversion Gain over

Temperature⁽³⁾

CG_ΔT

IP_1dB

T= -40 to +85 °C

0.7

-

dB

High current Mode

Low current Mode

High current Mode

Low current Mode

-

13.5

8

-

Input P1dB

dBm

24.5 25.5

18.5 19.5

Third-order input intercept

point⁽⁴⁾

IIP3

dBm

IIP3 variation over

temperature⁽³⁾

IIP3_ΔT

T= -40 to +85 °C

-

0.5

77

-

dB

2F_RF-2F_LOF_RFin= -5 dBm,

F_IF= 150 MHz

dBc

nF_RF-nF_LOSpurious rejection at IF⁽³⁾

3F_RF-3F_LOF_RFin= -5 dBm,

F_IF= 150 MHz

77

High-current mode, MIX = 0011

-

10.5

-35

-33

-29

58

11 dB

NF_SSB

Noise figure

Low-current mode, MIX = 0011

1xLO

-

dBm

-

LO to IF Leakage

2xLO

-

LO to RF Leakage

RF to IF Isolation

RF Return Loss

IF Return Loss

-

dBm

dB

-

RF_RL

IF_RL

Matched to 50 ohm

Matched to 200 ohm

20

dB

25

dB

Maximum deviation from F_cover 10

MHz. For any F_cwithin each TX

observation path band.

-0.05

-0.10

-

+0.05 dB

+0.10 dB

Gain Flatness for TX

observation path⁽⁵⁾

-

Maximum deviation from F_cover 30

MHz. For any F_cwithin each TX

observation path band.

Doc ID 018355 Rev 5

15/67

Electrical characteristics

STW82100B

(1)

Table 6.

Down converter mixer and IF amplifier electrical characteristics (continued)

Symbol

Parameter

Conditions

Min Typ Max Unit

Maximum deviation from linear phase

at F_cover 10 MHz. For any F_cwithin -0.3

each TX observation path band.

-

+0.3 deg

+0.7 deg

Phase Flatness for TX

observation path⁽⁵⁾

-

Maximum deviation from linear phase

at F_cover 30 MHz. For any F_cwithin -0.7

each TX observation path band.

Maximum ripple over a 4 MHz band.

For any F_cwithin each RX path band.

dB

pk-pk

-

Gain Flatness for RX path⁽⁵⁾

Phase Flatness for RX path⁽⁵⁾

-

0.1

Maximum ripple over a 4 MHz band.

For any F_cwithin each RX path band.

deg

pk-pk

-

0.6

3.3 V Supply (pin 41, 42)

5 V Supply (pin 40)

-

49

60

20

-

mA

Mixer Driver Current

Consumption

ICC_MD

Mixer Driver Current

Consumption (Low Current

Mode)

3.3 V Supply (pin 41, 42)

3.3 V Supply (pin 40)

-

35

-

mA

3.3 V Supply (pin 33)

5 V Supply (pin 31, 32)

3.3 V Supply (pin 33)

3.3 V Supply (pin 31, 32)

-

10

108

6

-

mA

IFAMP Current Consumption

ICC_IFAM

IFAMP Current Consumption

(Low Current Mode)

55

1. All linearity and NF performances are intended at maximum LO amplitude (LO_A[1:0]=[11]), tuning capacitors (CAP[2:0])

programmed according to the selected frequency, mixer bias (MIX[3:0]) set to maximize performance and the device

operated in high current mode. The performances of conversion gain, NF and linearity are intended at the SMA connectors

of a typical application board.

2. The IF frequency range supported by the IF Amplifier is from 70 to 400 MHz. The exact IF frequency range supported for a

specific RF frequency can be calculated as F_IF= ABS(F_LO-F_RF) where F_LOis inside the specified LO frequency range.

3. Guaranteed by design and characterization

4. RFin = 0 dBm/tone, RF tone spacing = 5 MHz

5. Guaranteed by design

Table 7.

Symbol

Pin diode attenuator driver (dual output current DAC) electrical characteristics

Parameters

Resolution

Conditions

Min Typ Max Unit

R

-

10

-

Bit

DNL

INL

I_FS

-

Differential non linearity

Integral non linearity

Full Scale current ⁽¹⁾

Current Mismatch

-0.05

-0.45

0.28

-

0.05 LSB

0.45 LSB

2.8 mA

-

2

3

%

V

Output voltage compliance

range

-

0

-

VR_{EXT_DAC}Voltage Reference

-

10

-

1.19

-

V

R_{EXT_DAC}

Icc_static

REXT DAC Range

100 kΩ

mA

Static current consumption

(Iout = 0 mA; pin 1)

2.5

-

1. See relationship between IDAC and R_{EXT_DAC}in the Circuit Description section (Dual Output Current DAC)

16/67

Doc ID 018355 Rev 5

STW82100B

Electrical characteristics

Table 8.

Symbol

Integer-N synthesizer electrical characteristics

Parameter Conditions

Min

Typ

Max

Unit

VCO dividers

Prescaler 16/17

256

361

-

65551

77836

-

N

VCO Divider Ratio (N)

Prescaler 19/20

Reference clock and phase frequency detector

F_ref

-

Reference input frequency

Reference input sensitivity

Reference Divider Ratio

PFD input frequency

-

10

0.35

2

19.2

200

1.5

MHz

1

-

Vpeak

R

1023

16

F_PFD

-

MHz

Hz

F_LO

/

F_LO

/

Prescaler 16/17

Prescaler 19/20

-

65551

256

F_STEP

Frequency step ⁽¹⁾

F_LO

/

F_LO

/

Hz

77836

361

Charge pump

I_CP

ICP sink/source ⁽²⁾

3bit programmable

-

0.4

-

5

mA

V

V_OCP

-

Output voltage compliance range

Spurious⁽³⁾

-

V_dd-0.3

-

-70

dBc

VCOs

Higher frequency range

-

100

85

-

MHz/V

Intermediate frequency

range

K_VCOA

VCOA sensitivity

VCOB sensitivity

Lower frequency range

Higher frequency range

-

70

75

-

MHz/V

Intermediate frequency

range

K_VCOB

-

65

-

MHz/V

Lower frequency range

-

55

-

125

95

MHz/V

° C

CALTYPE [0]

-

VCOA Maximum Temperature

variation for continuous lock ⁽⁴⁾

ΔT_LKA

ΔT_LKB

-

CALTYPE [1]

-

° C

CALTYPE [0]

-

° C

VCOB Maximum Temperature

variation for continuous lock ⁽⁴⁾

CALTYPE [1]

-

125

-

° C

VCO A Pushing

-

8

14

MHz/V

V

VCO B Pushing

-

V_CTRL

-

VCO control voltage

LO Harmonic Spurious

0.4

-

V_dd-0.3

-20

dBc

VCO and VCO buffer current

consumption

I_VCO

Amplitude [11] (pin 4)

(pin 3)

-

35

20

-

mA

IDIV

DIVIDER by 2 consumption

2

Doc ID 018355 Rev 5

17/67

Electrical characteristics

STW82100B

Table 8.

Symbol

Integer-N synthesizer electrical characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Unit

2 x LO output buffer (test purpose only)

F_OUT

P_OUT

RL

Frequency range

Output level

-

3.3

-

4.74

GHz

-

0

-

dBm

dB

Return Loss

Matched to 50ohm

(pin 15, 16, 17)

15

26

I_2LOBUF

Current Consumption

mA

LO output buffer

F_OUT

P_OUT

RL

Frequency range

-

1.65

-

2.37

GHz

dBm

dB

Output level

-

3

-

Return Loss

Matched to 50ohm

(pin 15, 16, 17)

14

26

I_LOBUF

Current Consumption

mA

External VCO (LO) buffer

f_INVCO

P_IN

Frequency range

Input level

-

1.65

-

2.37

-

GHz

dBm

0

External VCO Buffer

(pin 4)

I_EXTBUF

Current Consumption

-

25

-

mA

PLL miscellaneous

Input Buffer, Prescaler,

Digital Dividers, misc.

(pin 24)

I_PLL

PLL Current Consumption

-

8

-

mA

Prescaler input buffer Current

Consumption

I_PRE

I_CP

(pin 12)

-

3

4

-

mA

CPSEL=[111], REXT_CP

= 4.7 kΩ (pin 21)

Charge Pump Current Consumption

Lock up time⁽⁵⁾

25 kHz PLL bandwidth;

within 1ppm of frequency

error

t_LOCK

-

150

-

µs

1. The frequency step is related to the PFD input frequency as follows: F_STEP=F_PFD/2)

2. See relationship between ICP and R_{EXT_CP}in the Circuit Description section (Charge Pump)

3. The level of spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop BW.

4. When setting a specified output frequency, the VCO calibration procedure must be run first in order to select the best

subrange for the VCO covering the desired frequency. Once programmed at the initial temperature T₀inside the operating

temperature range (-40 ^oC to +85 ^oC), the synthesizer is able to maintain the lock status if the temperature drift (in either

direction) is within the limit specified by ΔT_LKAor ΔT_LKB, provided that the final temperature T₁is still inside the nominal

range.

5. Frequency jump form 1950 to 1800 MHz; it includes the time required by the VCO calibration procedure (7 x F_PFDcycles

=17.5 µs with F_PFD=400 kHz))

18/67

Doc ID 018355 Rev 5

STW82100B

Table 9.

Electrical characteristics

(1)

Phase noise performance

Parameters

Conditions

Min.

Typ.

Max.

Unit

In band phase noise floor, closed loop⁽²⁾

Normalized In Band Phase Noise

Floor (LO)

I

_CP=4 mA, PLL BW = 50 kHz

-

-230

-

dBc/Hz

(including reference clock

contribution)

In Band Phase Noise Floor (LO)

-230+20log(N)+10log(F_PFD) dBc/Hz

PLL integrated phase noise

Integrated Phase Noise

(single sided)

-

-45

-

dBc

F_LO=2.200 GHz, F_STEP=200 kHz,

I_CP=3 mA, PLL BW = 25 kHz

0.48

° rms

100 Hz to 40 MHz

LOA (1650 MHz to 1950 MHz) – open loop

Phase Noise @ 1 kHz

-

-69

-95

-

dBc/Hz

Phase Noise @ 10 kHz

Phase Noise @ 100 kHz

Phase Noise @ 1 MHz

Phase Noise @ 10 MHz

Phase Noise Floor @ 40 MHz

-118

-139

-152

-154

LOB (2050 MHz to 2370 MHz) – open loop

Phase Noise @ 1 kHz

-

-62

-88

-

dBc/Hz

Phase Noise @ 10 kHz

Phase Noise @ 100 kHz

Phase Noise @ 1 MHz

Phase Noise @ 10 MHz

Phase Noise Floor @ 40 MHz

-112

-134

-150

-153

1. Phase Noise SSB. VCO amplitude set to maximum value [11]. All the closed-loop performances are specified using a

Reference Clock signal at 76.8 MHz with phase noise of -144 dBc/Hz @1 kHz offset, -157 dBc/Hz @10 kHz offset and

-168 dBc/Hz of noise floor.

2. Normalized PN = Measured LO PN – 20log(N) – 10log(F_PFD) where N is the VCO divider ratio (N=B*P+A) and F_PFDis the

comparison frequency at the PFD input

Doc ID 018355 Rev 5

19/67

Typical performance characteristics

STW82100B

7

Typical performance characteristics

Note:

Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, F = 150 MHz,

IF

T = +25 °C, RF power = 0 dBm, unless otherwise specified.

A

Figure 3.

Conversion gain against RF frequency

RF frequency (MHz)

Figure 4.

Noise figure against RF frequency

RF frequency (MHz)

20/67

Doc ID 018355 Rev 5

STW82100B

Figure 5.

Typical performance characteristics

IIP3 against RF frequency

RF frequency (MHz)

Figure 6.

2RF-2LO response against RF frequency

RF frequency (MHz)

Doc ID 018355 Rev 5

21/67

Typical performance characteristics

Figure 7. LOA (VCOA div. by 2) closed-loop phase noise at 1.8 GHz (F

STW82100B

=

STEP

200 kHz, I = 2 mA)

CP

Figure 8.

LOB (VCOB div. by 2) closed-loop phase noise at 2.2 GHz (F

=

STEP

200 kHz, I = 2 mA)

CP

22/67

Doc ID 018355 Rev 5

STW82100B

General description

8

General description

The STW82100B (see Figure 1: STW82100B block diagram on page 7) consists of a high

linearity passive CMOS mixer with integrated RF balun, an IF amplifier, a 10-bit current

steering DAC with dual output, and an integrated integer-N synthesizer.

The synthesizer embeds 2 internal low-noise VCOs with buffer blocks, a divider by 2, a low

noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable

reference divider, two programmable counters and a dual-modulus prescaler. The A-counter

(5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler

P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P+A.

The device is controlled through a digital interface (I2C bus interface or SPI digital interface).

All internal devices operate with a power supply of 3.3 V except for the IF Amplifier output

stage and the mixer driver stage operating at 5 V power supply in order to maximize the

linearity performance. If the application requires a reduced linearity and noise figure

performance the device is programmed in a low-current mode by using the minimum LO

amplitude and the minimum biasing current in the IF amplifier. In low-current mode

operation the device can use only the 3.3 V power supply thus dissipating less power.

8.1

Circuit description

8.1.1

Reference input stage

The reference input stage is shown in Figure 9. The resistor network feeds a DC bias at the

F

input while the inverter used as the frequency reference buffer is AC coupled.

ref

Figure 9.

Reference frequency input buffer

VDD

F_ref

Inverter

Buffer

Power Down

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23/67

General description

STW82100B

8.1.2

Reference divider

The 10-bit programmable reference counter allows the input reference frequency to be

divided to produce the input clock to the PFD. The division ratio is programmed through the

digital interface.

8.1.3

Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it

down to a manageable frequency for the CMOS A and B counters. The modulus (P) is

programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which

division ratio depends on the state of the modulus input.

8.1.4

A and B counters

The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17

or 19/20) prescaler make it possible to generate output frequencies which are spaced only

by the reference frequency divided by the reference division ratio. Thus, the division ratio

and the VCO output frequency are given by the following formulae:

N = B × P + A

(B × P + A) × F_ref

F_VCO= -----------------------------------------------

R

where:

F

: VCO output frequency.

VCO

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface).

B: division ratio of the main counter.

A: division ratio of the swallow counter.

F : input reference frequency.

ref

R: division ratio of the reference counter.

N: division ratio of the PLL

The following points should be noted:

●

For the VCO divider to work correctly, B must be higher than A.

A can take any value from 0 to 31.

Two PLL division ratio (N) ranges are possible, depending on the value of P:

–

256 to 65551 (when P=16)

361 to 77836 (when P=19).

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Doc ID 018355 Rev 5

STW82100B

General description

Figure 10. VCO divider diagram

VCOBUF-

VCOBUF+

Prescaler

16/17 or 19/20

To PFD

modulus

12-bit

B counter

5-bit

A counter

8.1.5

Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output

proportional to the phase error. The PFD includes a delay gate that controls the width of the

anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer

function.

Figure 11 is a simplified schematic of the PFD.

Figure 11. PFD diagram

VDD

D

Q

Up

F

ref_DIV

R

Delay

R

F

VCO_div

Q

VDD

D

Down

ABL

Doc ID 018355 Rev 5

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General description

STW82100B

8.1.6

Lock detect

This signal indicates that the difference between rising edges of both UP and DOWN PFD

signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is

high when the PLL is locked. The Lock Detector consumes current only during PLL

transients.

8.1.7

Mute until lock

This (software controlled) function shuts down the following elements until the PLL achieves

the lock status:

●

RF output stage

LO output buffer

mixer

IF amplifier circuitry

Under this setting there is no signal at the IF output stage or the LO output during a

frequency jump.

8.1.8

Charge pump

This block drives two matched current sources, Iup and Idown, which are controlled

respectively by the UP and DOWN PFD outputs. The nominal value of the output current is

controlled by an external resistor (to be connected to the REXT input pin) and the selection

of one of 8 possible values by a 3-bit word.

The minimum value of the output current is: IMIN = 2*VBG/REXT_CP (VBG~1.17 V)

Table 10. Current values for CPSEL[2:0] selection

CPSEL2

CPSEL1

CPSEL0

Current

Value for REXT=4.7 kΩ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I_MIN

0.5 mA

1.00 mA

1.50 mA

2.00 mA

2.50 mA

3.00 mA

3.50 mA

4.00 mA

2*I_MIN

3*I_MIN

4*I_MIN

5*I_MIN

6*I_MIN

7*I_MIN

8*I_MIN

Note:

The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are

forced to VDD/2.

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Doc ID 018355 Rev 5

STW82100B

General description

Figure 12. Loop filter connection

VDD

VCTRL

C3

R3

Buffer

Charge

pump

ICP

R1

C1

C2

Buffer

Cal bit

8.1.9

Voltage controlled oscillators

VCO selection

Within the STW82100B two low-noise VCOs are integrated to cover a wide band from

1650 MHz to 1950 MHz, and from 2050 MHz to 2370 MHz after the division by 2:

●

VCO A frequency range is 3300 MHz to 3900 MHz

VCO B frequency range is 4100 MHz to 4740 MHz

●

VCO frequency calibration

Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting

capacitors to the resonator. These frequency ranges are intended to cover the wide band of

operation and compensate for process variations on the VCO center frequency.

An automatic range selection is performed when the bit SERCAL rises from ‘0’ to ‘1’ . The

charge pump is inhibited and the pins ICP and VCTRL are set at a fixed calibration voltage

(VCAL). The frequency ranges are then tested to select the nearest one to the desired

output frequency (F_OUT= N*F_ref/R) with VCAL input voltage applied. After this selection, the

charge pump is once again enabled and the PLL performs a fine adjustment around VCAL

on the loop filter voltage to lock F_OUT, thus enabling a fast settling time.

Two calibration algorithms are selectable by setting the CALTYPE bit.

Setting the CALTYPE to ’1’ guarantees the PLL lock versus temperature variations. Once

programmed at the initial temperature, T , within the operating temperature range (-40 °C to

0

+85 °C), the synthesizer is able to maintain the lock status if the temperature drift (in either

direction) is within the limit specified by ΔT , and provided that the final temperature, T , is

LK

1

still inside the nominal range.

Setting the CALTYPE bit to ‘0’ fixes VCAL to the mid point of the charge pump output

(VDD/2). Optimum PLL phase noise performance versus temperature variations with a

reduced ΔT is guaranteed in this case. The ΔT parameter, specific to each VCO and

LK

calibration type, in the STW82100B is specified in Table 8: Integer-N synthesizer electrical

characteristics.

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General description

STW82100B

Figure 13. VCO typical sub-band characteristics

00000

00001

01111

11111

Calibrator lock

range

3.50

0.00

0.50

2.50

3.00

1.00

1.50

VCTRL (V)

2.00

The SERCAL bit should be set to ’1’ at each division ratio change. The calibration takes

approximately 7 periods of the Comparison Frequency and the SERCAL bit is automatically

reset to ’0’ at the end of each calibration.

The maximum allowed F

to perform the calibration process is 1 MHz. If a higher F

is

PFD

used the following procedure should be adopted:

1. Calibrate the VCO at the desired frequency with an F

lower than 1 MHz

PFD

2. Set the A, B and R dividers ratio for the desired F

PFD

For calibration details refer to Section 9.4.1: VCO calibration procedure (I2C interface) or

Section 10.4.1: VCO calibration procedure (SPI interface).

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STW82100B

General description

VCO calibration auto-restart feature

The VCO Calibration Auto-Restart feature, once activated, allows the calibration procedure

to be restarted when the Lock Detector reports that the PLL has moved to an unlock

condition (trigger on ‘1’ to ‘0’ transition of Lock Detector signal).

This situation could happen if the device experiences a significant temperature variation and

the CALTYPE bit is set for optimum PLL phase noise performance (CALTYPE [0]).

By enabling the VCO Calibration Auto-Restart feature (through the AUTO_CAL bit), the

device re-selects the proper VCO frequency sub-range without any external user command.

This feature can be enabled only when the F

is lower than 1 MHz.

PFD

VCO voltage amplitude control

The voltage swing of the VCOs can be adjusted over 4 levels by means of two dedicated

programming bits (PLL_A1 and PLL_A0). This setting trades current consumption with

phase noise performances of the VCO. Higher amplitudes provide best phase noise while

lower ones save power.

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General description

STW82100B

Table 11 and Table 12 give the current consumption and the phase noise at 1 MHz.

Table 11. VCOA performance against amplitude setting (frequency = 3.6 GHz)

Current

PLL_A[1:0]

PN @ 1 MHz

Consumption (mA)

00

01

10

11

23

24

32

35

-127

-128

-131

-132

Table 12. VCOB performance against amplitude setting (frequency = 4.3 GHz)

Current

PLL_A[1:0]

PN @ 1 MHz

Consumption (mA)

00

01

10

11

16

18

27

30

-124

-126

-128

-129

8.1.10

8.1.11

Output stage

The differential output signal of the synthesizer after the Divider by 2 is available on

pins 16 and 17.

The output stage is selected by programming the PD[4:0] bits.

The output stage is an open-collector structure which is able to meet different requirements

over the desired output frequency range by proper connections on the PCB. See Figure 27:

Diversity mode operation with same LO frequencies.

External VCO buffer

Although the STW82100B includes two wideband and low-noise VCOs, external VCO use

capability is also provided.

The external VCO buffer can be used to manage a signal coming from an external VCO in

order to build a local oscillator signal by using the STW82100B internal synthesizer as a

PLL. This is only possible when External VCO standard mode or External VCO diversity

master mode operation are selected. See Figure 29: External VCO standard mode

operation and Figure 30: External VCO diversity mode operation with same LO.

If the STW82100B is operated in Diversity slave mode, the external VCO buffer manage the

signal coming from the synthesizer output stage of another STW82100B device See

Figure 27: Diversity mode operation with same LO frequencies and Figure 30: External

VCO diversity mode operation with same LO.

The selection of the external VCO buffer is done by setting the PD[4:0] bits.

The external VCO signal can range from 1650 MHz to 2370 MHz and its minimum power

level must be -10 dBm.

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STW82100B

General description

8.1.12

Mixer and IF amplifier

LO mixer driver

The LO signal is fed through a driver in order to achieve the high power level needed to drive

the passive mixer for maximum performance of linearity and NF.

The LO Mixer Driver is coupled to the mixer with an integrated LO balun. The LO signal level

is adjusted by means of an Automatic Level Control loop (ALC) controlled by the bits

LO_A[1:0].

In low current mode the configuration LO_A[1:0]=’00’ (minimum LO amplitude) should be

selected and the power supply on pin 40 can be set to 3.3 V.

The LO balun resonating frequency can be adjusted by means of the bits CAP[2:0] in order

to match the selected LO frequency.

Table 13. Suggested CAP[2:0] values for LO Frequency range mixer

CAP[2:0]

LO frequency range

000

001

010

011

100

101

110

111

2225MHz ÷ 2370MHz

2100MHz ÷ 2225MHz

2000MHz ÷ 2100MHz

1900MHz ÷ 2000MHz

1825MHz ÷ 1900MHz

1750MHz ÷ 1825MHz

1700MHz ÷ 1750MHz

1650MHz ÷ 1700MHz

Mixer

A doubly balanced CMOS passive mixer is internally driven by the high level LO signal in

order to achieve high linearity and low noise performance.

The RF integrated balun permits the removal of external components and it is internally

matched to 50 ohms.

The gate bias of the CMOS devices in the mixer is programmable with 4 bits (MIX[3:0]) to

optimize the input matching and the gain of the signal chain.

Higher values of gate bias (higher decimal values of MIX[3:0]) are suggested to maximize

linearity and lower values to maximize the performance of Gain and NF.

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General description

STW82100B

IF amplifier

The integrated IF stage permits a 200-ohm load to be driven (typically a SAW filter) ensuring

high linearity.

It is an open collector stage (pin 31, 32) and should be biased to 5 V with choke inductors.

The typical output impedance is 200 ohms. The linearity performances are controlled by the

bits IFAMP[1:0]. In low current mode the configuration IFAMP[1:0]=’00’ (minimum linearity)

should be selected and the open collector stage can be biased to 3.3 V with choke

inductors.

Table 14. Linearity performance against IFAMP[1:0] configuration (typical

condition)

IFAMP[1:0]

Linearity performance

00

01

10

11

19.5 dB

21.5 dB

23.5dB

25.5dB

8.1.13

Dual output current DAC

The STW82100B embeds a 10-bit Dual Output steering current DAC especially suited to

drive an external PIN diode attenuator. This provides power level calibration capability at the

RF input for the TX observation path applications.

The current sourced by the DAC is related to the R

resistor according to the

EXT_DAC

following formulae (where VR

is approximately 1.19 V):

EXT_DAC

3 × VR_{EXT_DAC}

1

2

1

64

-- ---------------------------------------- ------

IDAC_LSB

=

×

LSB DAC current

R_{EXT_DAC}

3 × VR_{EXT_DAC}

-- ---------------------------------------- ------------

1

2

1023

64

IDAC_FS

=

×

Full scale current

R_{EXT_DAC}

With a 10 kΩ R

the FS current is approximately 2.8 mA.

EXT_DAC

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Doc ID 018355 Rev 5

STW82100B

I2C bus interface

2

9

I C bus interface

2

The I C bus interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 0 V.

Data transmission from a microprocessor to the STW82100B takes place through the 2

2

wires (SDA and SCL) I C-bus interface. The STW82100B is always a slave device.

2

The I C-bus protocol defines any device that sends data on to the bus as a transmitter and

any device that reads the data as receiver. The device that controls the data transfer is

known as the master and the others as slaves. The master always initiates the transfer and

provides the serial clock for synchronization.

2

The STW82100B I C bus supports Fast Mode operation (clock frequency up to 1 MHz).

9.1

I²C general features

9.1.1

Data validity

Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while

the clock is HIGH identify START or STOP conditions.

Figure 14. Data validity waveform

SDA

SCL

Change

data allowed

Data line stable

data valid

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I2C bus interface

STW82100B

9.1.2

START and STOP conditions

Figure 15. START and STOP condition waveform

SCL

SDA

START

STOP

START condition

A START condition is identified by a HIGH to LOW transition of the data bus SDA while the

clock signal SCL is stable in the HIGH state. A Start condition must precede any command

for data transfer.

STOP condition

A STOP condition is identified by a transition of the data bus SDA from LOW to HIGH while

the clock signal SCL is stable in the HIGH state.. A STOP condition terminates

communications between the STW82100B and the Bus Master.

9.1.3

Byte format and acknowledge

Every byte (8 bits long) transferred on the SDA line must contain bits. Each byte must be

followed by an acknowledge bit. The MSB is transferred first.

An acknowledge bit indicates a successful data transfer. The transmitter, either master or

slave, releases the SDA bus after sending 8 bits of data. During the 9th clock pulse the

receiver pulls the SDA low to acknowledge the receipt of 8 bits of data.

Figure 16. Byte format and acknowledge waveform

SCL

2

7

1

3

8

9

SDA

MSB

Acknowledgement

from receiver

START

STOP

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STW82100B

I2C bus interface

9.1.4

Device addressing

To start the communication between the Master and the STW82100B, the master must

initiate with a START condition. Following this, the master sends onto the SDA line 8 bits

(MSB first) corresponding to the device select address and read or write mode.

2

The first 7 MSBs are the device address identifier, corresponding to the I C-Bus definition.

For the STW82100B the address is set as ’1101A A A ’, 3-bits programmable. The 8th bit

2

1 0

(LSB) is the read or write operation bit (the RW bit is set to 1 in read mode and to 0 in write

mode).

After a START condition the STW82100B identifies the device address on the bus and, if

matched, it acknowledge the identification on SDA bus during the 9th clock pulse.

9.1.5

9.1.6

9.1.7

Single-byte write mode

Following a START condition the master sends a device select code with the RW bit set to 0.

The STW82100B gives an acknowledge and waits for the internal sub-address (1 byte). This

byte provides access to any of the internal registers.

After reception of the internal byte sub-address the STW82100B again responds with an

acknowledge. A single-byte write to sub-address 0x00 would affect DATA_OUT[47:40], a

single-byte write with sub-address 0x04 would affect DATA_OUT[15:8] and so on.

sub-address

S

1101A₂A₁A₀

0

ack

DATA IN

ack

P

byte

Multi-byte write mode

The multi-byte write mode can start from any internal address. The master sends the data

bytes and each one is acknowledged. The master terminates the transfer by generating a

STOP condition.

The sub-address determines the starting byte. For example, a multi-byte write with sub-

address 0x01 and 4 DATA_IN bytes affects 4 bytes starting at address 0x01 (registers at

addresses 0x01, 0x02, 0x03 and 0x04 are modified).

sub-address

byte

DATA

IN

S

1101A₂A₁A₀0 ack

ack

DATA IN

ack

..

ack

P

Current byte address read

In the current byte address read mode, following a START condition, the master sends the

device address with the RW bit set to 1 (No sub-address is needed as there is only 1 byte

read register). The STW82100B acknowledges this and outputs the data byte. The master

does not acknowledge the received byte, but terminates the transfer with a STOP condition.

S

1101A₂A₁A₀

1

ack

DATA OUT

No ack

P

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I2C bus interface

STW82100B

9.2

I²C timing specifications

9.2.1

Data and clock timing specification

2

Figure 17. I C data and clock waveforms

SDA

SCL

t_cwl

t_cs

t_ch

t_cwh

2

Table 15. I C data and clock timing parameters

Symbol

T_cs

Parameter

Data to clock set up time

Min

2

Unit

T_ch

Data to clock hold time

Clock pulse width high

Clock pulse width low

2

ns

T_cwh

T_cwl

10

5.5

2

9.2.2

I C START and STOP timing specification

2

Figure 18. I C START and STOP timing waveforms

SDA

SCL

t_stop

t_start

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Doc ID 018355 Rev 5

STW82100B

I2C bus interface

2

Table 16. I C START and STOP timing parameters

Symbol

start

Parameter

Clock to data start time

Data to clock down stop time

Min

Unit

T

2

ns

stop

2

9.2.3

I C acknowledge timing specification

2

Figure 19. I C acknowledge timing waveforms

SDA

SCL

8

9

t_d1

t_d2

2

Table 17. I C acknowledge timing parameters

Symbol

Parameter

Ack begin delay

Ack end delay

Max

Unit

T_d1

T_d2

2

ns

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I2C bus interface

STW82100B

9.3

I²C registers

STW82100B has 9 write-only registers and 1 read-only register.

2

9.3.1

I C register summary

The following table gives a short description of the write-only registers list.

2

Table 18. I C register list

Offset

0x00

Register name

Description

Functional mode register

Page

FUNCTIONAL_MODE

B_COUNTER

on page 39

on page 40

on page 41

on page 42

on page 43

on page 44

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

B counter register

A_COUNTER

A counter register

REF_DIVIDER

Reference clock divider ratio register

PLL control register

CONTROL

MUTE_&_CALIBRATION

DAC_CONTROL

Mute and calibration control register

DAC control register

MIXER_CONTROL

IFAMP_LO_CONTROL

READ_ONLY_REGISTER

Mixer control register

IF amplifier LO control register

Device ID and calibration status register

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STW82100B

I2C bus interface

2

9.3.2

I C register definitions

FUNCTIONAL_MODE

Functional mode register

7

ALC_PD

W

6

PKD_EN

W

5

4

3

PD[4:0]

W

2

1

0

B11

W

Address:

Type:

0x00

W

Reset:

0x00

[7] ALC_PD: for test purpose only must be set to ’0’. (ALC ON)

[6] PKD_EN: for test purpose only must be set to ’0’. (Peak detector output on pin 36 OFF)

[5:1] PD[4:0]: bits used to select different functional modes for the STW82100B according to

the following table

00000: (0 decimal) Power down mode

00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON)

00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON)

00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON;

internal synthesizer OFF)

00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output

buffer ON)

00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output

buffer ON)

00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO

input buffer ON)

00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO

input buffer and LO output buffer ON)

[0] B11: B counter value (bits B[10:0] in the B_COUNTER and A_COUNTER registers)

B_COUNTER

B counter register

7

6

5

4

3

2

1

0

B[10:3]

W

Address:

Type:

0x01

W

Reset:

0x00

Description:

Most significant bits of the B counter value

[7:0] B[10:3]: B counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[2:0] in the

A_COUNTER register)

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I2C bus interface

STW82100B

A_COUNTER

A counter register

7

6

5

4

3

2

A[4:0]

W

1

0

B[2:0]

W

Address:

Type:

0x02

W

Reset:

0x00

Description:

Least significant bits of the B-counter value. A-counter value.

[7:5] B[2:0]: B Counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[10:3] in

the B_COUNTER register).

[4:0] A[4:0]: A counter value

REF_DIVIDER

Reference clock divider ratio register

7

6

5

4

3

2

1

0

R[9:2]

W

Address:

Type:

0x03

W

Reset:

0x00

Description:

Most significant bits of the reference clock divider ratio value.

[7:0] R[9:2]: Reference clock divider ratio (bits R[1:0] in the CONTROL register)

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STW82100B

I2C bus interface

CONTROL

PLL control register

7

6

5

4

3

2

CPSEL[2:0]

W

1

0

PSC_SEL

W

[R1:0]

PLL_A[1:0]

W

Address:

Type:

0x04

W

Reset:

0x00

Description:

Least significant bits of the reference clock divider ratio value and PLL control bits.

[7:6] R[1:0]: Reference clock divider ratio (bits R[9:2] in the REF_DIVIDER register)

[5:4] PLL_A[1:0]: VCO amplitude

[3:1] CPSEL[2:0]: Charge Pump output current

[0] PSC_SEL: Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19)

The LO output frequency is programmed by setting the proper value for A, B and R

according to the following formula:

F_ref

---------

F_LO= D_R⋅ (B ⋅ P + A) ⋅

R

where D_Requals 0.5 (VCOs output frequency divided by 2)

and P is the selected Prescaler Modulus

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I2C bus interface

STW82100B

MUTE_&_CALIBRATION

Mute and calibration control register

7

6

5

4

3

2

1

0

W

Address:

Type:

0x05

W

Reset:

0x00

Description:

For test purposes only

[7] CALTYPE: Calibration algorithm selection

0: standard calibration to optimize the phase noise versus temperature

1: enhanced calibration to maximize the Δ_TLKrange

[6] SERCAL:

1: starts the VCO auto-calibration (automatically reset to ’0’ at the end of calibration)

[5] SELEXTCAL: test purpose only; must be set to ‘0’

[4] MUTE_EN:

0: mute function disabled

1: mute function enabled

[3] MUTE_TYPE: must be set to '1' while the mute function is enabled (mute the IF output

on Unlock state)

[2] MUTE_LOOUT_EN:

To be set to ’1’ to mute the LO output buffer

[1] MUTE_MIX_EN:

To be set to ’1’ mute the Mixer circuitry

[0] MUTE_IFAMP_EN: To be set to '1' to mute the IF amplifier circuitry

DAC_CONTROL

DAC control register

7

6

5

4

3

2

1

0

DAC[9:2]

W

Address:

Type:

0x06

W

Reset:

0x00

Description:

Most significant bits of the DAC control word

[7:0] DAC[9:2]: DAC input word for DAC current control (bits DAC[1:0] in the

MIXER_CONTROL register).

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STW82100B

I2C bus interface

MIXER_CONTROL

Mixer control register

7

6

5

4

3

2

1

0

W

Address:

Type:

0x07

W

Reset:

0x00

Description:

Least significant bits of DAC control word and mixer control bit fields

[7:6] DAC[1:0]: DAC input word for DAC current control (bits DAC[9:2] in the DAC_CONTROL

register)

[5:2] MIX[3:0]: Mixer bias control value

[1] PD_DAC: DAC power down

[0] CAL_AUTOSTART_EN: VCO calibration auto-restart enable (’1’ active), permits to

automatically restart the VCO calibration procedure in case of PLL unlock

IFAMP_ LO_CONTROL

IF amplifier LO control register

7

6

5

4

CAP[2:0]

W

3

2

1

0

LPMUX_EN

W

IFAMP[1:0]

W

LO_A[1:0]

W

Address:

Type:

0x08

W

Reset:

0x00

[7:6] IFAMP[1:0]: power consumption/linearity control

[5:3] CAP[2:0]: Tuning capacitors control

[2:1] LO_A[1:0]: LO amplitude control

[0] LPMUX_EN: for test purpose only (low power mode for MUX). Must be set to ’0’

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I2C bus interface

STW82100B

READ-ONLY REGISTER

Device ID and calibration status register

7

6

5

LOCK_DET

R

4

3

2

INTCAL[4:0]

R

1

0

ID[1:0]

R

Address:

Type:

0x09

R

Reset:

0x00

Description:

This register is automatically addressed in the ‘current byte address read mode’

[7:6] ID[1:0]: device identification ’00’ for STW82100B

[5] LOCK_DET: ’1’ when PLL is locked

[4:0] INTCAL[4:0]: internal value of the VCO calibration control word

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STW82100B

I2C bus interface

9.4

Device calibration through the I²C interface

2

9.4.1

VCO calibration procedure (I C interface)

The calibration of the VCO center frequency is activated by setting the SERCAL bit of the

MUTE & CALIBRATION register to ’1’.

To program the device ensuring a correct VCO calibration, the following procedure is

required before every channel change:

1. Program all the Registers using a multi-byte write sequence with the desired setting:

–

Functional Mode

B and A counters

R counter

VCO amplitude

Charge Pump

Prescaler Modulus

DAC

Mixer and LO Control

all bits of the MUTE & CALIBRATION Register (0x05) set to ’0’.

2. Program the MUTE & CALIBRATION register using a single-byte write sequence (sub-

address 0x05) with the SERCAL bit set to ’1’.

The maximum allowed PFD frequency (F

) to perform the calibration process is 1 MHz. If

PFD

the desired F

is higher than 1 MHz the following steps are needed:

PFD

3. Perform all the step of the above calibration procedure programming the desired VCO

frequency with a proper setting of R, B and A counter so that F

1 MHz.

results lower than

PFD

4. Once calibration is completed, program all the Registers by using a multi-byte write

sequence (Functional Mode, B and A counters, R counter, VCO amplitude, Charge

Pump, Prescaler Modulus, DAC, Mixer and LO Control) with the proper settings for the

desired VCO and PFD frequencies.

2

9.4.2

Power ON sequence (I C interface)

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following

steps must be followed:

1. Power up the device

2. Provide the Reference clock

3. Implement the first programming sequence with a proper delay time between the STOP

condition of the multi-byte write sequence and that of the single-byte write sequence

(see Figure 20). The T

value must respect the following condition:

delay

1

F_ref

---------

T_delay>1023 ×

F

is the reference clock frequency.

ref

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I2C bus interface

STW82100B

2

Figure 20. I C first programming timing

START

STOP

CLK

Tdelay > 1023/F

ref

LSB

MSB

LSB

MSB

DATA

Multi-byte sequence

Single-byte sequence

2

9.4.3

VCO calibration auto-restart procedure (I C interface)

The VCO calibration auto-restart feature is enabled in two steps:

1. Set the desired frequency ensuring VCO calibration procedure as described above

(Section 9.4.1).

2. Program the MIXER_CONTROL register (sub-address 0x07) using a single-byte write

sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping the others

unchanged.

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STW82100B

SPI digital interface

10

SPI digital interface

10.1

SPI general features

The SPI digital interface is selected by hardware connection of the pin 25 (DBUS_SEL) to

3.3 V.

The STW82100B IC is programmed by means of a high-speed serial-to-parallel interface

with write option only. The 3-wires bus can be clocked at a frequency as high as 100 MHz to

allow fast programming of the registers containing the data for RF IC configuration.

The programming of the chip is done through serial words with whole length of 26 bits. The

first 2 MSB represent the address of the registers. The others 24 LSB represent the value of

the registers.

Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal.

On the rising edge of the LOAD signal the outputs of the selected register are sent to the

device.

Figure 21. SPI input and output bit order

Last

bit sent

(LSB) 0

25 (MSB)

23

2

1

24

DATA

A1

LOAD

Address

decoder

LOAD #4

00 (LSB)

Reg. #0

Reg. #1

Reg. #4

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SPI digital interface

STW82100B

Figure 22. SPI data structure

LSB

MSB

Address

Data for register (24 bits)

A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Note: MSB is sent first

Table 19. Address decoder and outputs

Address

Outputs

DATABITS

D23-D0

A1

A0

N^o

Name

ST1

Function

0

1

24

0

1

DAC, Mixer, Tuning capacitors, LO_amplitude

Reference divider, VCO amplitude, VCO Calibration, Charge

Pump current, Prescaler Modulus, Mute functions

ST2

1

0

1

24

2

3

ST3

ST4

Functional modes, VCO dividers

Reserved

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Doc ID 018355 Rev 5

STW82100B

SPI digital interface

10.2

SPI timing specification

10.2.1

Data, clock and load timing

Figure 23. SPI timing waveforms

t

setup

hold

MSB

MSB - 1

LSB

DATA

CLOCK

t

clk_loadr

t

clk

LOAD

t

clk_loadf

load

Table 20. SPI timing parameters

Parameter Description

t_setup

Min.

Typ.

Max.

Unit

DATA to CLOCK setup time

DATA to clock hold time

CLOCK cycle period

1

-

ns

t_hold

0.5

10

3

t_clk

t_load

LOAD pulse width

t_{clk_loadr}

t_{clk_loadf}

CLOCK to LOAD rising edge

CLOCK to LOAD falling edge

0.6

2.5

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SPI digital interface

STW82100B

10.3

SPI registers

10.3.1

SPI register summary

Table 21. SPI register list

Offset Register name

0x00

Description

Page

ST1

ST2

ST3

SPI register 1

SPI register 2

SPI register 3

on page 50

on page 51

on page 52

0x01

0x10

10.3.2

ST1

SPI register definitions

SPI register 1

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

W

Address:

Type:

0x00

W

Reset:

0x00

[23:14] DAC[9:0]: DAC input word

[13:10] MIX[3:0]: Mixer bias control

[9] PWD_DAC: DAC power down

[8] CAL_AUTOSTART_EN: VCO calibration auto-restart enable

[7:6] IF[1:0]: Power consumption/linearity control

[5:3] CAP[2:0]: Tuning capacitors control

[2:1] LO_A[1:0]: LO amplitude control

[0] LPMUX_EN: For test purpose only. Must be set to ‘0’

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Doc ID 018355 Rev 5

STW82100B

SPI digital interface

ST2

SPI register 2

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

W

Address:

Type:

0x01

W

Reset:

0x00

[23:14] R[9:0]: Reference clock divider ratio

[13:12] PLL_A[1:0]: VCO amplitude control

[11:9] CPSEL[2:0]: Charge pump output current control

[8] PSC_SEL: Prescaler modulus select (‘0’ for P=16, ‘1’ for P=19)

[7] CAL_TYPE: Calibration algorithm selection

0: standard calibration to optimize the phase noise versus temperature

1: enhanced calibration to maximize the ΔTLK range

[6] SERCAL:

at ‘1’ starts the VCO auto-calibration (automatically reset to ‘0’ at the end of calibration)

[5] SELEXTCAL: test purpose only. Must be set to ‘0’

[4] MUTE_EN:

0: mute function disabled

1: mute function enabled

[3] MUTE_TYPE: must be set to '1' while the mute function is enabled (mute the IF output

on Unlock state)

[2] MUTE_LOOUT_EN:

To be set to ’1’ to mute the LO output buffer

[1] MUTE_MIX_EN:

To be set to ’1’ to mute the Mixer circuitry

[0] MUTE_IFAMP_EN:

To be set to ’1’ to mute the IF amplifier circuitry

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SPI digital interface

STW82100B

ST3

SPI register 3

23

22

W

21

20

19

W

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

W

Address:

Type:

0x10

W

Reset:

0x00

[23] ALC_PD: Test purpose only; must be set to ‘0’ (ALC ON)

[22] PKD_EN: for test purpose only; must be set to ‘0’

[21:17] PD[4:0]:

00000: (0 decimal) Power down mode

00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON)

00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON)

00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON;

internal synthesizer OFF)

00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output

buffer ON)

00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output

buffer ON)

00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO

input buffer ON)

00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO

input buffer and LO output buffer ON)

[16:5] B[11:0]: B counter bits

[4:0] A[4:0]: A Counter Bits

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Doc ID 018355 Rev 5

STW82100B

SPI digital interface

10.4

Device calibration through the SPI interface

10.4.1

VCO calibration procedure (SPI interface)

The calibration of the VCO center frequency is activated by setting to ’1’ the SERCAL bit

(ST2 Register bit [6]).

In order to program properly the device while ensuring the VCO calibration, the following

procedure is required before every channel change:

1. Program the ST1 Register with the desired setting (DAC, Mixer, LO Control)

2. Program the ST3 Register with the desired setting (Functional mode, B and A counters)

3. Program the ST2 Register with the desired setting (R counter, VCO amplitude, Charge

Pump, Prescaler Modulus) and SERCAL bit set to ’1’

The maximum allowed PFD frequency (F

) to perform the calibration process is 1 MHz; if

PFD

the desired F

is higher than 1 MHz the following steps are needed:

PFD

4. Perform all the steps of the above calibration procedure programming the desired VCO

frequency with a proper setting of R, B and A counter so that F

MHz.

results lower than 1

PFD

5. Once calibration is completed program the device with the proper setting for the desired

VCO and PFD frequencies according to the following steps:

a) Program the ST3 Register with the desired setting (Functional mode, B and A

counters)

b) Program the ST2 Register with the desired setting (R counter, VCO amplitude,

Charge Pump, Prescaler Modulus) with the SERCAL bit set to ’0’.

10.4.2

Power ON sequence (SPI interface)

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following

steps must be followed:

1. Power up the device

2. Provide the reference clock

3. Implement the first programming sequence with a proper delay time between the ST3

and ST2 load rising edges (see Figure 24). The T

value must respect the following

delay

condition:

1

F_ref

---------

T_delay>1023 ×

F

is the reference clock frequency.

ref

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SPI digital interface

STW82100B

Figure 24. SPI first programming timing

ST2

ST3

LSB-1

MSB

MSB-1

LSB

LSB-1

DATA

MSB

MSB-1

LSB

T

> 1023/F

delay

ref

LOAD

10.4.3

VCO calibration auto-restart procedure (SPI interface)

The VCO calibration auto-restart feature is enabled in two steps:

1. Set the desired frequency ensuring VCO calibration as described in Section 10.4.1.

2. Program the ST1 register with the CAL_AUTOSTART_EN bit set to '1' while keeping

unchanged the others.

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STW82100B

Application information

11

Application information

11.1

Application circuit

Figure 25. Typical STW82100B application circuit

3.3V_LN4

C1

C2 C3

RF_IN

C19

5V_1

C1

C2 C3

C1

C2 C3

3.3V_LN1

C1

C2 C3

3.3V_LN3

40

38

42

44 43

39

36

35

34

41

37

C1

C2 C3

1

2

VDD_DAC

REXT_DAC

VDD_DIV

VDD_IFAMP

33

U3

IF_out

3.3V_LN1

5V_2

C15 C16 C17

1

2

3

6

L3

L4

32

31

30

IF_OUTP

IF_OUTN

C18

NC

5

4

C1

C2 C3

3

4

VDD_VCO

NC

C4

C14

C13

C12

NC

6

LOAD

5

EXTVCO_INN

EXTVCO_INP

EXT_PD

ADD2

LOAD

29

28

4

5

2

R1

C5

R10

R9

SLC/CLK

U1

1

3

X1

SLC/CLK

X3

6

VFQFPN-44

SDA/DATA

7

SDA/DATA 27

VDD_DIG 26

External VCO

X4

X2

R8

3.3V_LN2

8

3.3V_LN2

SPI

I2C

3.3V_LN1

C1

C2 C3

DBUS_SEL

25

9

ADD1

3.3V_LN2

_{VDD_PLL}24

REF_CLK 23

ADD0

10

11

REF_CLK

C11

C1 C2 C3

VDD_IO

R7

12

22

13

20

14 15

16 17 18 19

3.3V_LN1

21

LOCK_DET

3.3V_LN1

R6

C1

C2 C3

3.3V_LN1

C2 C3

C1

C2 C3

R2

L1

R3

L2

C1

R4

C9

C1 C2

C3

C10

C8

R5

C6

C7

3

2

1

4

5

6

NC

U2

X5

X7

X6

X8

LO_Output

Doc ID 018355 Rev 5

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Application information

STW82100B

Table 22. Application circuit component values

Designation

C1, C15

Quantity

Description

Supplier

2

1

2

3

1

3

1

4

3

1

2

1

0

1

2

4.7 µF capacitors COG (0402)

1 nF capacitors COG (0402)

10 pF capacitor COG (0402)

3.6 pF capacitors COG (0402)

6.8 pF capacitors COG (0402)

270 pF capacitor COG (0402)

2.7 nF capacitor COG (0402)

68 pF capacitor COG (0402)

15 pF capacitors COG (0402)

100 nF capacitor COG (0402)

100 pF capacitor COG (0402)

180 pF capacitor COG (0402)

100 Ohm resistors (0402)

51 Ohm resistors (0402)

2.2 kohm resistor (0402)

8.2 kohm resistor (0402)

4.7 kohm resistor (0402)

Balun JTI - 2450BL15B100

Balun JTI - 1600BL15B100

Balun ADT4-5WT

C2, C11

C3

C4,C5

C6, C7, C19

C8

Murata Manufacturing Co., Ltd

C9

C10

C12, C13, C14

C16

C17

C18

R1, R8, R9, R10

-

R2, R3, R7

R4

R5

R6

U1

JOHANSON TECHNOLOGY

U2

U3

Mini Circuits

X1, X8

X2

3.3 nH inductors CS (0402)

1.2 pF capacitor COG (0402)

0 Ohm resistor (0402)

Coilcraft, Inc

Murata Manufacturing Co., Ltd

X3

-

X4

NC

-

X5

1.6 pF capacitor COG (0402)

3.9 nH inductor CS (0402)

2 pF capacitor COG (0402)

3.7 nH inductors HQ (0402)

220 nH inductors CS (1206)

Murata Manufacturing Co., Ltd

Coilcraft, Inc

X6

X7

Murata Manufacturing Co., Ltd

L1, L2

L3, L4

Coilcraft, Inc

Note:

1

2

For optimum performance a low-noise 3.3 V power supply must be used.

The 3.3 V and 5 V power supplies are split in order to maximize the isolation between RF,

LO, IF and digital sections.

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Doc ID 018355 Rev 5

STW82100B

Application information

11.2

Standard Mode Operation

The STW82100B can be used in Standard Mode for both RX path and TX observation path

(RX Chain ON and Synthesizer ON).

In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to

calibrate the signal level at the input of the device.

Figure 26. Standard mode operation

I_PINDRV1

STW82100B

DAC

I_PINDRV2

5V

RF_IN2

RF_IN

4:1

IF_OUT

IF_OUTP

IF_OUTN

IF AMP

DBUS

RF_VSS

RF_CT

50 Ω

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

MIXDRV_CT

VCO

calibrator

MIX

DRV

CAL_VCO

REF_CLK

BUF

DIV2

LOCK_DET

UP

DN

PLL

PFD

CHP

REXT_CP

VCO

BUFF

CAL_VCO

ICP

VCTRL

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Application information

STW82100B

11.3

Diversity mode operation with same LO frequency

The STW82100B supports the Diversity mode with the same LO frequency by using one

STW82100B in Master Mode (RX Chain ON, Synthesizer ON and LO output buffer ON) and

the other in Slave Mode (RX Chain ON, Synthesizer OFF and EXT VCO/LO buffer ON). This

operation mode is suitable for antenna diversity.

Figure 27. Diversity mode operation with same LO frequencies

5V

STW82100B Master

RF_IN_M

RF_IN

4:1

IF_M

IF_OUTP

IF_OUTN

IF AMP

DBUS

RF_VSS

RF_CT

50 Ω

DBUS_SEL

to DAC

SDA/DATA

SCL/CLK

LOAD

5V

MIXDRV_CT

MIX

DRV

VCO

calibrator

CAL_VCO

3.3V

REF_CLK

50 Ω

BUF

OUTBUFP

LO

OUT

DIV2

OUTBUFN

LOCK_DET

UP

DN

PLL

PFD

CHP

REXT_CP

VCO

BUFF

CAL_VCO

ICP

VCTRL

STW82100B Slave

EXTVCO_INP

EXT

LO/VCO

BUF

100 Ω

EXTVCO_INN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

DBUS

MIX

DRV

5V

MIXDRV_CT

RF_IN_S

RF_IN

4:1

IF_S

IF_OUTP

IF_OUTN

IF AMP

RF_VSS

RF_CT

50 Ω

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Doc ID 018355 Rev 5

STW82100B

Application information

11.4

Diversity mode operation with different LO frequencies

The STW82100B is particularly suitable for Diversity schemes using different LO

frequencies such as the Interferer Diversity. In these schemes two STW82100Bs are used,

each one set in Standard Mode and with different LO frequencies.

Figure 28. Diversity mode operation with different LO frequencies

5V

STW82100B Master

RF_IN1

RF_IN

RF_VSS

RF_CT

4:1

IF_OUT1

IF_OUTP

IF_OUTN

IF AMP

DBUS

50 Ω

LO1

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

MIXDRV_CT

MIX

DRV

VCO

calibrator

CAL_VCO

REF_CLK

BUF

DIV2

LOCK_DET

UP

DN

PLL

PFD

CHP

REXT_CP

VCO

BUFF

CAL_VCO

ICP

VCTRL

5V

RF_IN2

RF_IN

RF_VSS

RF_CT

4:1

IF_OUT2

STW82100B Diversity

IF_OUTP

IF_OUTN

IF AMP

50 Ω

LO2

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

DBUS

MIXDRV_CT

MIX

DRV

VCO

calibrator

CAL_VCO

REF_CLK

BUF

DIV2

LOCK_DET

UP

DN

PLL

PFD

CHP

REXT_CP

VCO

BUFF

CAL_VCO

ICP

VCTRL

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Application information

STW82100B

11.5

External VCO standard mode operation

The STW82100B can be used in Ext VCO Mode for both RX path and TX observation path

(RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON and with an external VCO).

In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to

calibrate the signal level at the input of the device.

Figure 29. External VCO standard mode operation

I_PINDRV1

STW82100B

DAC

I_PINDRV2

5V

RF_IN2

RF_IN

4:1

IF_OUT

RF_IN

RF_VSS

RF_CT

IF_OUTP

IF_OUTN

IF AMP

DBUS

50 Ω

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

MIXDRV_CT

MIX

DRV

REF_CLK

BUF

LOCK_DET

REXT_CP

UP

DN

PLL

PFD

CHP

EXT

LO/VCO

BUF

ICP

EXTVCO_INP

EXTVCO_INN

EXTERNAL

VCO

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Doc ID 018355 Rev 5

STW82100B

Application information

11.6

External VCO diversity mode operation with same LO

The STW82100B can be used in Diversity mode using one STW82100B in Master Mode

(RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON, LO output buffer ON and with an

external VCO) and the other one in Slave Mode (RX Chain ON, Synthesizer OFF and EXT

VCO/LO buffer ON).

Figure 30. External VCO diversity mode operation with same LO

STW82100B Master

5V

RF_IN_M

RF_IN

4:1

IF_M

IF_OUTP

IF_OUTN

IF AMP

RF_VSS

50 Ω

RF_CT

to DAC

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

5V

DBUS

MIXDRV_CT

MIX

DRV

REF_CLK

3.3V

BUF

50 Ω

LO/2xLO

OUT

OUTBUFP

OUTBUFN

LOCK_DET

REXT_CP

UP

DN

PLL

PFD

CHP

VCO

BUFF

ICP

EXTVCO_INP

EXTVCO_INN

EXTERNAL

VCO

EXTVCO_INP

100 Ω

STW82100B Slave

EXT

LO/VCO

BUF

EXTVCO_INN

DBUS_SEL

SDA/DATA

SCL/CLK

LOAD

DBUS

MIX

DRV

5V

MIXDRV_CT

RF_IN_S

4:1

IF_S

RF_IN

IF_OUTP

IF_OUTN

IF AMP

RF_VSS

RF_CT

50 Ω

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Evaluation kit

STW82100B

12

Evaluation kit

An evaluation kit can be delivered upon request, including the following:

●

Evaluation board

GUI (graphical user interface) to program the device

PLLSim software for PLL loop filter design and noise simulation

When ordering, please specify the following order code:

Table 23. Evaluation kit order code

Part number

Description

STW82100B evaluation kit, 1.6 to 2.4 GHz RF frequency range

STW82100B-EVB

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Doc ID 018355 Rev 5

STW82100B

Package mechanical data

13

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Figure 31. VFQFPN-44 package outline

Doc ID 018355 Rev 5

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Package mechanical data

STW82100B

Table 24. VFQFPN-44 package dimensions

Dimensions in mm

Typ

Symbol

Min

Max

A

0.80

0.90

0.02

0.65

0.200

0.25

7.00

6.750

3.90

4.90

7.00

6.750

3.90

4.90

0.50

0.55

-

1.00

0.05

1.00

-

A1

A2

A3

b

-

0.18

0.30

7.15

-

D

6.85

D1

D2

D3

E

-

3.80

4.00

-

6.85

7.15

-

E1

E2

E3

e

-

3.80

4.00

-

L

0.35

0.75

0.60

12

P

-

K (degree)

ddd

-

0.08

Note:

1

2

VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead.

Very thin: A=1.00 Max.

Details of terminal 1 identifier are optional but must be located on the top surface of the

package by using either a mold or marked features.

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STW82100B

Revision history

14

Revision history

Table 25. Document revision history

Date

Revision

Changes

14-Jan-2011

1

First release

Corrected cover-page description paragraph tag

Table 11 and Table 12:

07-Mar-2011

2

– corrected introductory sentence

– aligned titles with corporate rules

Corrected RF range on cover page and in Table 6: Down converter mixer and

IF amplifier electrical characteristics

Updated description of bitfield MUTE_TYPE in Mute and calibration control

register

Removed Section 4.4.1: Default configuration

Added Section 9.4.2: Power ON sequence (I2C interface)

Updated Figure 23: SPI timing waveforms

29-Jun-2011

3

Updated Table 20: SPI timing parameters

Updated description of bitfield MUTE_TYPE in SPI register 2

Updated description of bitfield PD[4:0] in SPI register 3

Removed Section 5.4.1: Default configuration

Added Section 10.4.2: Power ON sequence (SPI interface)

Removed ‘Preliminary Data’ tags from cover page.

Table 3 moved to new Section 3: Absolute maximum ratings

Section 2.1 becomes Section 4: Operating conditions

Secction 2.2 becomes Section 5: Test conditions

Section 2.3 becomes Section 6: Electrical characteristics

Table 3: Absolute maximum ratings pins 31 and 32 changed from 0.7 to 0.8 kV

ESD rating.

Table 4: Operating conditions updated current consumption:

– I_CC3.3V. Updated typical values for Diversity Master mode and external VCO

diversity master mode. Added maximum values.

10-Jan-2012

4

– I_CC5V. Added maximum values.

Section 6: Electrical characteristics. Added note about Vsupply, RF frequency

range, ambient temperature and RF power conditons.

Table 6: Down converter mixer and IF amplifier electrical characteristics :

– added Max value for CG

– added Min values for IIP3

– modified typical value of nFRF-nFLO at 3FRF-3FLO FRFin = -5 dBm,

FIF = 150 MHz condition.

– modified LO to IF leakage typical value

– modified IF_RLtypical value

– modified ICC_MDtypical value on 3.3 V supply (pin 41, 42)

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Revision history

STW82100B

Table 25. Document revision history (continued)

Date

Revision

Changes

Table 8: Integer-N synthesizer electrical characteristics updated:

– K_VCOAand K_VCOBvalue

– ΔT_LKsplit into ΔT_{LK A}and ΔT_{LK B}(for VCOA and VCOB). Specified as

maximum values.

– I2_{LOBUF, LOBUF, PLL}and I_PREvalues

I

– Added table footnote 4

Table 9: Phase noise performance updated values of:

– Integrated Phase Noise (single sided) 100 Hz to 40 MHz

– LOA open-loop phase noise @ 1 kHz and 10 kHz

– LOB open-loop phase noise @ 1 kHz and 100 kHz

Added Section 7: Typical performance characteristics.

Modified sub-sections;

10-Jan-2012

4

– VCO frequency calibration

– VCO calibration auto-restart feature

Updated description of bitfield CALTYPE in registers

– MUTE_&_CALIBRATION

– ST2

Added Section 12: Evaluation kit.

Corrected RF range lower value on cover page.

Replaced occurrences of ‘STI register’ with ‘SPI register’ in section headers:

– Section 10.3: SPI registers

10-May-2012

5

– Section 10.3.1: SPI register summary

– Section 10.3.2: SPI register definitions.

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Doc ID 018355 Rev 5

STW82100B

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型号：	STW82100B
厂家：	ST
描述：	RF down converter with embedded integer-N synthesizer 射频降频转换器采用嵌入式整数N频率合成转换器射频
文件：	总67页 (文件大小：753K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STW82100B [STMICROELECTRONICS]

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