STL75N3LLZH5 [STMICROELECTRONICS]
19A, 30V, 0.0078ohm, N-CHANNEL, Si, POWER, MOSFET, 6 X 5 MM, ROHS COMPLIANT, POWERFLAT-8;
| 型号： | STL75N3LLZH5 |
| 厂家： | 
ST |
| 描述： | 19A, 30V, 0.0078ohm, N-CHANNEL, Si, POWER, MOSFET, 6 X 5 MM, ROHS COMPLIANT, POWERFLAT-8 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总9页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STL75N3LLZH5
N-channel 30 V, 0.0055 Ω, 19 A PowerFLAT™ (5x6)
STripFET™ V Power MOSFET
Preliminary data
Features
RDS(on)
max
<0.0061 Ω 19 A (1)
Type
VDSS
30 V
ID
STL75N3LLZH5
1. The value is rated according Rthj-pcb
■ R
* Q industry benchmark
DS(on)
g
■ Extremely low on-resistance R
DS(on)
PowerFLAT™ ( 5x6 )
■ Very low switching gate charge
■ High avalanche ruggedness
■ Low gate drive power losses
■ Built in G-S Zener diodes
Application
Figure 1.
Internal schematic diagram
■ Switching applications
Description
The STL75N3LLZH5 is an N-channel
STripFET™V Power MOSFET which has been
designed to achieve very low on-state resistance
providing also one of the best-in-class figure of
merit (FOM).
Table 1.
Order code
STL75N3LLZH5
Device summary
Marking
Package
Packaging
75N3LLZH5
PowerFLAT™ (5x6)
Tape and reel
July 2010
Doc ID 17661 Rev 2
1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
9
Electrical ratings
STL75N3LLZH5
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
30
18
Unit
VDS
VGS
Drain-source voltage (VGS = 0)
Gate-source voltage
V
V
(1)
ID
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC=100°C
Drain current (pulsed)
75
47
A
(1)
ID
A
(2)
ID
19
A
(2)
ID
11.8
76
A
(3)
IDM
A
(1)
PTOT
Total dissipation at TC = 25°C
Total dissipation at TC = 25°C
Derating factor
60
W
W
W/°C
(2)
PTOT
4
0.03
TJ
Operating junction temperature
Storage temperature
-55 to 150
°C
Tstg
1. The value is rated according Rthj-c
.
2. The value is rated according Rthj-pcb.
3. Pulse width limited by safe operating area.
Table 3.
Symbol
Thermal resistance
Parameter
Value
Unit
Thermal resistance junction-case (Drain) (steady
state)
Rthj-case
2.08
31.3
°C/W
°C/W
(1)
Rthj-pcb
Thermal resistance junction-ambient
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
2/9
Doc ID 17661 Rev 2
STL75N3LLZH5
Electrical characteristics
2
Electrical characteristics
(T
= 25 °C unless otherwise specified).
CASE
Table 4.
Symbol
On/off states
Parameter
Test conditions
Min. Typ.
Max. Unit
Drain-source breakdown
voltage
V(BR)DSS
ID = 250 µA, VGS= 0
30
V
VDS = max rating,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = max rating @125 °C
10
Gate body leakage current
(VDS = 0)
IGSS
VGS
=
18 V
±10
µA
V
VGS(th) Gate threshold voltage
VDS= VGS, ID = 250 µA
1
VGS= 10 V, ID= 9.5 A
VGS= 4.5 V, ID= 9.5 A
0.0055 0.0061
0.0066 0.0078
Ω
Ω
Static drain-source on
resistance
RDS(on)
Table 5.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Input capacitance
Ciss
Coss
Crss
1510
287
40
pF
pF
pF
Output capacitance
VDS =25 V, f=1 MHz,
VGS=0
-
-
-
-
Reverse transfer
capacitance
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD=15 V, ID = 19 A
VGS =4.5 V
11.8
4
nC
nC
nC
Figure 3
6
Table 6.
Symbol
Switching times
Parameter
Test conditions
Min.
Typ. Max. Unit
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
9.2
11
55
20
ns
ns
ns
ns
VDD=15 V, ID= 9.5 A,
RG=4.7 Ω, VGS=10 V
Figure 2
-
-
Turn-off delay time
Fall time
Doc ID 17661 Rev 2
3/9
Electrical characteristics
STL75N3LLZH5
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min Typ. Max Unit
ISD
Source-drain current
-
-
-
19
76
A
A
V
(1)
ISDM
Source-drain current (pulsed)
Forward on voltage
(2)
VSD
ISD = 19 A, VGS=0
1.1
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 19 A,
24
17
ns
nC
A
Qrr
di/dt = 100 A/µs,
VDD=25 V, Tj=150 °C
-
IRRM
1.4
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration= 300 µs, duty cycle 1.5%.
4/9
Doc ID 17661 Rev 2
STL75N3LLZH5
Test circuits
3
Test circuits
Figure 2. Switching times test circuit for
resistive load
Figure 3. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
2200
3.3
µF
RL
µF
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
D.U.T.
VG
VD
RG
VGS
2200
µF
D.U.T.
2.7kΩ
47kΩ
PW
1kΩ
PW
AM01468v1
AM01469v1
Figure 4. Test circuit for inductive load
switching and diode recovery times
Figure 5. Unclamped inductive load test
circuit
L
A
A
A
B
D
FAST
DIODE
L=100µH
VD
G
2200
µF
D.U.T.
B
3.3
µF
VDD
S
3.3
µF
1000
µF
B
VDD
25
Ω
ID
D
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 6. Unclamped inductive waveform
Figure 7. Switching time waveform
ton
toff
tdoff
V(BR)DSS
tr
tf
tdon
VD
90%
10%
90%
IDM
10%
VDS
ID
0
0
VDD
VDD
90%
VGS
10%
AM01472v1
AM01473v1
Doc ID 17661 Rev 2
5/9
Package mechanical data
STL75N3LLZH5
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
6/9
Doc ID 17661 Rev 2
STL75N3LLZH5
Package mechanical data
Table 8.
Power FLAT™ (5x6) mechanical data
mm.
inch.
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
A1
A3
b
0.80
0.83
0.02
0.20
0.40
5.00
4.75
4.20
6.00
5.75
3.48
2.63
1.27
0.80
0.93
0.05
0.031
0.32
0.0007
0.007
0.015
0.196
0.187
0.165
0.236
0.226
0.137
0.103
0.050
0.031
0.036
0.0019
0.35
4.15
0.47
4.25
0.013
0.163
0.135
0.027
0.018
0.167
D
D1
D2
E
E1
E2
E4
e
3.43
2.58
3.53
2.68
0.139
0.105
L
0.70
0.90
0.035
Figure 8.
Power FLAT™ (5x6) drawing
Doc ID 17661 Rev 2
7/9
Revision history
STL75N3LLZH5
5
Revision history
Table 9.
Date
Document revision history
Revision
Changes
22-Jun-2010
08-Jul-2010
1
2
First release.
Modified VGS in Table 2: Absolute maximum ratings and Table 4:
On/off states.
8/9
Doc ID 17661 Rev 2
STL75N3LLZH5
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Doc ID 17661 Rev 2
9/9
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