STL75NH3LL [STMICROELECTRONICS]
N-channel 30 V, 0.004 ヘ, 20 A, PowerFLAT⑩ (6x5) ultra low gate charge STripFET⑩ Power MOSFET; N沟道30 V ， 0.004ヘ， 20 A ， PowerFLAT⑩ （引脚6x5 ）超低栅极电荷STripFET⑩功率MOSFET
| 型号： | STL75NH3LL |
| 厂家： | 
ST |
| 描述： | N-channel 30 V, 0.004 ヘ, 20 A, PowerFLAT⑩ (6x5) ultra low gate charge STripFET⑩ Power MOSFET |
| 文件： | 总12页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STL75NH3LL
N-channel 30 V, 0.004 Ω, 20 A, PowerFLAT™ (6x5)
ultra low gate charge STripFET™ Power MOSFET
Features
RDS(on)
max
< 0.0057 Ω 20 A (1)
Type
VDSS
30V
ID
STL75NH3LL
1. This value is according Rthj-pcb
■ Improved die-to-footprint ratio
■ Very low profile package (1mm max)
■ Very low thermal resistance
■ Very low gate charge
PowerFLAT™(6x5)
■ Low threshold device
Application
Figure 1.
Internal schematic diagram
■ Switching applications
Description
This application specific Power MOSFET is the
latest generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor
is optimized for low on-resistance and minimal
gate charge. The chip-scaled PowerFLAT™
package allows a significant board space saving,
still boosting the performance.
Table 1.
Order code
STL75NH3LL
Device summary
Marking
Package
Packaging
L75NH3LL
PowerFLAT™ (6 x 5)
Tape and reel
June 2008
Rev 1
1/12
www.st.com
12
Contents
STL75NH3LL
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
STL75NH3LL
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
30
16
Unit
VDS
VGS
Drain-source voltage (VGS = 0)
Gate-source voltage
V
V
(1)
ID
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC = 100 °C
Drain current (pulsed)
75
47
A
(1)
ID
A
(2)
ID
20
A
(2)
ID
12.5
80
A
(3)
IDM
A
(1)
PTOT
Total dissipation at TC = 25 °C
Total dissipation at TC = 25 °C
Derating factor
60
W
W
W/°C
(2)
PTOT
4
0.03
Tj
Operating junction temperature
Storage temperature
-55 to 150
°C
Tstg
1. The value is rated according Rthj-C
2. This value is according Rthj-pcb
3. Pulse width limited by safe operating area
Table 3.
Symbol
Thermal resistance
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case (drain) max
Thermal resistance junction-pcb max
2.08
31.3
°C/W
°C/W
(1)
Rthj-pcb
1. When mounted on FR-4 board of 1inch2, 2 oz Cu, t < 10 sec
3/12
Electrical characteristics
STL75NH3LL
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 4.
Symbol
On/off states
Parameter
Test conditions
Min.
Typ.
Max. Unit
Drain-source breakdown
voltage
V(BR)DSS
ID = 250 µA, VGS= 0
30
V
VDS = Max rating,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = Max rating,@125 °C
10
Gate body leakage current
(VDS = 0)
IGSS
VDS
=
16 V
100
nA
V
VGS(th) Gate threshold voltage
VDS = VGS, ID = 250 µA
1
VGS= 10 V, ID= 10 A
VGS= 4.5 V, ID= 10 A
0.004 0.0057
0.005 0.0075
Ω
Ω
Static drain-source on
resistance
RDS(on)
Table 5.
Symbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
Input capacitance
Ciss
Coss
Crss
1810
565
41
pF
pF
pF
Output capacitance
VDS = 25 V, f = 1 MHz,
VGS=0
Reverse transfer
capacitance
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 15 V, ID = 20 A,
VGS = 4.5 V
18
4.8
5.3
24
3
nC
nC
nC
(see Figure 14)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
RG
Gate input resistance
0.5
1.5
Ω
4/12
STL75NH3LL
Electrical characteristics
Min. Typ. Max. Unit
Table 6.
Switching times
Parameter
Symbol
Test conditions
VDD = 15 V, ID = 10 A
RG= 4.7 Ω, VGS= 10 V
(see Figure 16)
td(on)
tr
Turn-on delay time
Rise time
8
ns
ns
65
VDD = 15 V, ID = 10 A
RG= 4.7 Ω, VGS= 10 V
(see Figure 16)
td(off)
tf
Turn-off delay time
Fall time
30
20
ns
ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min Typ. Max Unit
ISD
Source-drain current
20
80
A
A
ISDM
Source-drain current (pulsed)
(1)
VSD
Forward on voltage
ISD = 20 A, VGS = 0
1.3
V
ISD = 20 A,
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
22
32
ns
nC
A
di/dt = 100 A/µs
VDD = 20 V
Qrr
IRRM
1.9
(see Figure 15)
1. Pulsed: Pulse duration = 300µs, duty cycle 1.5%
5/12
Electrical characteristics
STL75NH3LL
2.1
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
Figure 4. Output characteristics
Figure 5. Transfer characteristics
Figure 6. Normalized B
vs temperature
Figure 7. Static drain-source on resistance
VDSS
6/12
STL75NH3LL
Electrical characteristics
Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature
temperature
Figure 12. Source-drain diode forward
characteristics
7/12
Test circuits
STL75NH3LL
3
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
switching and diode recovery times
Figure 16. Unclamped inductive load test
circuit
Figure 17. Unclamped inductive waveform
Figure 18. Switching time waveform
8/12
STL75NH3LL
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STL75NH3LL
PowerFLAT™ (6x5) MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
0.83
0.02
0.20
0.40
5.00
4.75
4.20
6.00
5.75
3.48
2.63
1.27
0.80
MAX.
0.93
0.05
MIN.
MAX.
0.036
A
A1
A3
b
0.80
0.031
0.032
0.0007
0.007
0.015
0.196
0.187
0.165
0.236
0.226
0.137
0.103
0.050
0.031
0.0019
0.35
4.15
0.47
4.25
0.013
0.163
0.135
0.027
0.018
0.167
D
D1
D2
E
E1
E2
E4
e
3.43
2.58
3.53
2.68
0.139
0.105
L
0.70
0.90
0.035
10/12
STL75NH3LL
Revision history
5
Revision history
Table 8.
Date
12-Jun-2008
Document revision history
Revision
Changes
1
First release
11/12
STL75NH3LL
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