STL7NM60N [STMICROELECTRONICS]
Low input capacitance and gate charge, Low gate input resistance; 低输入电容和栅极电荷，低栅极输入电阻
| 型号： | STL7NM60N |
| 厂家： | 
ST |
| 描述： | Low input capacitance and gate charge, Low gate input resistance |
| 文件： | 总13页 (文件大小：786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STL7NM60N
N-channel 600 V, 0.805 Ω, 5.8 A PowerFLAT™ 5x5
MDmesh™ II Power MOSFET
Features
VDSS @
TJMAX
RDS(on)
max.
7
Order code
ID
8
5
STL7NM60N
650 V
< 0.90 Ω
5.8 A(1)
11
4
1. The value is rated according Rthj-case
12
■ 100% avalanche tested
1
14
■ Low input capacitance and gate charge
■ Low gate input resistance
PowerFLAT™ 5x5
Application
■ Switching applications
Description
Figure 1.
Internal schematic diagram
D
D
D
This device is an N-channel Power MOSFET
developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. It is
therefore suitable for the most demanding high
efficiency converters.
13
12
14
11 G
10 S
9 S
Pin 1
(not connected)
S 2
S 3
S 4
Drain
8 S
5
6
7
D
D
D
Top view
Table 1.
Order code
STL7NM60N
Device summary
Marking
Package
Packaging
Tape and reel
7NM60N
PowerFLAT™ 5x5
November 2011
Doc ID 18348 Rev 2
1/13
www.st.com
13
Contents
STL7NM60N
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuits
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
Doc ID 18348 Rev 2
STL7NM60N
Electrical ratings
1
Electrical ratings
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDS
VGS
Drain-source voltage
Gate-source voltage
600
25
V
V
(1)
ID
Drain current (continuous) at TC = 25 °C
Drain current (continuous) at TC=100 °C
Drain current (continuous) at Tamb = 25 °C
Drain current (continuous) at Tamb =100 °C
Drain current (pulsed)
5.8
3.7
1.4
0.9
5.6
4
A
(1)
ID
A
(2)
ID
A
(2)
ID
A
(2)(3)
IDM
A
(2)
PTOT
Total dissipation at Tamb = 25 °C
W
W
A
(1)
PTOT
Total dissipation at TC = 25 °C
68
2
IAS
Avalanche current, repetitive or not-repetitive (3)
Single pulse avalanche energy (4)
Peak diode recovery voltage slope
EAS
119
15
mJ
V/ns
dv/dt (5)
TJ
Operating junction temperature
storage temperature
-55 to 150
°C
Tstg
1. The value is rated according Rthj-case
.
2. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
3. Pulse width limited by Tjmax
4. Starting Tj = 25 °C, ID= IAS, VDD = 50 V
5. ISD ≤ 5.8 A, dv/dt ≤ 400 A/µs,VDS peak ≤V(BR)DSS, VDD= 80% V(BR)DSS.
Table 3.
Symbol
Thermal resistance
Parameter
Value
Unit
Rthj-case
Thermal resistance junction-case max.
Thermal resistance junction-amb max.
1.85
31.3
°C/W
°C/W
(1)
Rthj-amb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec.
Doc ID 18348 Rev 2
3/13
Electrical characteristics
STL7NM60N
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 4.
On/off states
Symbol
Parameter
Test conditions
ID = 1 mA
Min.
Typ.
Max.
Unit
Drain-source breakdown
voltage (VGS= 0)
V(BR)DSS
600
V
VDS = 600 V,
1
µA
µA
Zero gate voltage drain
current (VGS = 0)
IDSS
VDS = 600 V, Tc = 125 °C
100
Gate body leakage current
(VDS = 0)
IGSS
VGS
VDS= VGS, ID = 250 µA
GS= 10 V, ID= 2.5 A
=
25 V
100
4
nA
V
VGS(th) Gate threshold voltage
2
3
Static drain-source on
resistance
RDS(on)
V
0.805
0.90
Ω
Table 5.
Dynamic
Parameter
Symbol
Test conditions
Min. Typ.
Max.
Unit
Input capacitance
Ciss
Coss
Crss
363
pF
pF
pF
Output capacitance
VDS = 50V, f=1 MHz,
VGS=0
-
24.6
1.1
-
Reverse transfer
capacitance
Co(s1s)eq. Output equivalent
capacitance
VGS =0, VDS =0 to 480 V
-
-
130
5.4
-
-
pF
f=1 MHz gate DC bias=0
test signal level = 20 mV
open drain
Rg
Gate input resistance
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD= 480 V, ID = 5 A
VGS =10 V
14
2.7
2.7
nC
nC
nC
-
-
(see Figure 15)
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 6.
Switching times
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
7
ns
ns
ns
ns
VDD= 300 V, ID = 2.5 A,
RG= 4.7 Ω, VGS = 10 V
(see Figure 14)
10
26
12
Turn-off delay time
Fall time
4/13
Doc ID 18348 Rev 2
STL7NM60N
Electrical characteristics
Table 7.
Source drain diode
Symbol
Parameter
Test conditions
Min Typ. Max Unit
ISD
Source-drain current
5.8
23
A
A
V
-
-
(1) (2)
ISDM
Source-drain current (pulsed)
Forward on voltage
,
(3)
VSD
ISD= 5 A, VGS=0
1.3
ISD= 5 A,
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
213
1.5
14
ns
nC
A
di/dt = 100 A/µs,
VDD = 60 V
Qrr
-
-
IRRM
(see Figure 16)
ISD= 5 A,
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
265
1.8
14
ns
nC
A
di/dt = 100 A/µs,
VDD = 60 V, Tj= 150 °C
(see Figure 16)
Qrr
IRRM
1. Pulse width limited by safe operating area.
2. When mounted on FR-4 board of 1inch², 2 oz Cu.
3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Doc ID 18348 Rev 2
5/13
Electrical characteristics
STL7NM60N
2.1
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
AM07211v1
I
D
(A)
Tj=150°C
Tc=25°C
Single pulse
10
10µs
1
100µs
0.1
1ms
10ms
0.01
0.001
10
V
DS(V)
0.1
1
100
Figure 4. Output characteristics
Figure 5. Transfer characteristics
AM06477v1
AM06478v1
10
I
D
(A)
9
V
GS=10V
VDS=20V
9
8
7
6V
8
7
6
5
4
6
5
I
D
(A)
4
5V
3
3
2
2
1
0
0
1
0
0
2
20
40
V
DS(V)
8
10
VGS(V)
10
4
6
Figure 6.
Gate charge vs gate-source voltage Figure 7. Static drain-source on resistance
AM06479v1
AM06480v1
V
DS
(V)
V
(V)
GS
R
DS(on)
(Ohm)
V
DD=480V
=5A
V
GS=10V
0.88
12
10
8
I
D
500
VDS
0.86
0.84
0.82
400
300
200
6
0.80
4
2
0
0.78
0.76
0.74
100
0
2
3
4
5
1
6
12
14 16
Qg(nC)
ID(A)
10
0
2
4
8
0
6/13
Doc ID 18348 Rev 2
STL7NM60N
Electrical characteristics
Figure 8. Capacitance variations
Figure 9.
Output capacitance stored energy
AM06481v1
AM06482v1
C
Eoss
(pF)
(µJ)
2.5
2.0
1000
100
Ciss
1.5
1.0
Coss
Crss
10
1
0.5
0
0.1
100
200
400 500
600
1
10
V
DS(V)
0
100
300
VDS(V)
Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs
vs temperature temperature
AM06483v1
AM06484v1
V
GS(th)
(norm)
R
DS(on)
(norm)
ID=2.5A
2.1
1.10
ID=250µA
1.9
1.00
0.90
1.7
1.5
1.3
1.1
0.9
0.80
0.7
0.5
-50
-25
0.70
-50
-25
0
25 50 75
TJ(°C)
0
25 50 75
TJ(°C)
100
100
Figure 12. Normalized B
vs temperature
Figure 13. Source-drain diode forward
characteristics
VDSS
AM09028v1
AM08913v1
V
DS
VSD
(V)
(norm)
ID=1mA
1.10
TJ
=-50°C
1.2
1.08
TJ=25°C
1.0
1.06
1.04
1.02
1.00
0.98
0.96
0.8
0.6
0.4
TJ=150°C
0.2
0
0.94
0.92
-50
0
7
-25
0
25 50 75
TJ
(°C)
1
2
3
4
5
6
ISD(A)
100
Doc ID 18348 Rev 2
7/13
Test circuits
STL7NM60N
3
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
2200
3.3
µF
RL
µF
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
D.U.T.
VG
VD
RG
VGS
2200
µF
D.U.T.
2.7kΩ
47kΩ
PW
1kΩ
PW
AM01468v1
AM01469v1
Figure 16. Test circuit for inductive load
switching and diode recovery times
Figure 17. Unclamped inductive load test
circuit
L
A
A
A
B
D
FAST
DIODE
L=100µH
VD
G
2200
µF
D.U.T.
B
3.3
µF
VDD
S
3.3
µF
1000
µF
B
VDD
25
Ω
ID
D
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
ton
tdon
toff
tdoff
V(BR)DSS
tr
tf
VD
90%
10%
90%
IDM
10%
VDS
ID
0
0
VDD
VDD
90%
VGS
10%
AM01472v1
AM01473v1
8/13
Doc ID 18348 Rev 2
STL7NM60N
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Doc ID 18348 Rev 2
9/13
Package mechanical data
STL7NM60N
Table 8.
PowerFLAT™ 5x5 mechanical dimensions
mm
Dim.
Min.
Typ.
Max.
A
A1
A3
D
0.80
0
0.90
0.02
0.24
5.0
1.0
0.05
4.90
4.90
2.49
1.22
0.43
0.64
5.10
5.10
2.64
1.32
0.58
0.79
E
5.0
E2
e
2.57
1.27
0.51
0.71
b
c
Figure 20. PowerFLAT™ 5x5 mechanical drawing
10/13
Doc ID 18348 Rev 2
STL7NM60N
Package mechanical data
Figure 21. PowerFLAT™ 5x5 recommended footprint (dimensions in mm)
Doc ID 18348 Rev 2
11/13
Revision history
STL7NM60N
5
Revision history
Table 9.
Date
Document revision history
Revision
Changes
18-Jan-2011
10-Nov-2011
1
2
First release.
Updated Figure 1: Internal schematic diagram in cover page.
Updated Table 2: Absolute maximum ratings and Section 4:
Package mechanical data.
Minor text changes.
12/13
Doc ID 18348 Rev 2
STL7NM60N
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Doc ID 18348 Rev 2
13/13
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