STEF12PUR [STMICROELECTRONICS]
Electronic fuse for 12 V line; 电子保险丝12 V线路
| 型号： | STEF12PUR |
| 厂家： | 
ST |
| 描述： | Electronic fuse for 12 V line |
| 文件： | 总20页 (文件大小：1180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STEF12
Electronic fuse for 12 V line
Features
■ Continuous current (typ): 3.6 A
■ N-channel on-resistance (typ): 53 mΩ
■ Enable/Fault functions
■ Output clamp voltage (typ):15 V
■ Undervoltage lockout
■ Short-circuit limit
DFN10 (3 x 3 mm)
■ Overload current limit
■ Controlled output voltage ramp
■ Thermal latch (typ): 165 °C
■ Uses tiny capacitors
persists it goes into an open state, disconnecting
the load from the power supply. If a continuous
short-circuit is present on the board, when power
is re-applied the E-fuse initially limits the output
current to a safe value and then again goes into
an open state. The device is equipped with a
thermal protection circuit. The intervention of the
thermal protection is signalled to the board
monitoring circuits through a signal on the Fault
pin. Unlike the mechanical fuses, which must be
physically replaced after a single event, the E-
fuse does not degrade in its performance after
short-circuit/thermal protection interventions and
it is reset either by recycling the supply voltage or
using the Enable pin. The companion chip for the
5 V power rails is also available with part number
STEF05.
■ Operating junction temp. - 40 °C to 125 °C
■ Available in DFN10 (3 x 3 mm) package
Applications
■ Hard disk drives
■ Solid state drives (SSD)
■ Hard disk and SSD arrays
■ Set-top boxes
■ DVD and Blu-Ray disc drivers
Description
The STEF12 is an integrated electronic fuse
optimized for monitoring output current and input
voltage. Connected in series to a 12 V rail, it is
capable of protecting the electronic circuitry on its
output from overcurrent and overvoltage. The
device has a controlled delay and turn-on time.
When an overload condition occurs, the STEF12
limits the output current to a predefined safe
value. If the anomalous overload condition
Table 1.
Device summary
Order code
Package
Packaging
STEF12PUR
DFN10 (3 x 3 mm)
Tape and reel
December 2011
Doc ID 019056 Rev 3
1/20
www.st.com
20
Contents
STEF12
Contents
1
2
3
4
5
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
Turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
5.3
5.4
R limit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
dv/dt calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Enable/Fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
C
6
7
8
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Doc ID 019056 Rev 3
STEF12
1
Device block diagram
Device block diagram
Figure 1.
STEF12 block diagram
AM09891v1
Doc ID 019056 Rev 3
3/20
Pin configuration
STEF12
2
Pin configuration
Figure 2.
Pin configuration (top view)
GND
dv/dt
En/fault
I-Limit
N/C
Source
Source
Source
Source
Source
VCC
AM09880v1
Table 2.
Pin n°
Pin description
Symbol
Note
1
GND
Ground pin
The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The
internal capacitor allows a ramp-up time of around 1ms. An external capacitor can be
added to this pin to increase the ramp time. If an additional capacitor is not required, this
pin should be left open.
2
dv/dt
The Enable/Fault pin is a tri-state, bi-directional interface. During normal operation the pin
must be left floating, or it can be used to disable the output of the device by pulling it to
ground using an open drain or open collector device.
3
En/Fault
If a thermal fault occurs, the voltage on this pin goes into an intermediate state to signal a
monitor circuit that the device is in thermal shutdown. It can be connected to another
device of this family to cause a simultaneous shutdown during thermal events.
A resistor between this pin and the Source pin sets the overload and short-circuit current
limit levels.
4
5
I-Limit
NC
Not connected
Connected to the source of the internal power MOSFET and to the output terminal of the
fuse
6 to 10 VOUT/Source
11 VCC
Exposed pad. Positive input voltage must be connected to VCC
.
4/20
Doc ID 019056 Rev 3
STEF12
Maximum ratings
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
Positive power supply voltage (steady state)
Positive power supply voltage (max 100ms)
-0.3 to 18
-0.3 to 25
-0.3 to Vcc+0.3
-0.3 to 25
-0.3 to 7
VCC
V
VOUT/source (max 100ms)
V
V
I-Limit
En/Fault
dv/dt
(max 100ms)
V
-0.3 to 7
V
Top
Operating junction temperature range (1)
Storage temperature range
-40 to 125
-65 to 150
260
°C
°C
°C
TSTG
TLEAD
Lead temperature (soldering) 10 sec
1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures
greater than the maximum ratings for extended periods of time.
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Symbol
Thermal data
Parameter
Value
Unit
RthJA
RthJC
Thermal resistance junction-ambient
Thermal resistance junction-case
52.7
17.4
°C/W
°C/W
Table 5.
Symbol
ESD performance
Parameter
Test conditions
Value
Unit
HBM
MM
1
kV
V
ESD
ESD protection
200
500
CDM
V
Doc ID 019056 Rev 3
5/20
Electrical characteristics
STEF12
4
Electrical characteristics
V
= 12 V, V = 3.3 V, C = 10 µF, C = 47 µF, T = 25 °C (unless otherwise specified).
EN I O J
CC
Table 6.
Symbol
Electrical characteristics for STEF12
Parameter Test Conditions
Min.
Typ.
Max. Unit
Under/Overvoltage protection
VClamp
VUVLO
VHyst
Output clamping voltage
Undervoltage lockout
UVLO hysteresis
VCC = 18 V
13.8
7.7
15
8.5
16.2
9.3
V
V
V
Turn-on, voltage rising
0.80
Power MOSFET
Enabling of chip to ID = 100 mA
with a 1 A resistive load
tdly
Delay time
350
53
µs
(1)
35
70
82
RDSon
VOFF
ID
On-resistance
mΩ
mV
A
- 40 °C < TJ < 125 °C (2)
Off state output voltage
Continuous current
VCC = 18 V, VGS = 0, RL = infinite
0.5in2 pad, TA = 25 °C (1)
40
3.6
1.7
100
Minimum copper, TA = 80 °C
Current limit
IShort Short-circuit current limit
ILim
RLimit = 22 Ω
RLimit = 22 Ω
3.3
0.5
4.4
4.4
5.5
2.6
A
A
Overload current limit
dv/dt circuit
Enable to VOUT = 11.7 V, No
Cdv/dt
dv/dt
Output voltage ramp time
0.9
ms
Enable/Fault
VIL
VI(INT)
VIH
Low level input voltage
Output disabled
0.35
0.82
1.96
3.4
0.58
1.4
0.81
1.95
3.3
V
V
Intermediate level input voltage Thermal fault, output disabled
High level input voltage
Output enabled
2.64
4.3
V
VI(MAX)
IIL
High state maximum voltage
Low level input current (sink)
5.4
V
VEnable = 0 V
-10
-30
µA
High level leakage current for
external switch
II
VEnable = 3.3 V
1
3
µA
Total numbers of chips that can
Maximum fan-out for fault signal be connected to this pin for
simultaneous shutdown
Units
Total device
Device operational
Bias current
1.5
1
2
IBias
mA
Thermal shutdown
6/20
Doc ID 019056 Rev 3
STEF12
Electrical characteristics
Table 6.
Symbol
Electrical characteristics for STEF12 (continued)
Parameter
Test Conditions
Min.
Typ.
Max. Unit
Vmin
Minimum operating voltage
7.6
V
Thermal latch
(1)
TSD
Shutdown temperature
165
°C
1. Pulse test: Pulse width = 300 µs, Duty cycle = 2%
2. Guaranteed by design, but not tested in production
Doc ID 019056 Rev 3
7/20
Typical application
STEF12
5
Typical application
Figure 3.
Application circuit
Figure 4.
Typical HDD application circuit
AM09869v1
5.1
Operating modes
5.1.1
Turn-on
When the input voltage is applied, the Enable/Fault pin goes up to the high state, enabling
the internal control circuitry.
After an initial delay time of typically 350 µs, the output voltage is supplied with a slope
defined by the internal dv/dt circuitry. If no additional capacitor is connected to dv/dt pin, the
total time from the Enable signal going high and the output voltage reaching the nominal
value is around 1 ms (refer to Figure 5, 15)
8/20
Doc ID 019056 Rev 3
STEF12
Typical application
5.1.2
Normal operating condition
The STEF12 E-fuse behaves like a mechanical fuse, buffering the circuitry on its output with
the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET
R
.
DSOn
5.1.3
5.1.4
Output voltage clamp
This internal protection circuit clamps the output voltage to a maximum safe value, typically
15 V, if the input voltage exceeds this threshold.
Current limiting
When an overload event occurs, the current limiting circuit reduces the conductivity of the
power MOSFET, in order to clamp the output current at the value selected externally by
means of the limiting resistor R
(Figure 3).
Limit
5.1.5
Thermal shutdown
If the device temperature exceeds the thermal latch threshold, typically 165 °C, the thermal
shutdown circuitry turns the power MOSFET off, thus disconnecting the load. The EN/Fault
pin of the device is automatically set at an intermediate voltage, in order to signal the
overtemperature event. In this condition the E-fuse can be reset either by cycling the supply
voltage or by pulling down the EN pin below the V threshold and then releasing it.
il
5.2
R limit calculation
As shown in Figure 3, the device uses an internal N-channel sense FET with a fixed ratio, to
monitor the output current and limit it at the level set by the user.
The R
value for achieving the requested current limitation can be estimated by using the
Limit
following theoretical formula, together with the graph in Figure 13: Current limit vs. RLimit.
Equation 1
95
RLimit = --------------
IShort
5.3
Cdv/dt calculation
Connecting a capacitor between the C
output voltage ramp-up time.
pin and GND allows the modification of the
dv/dt
Given the desired time interval Δt during which the output voltage goes from zero to its
maximum value, the capacitance to be added on the C
pin can be calculated using the
dv/dt
following theoretical formula:
Equation 2
Cdvdt = 24 × 10–9Δt – 30x10–12
Where C
is expressed in Farads and the time in seconds.
Doc ID 019056 Rev 3
dv/dt
9/20
Typical application
The addition of an external C
STEF12
influences also the initial delay time, defined as the time
dv/dt
between the Enable signal going high and the start of the V
slope (Figure 5).
OUT
The contribution of the external capacitor to this time interval can be estimated by using the
following theoretical formula:
Equation 3
delay time = 350 × 10–6 + 11.3 × 106 × Cdvdt
Figure 5.
Delay time and V
ramp-up time
OUT
AM09882v1
12
En/Fault
delay ramp-up
time time
10
8
VOUT
6
4
2
0
Time
5.4
Enable/Fault pin
The Enable/Fault pin has the dual function of controlling the output of the device and, at the
same time, of providing information about the device status to the application.
When it is used as a standard Enable pin, it should be connected to an external open-drain
or open-collector device. In this case, when it is pulled at low logic level, it turns the output of
the E-Fuse off.
If this pin is left floating, since it has internal pull-up circuitry, the output of the E-Fuse is kept
ON, in normal operating conditions.
In case of thermal fault, the pin is pulled to an intermediate state (Figure 6). This signal can
be provided to a monitor circuit, informing it that a thermal shutdown has occurred, or it can
be directly connected to the Enable/Fault pins of other STEFxx devices on the same
application in order to achieve a simultaneous enable/disable feature.
When a thermal fault occurs, the device can be reset either by cycling the supply voltage or
by pulling down the Enable pin below the V threshold and then releasing it.
il
10/20
Doc ID 019056 Rev 3
STEF12
Typical application
Figure 6.
Enable/Fault pin status
5
4
3
2
1
0
Normal operating condition
Thermal fault condition
Off/Reset
AM09871v1
time
Doc ID 019056 Rev 3
11/20
Typical performance characteristics
STEF12
6
Typical performance characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted,
at T = 25 °C.
A
Figure 7.
Clamping voltage vs. temperature Figure 8.
UVLO voltage vs. temperature
AM09883v1
16.5
AM09884v1
9.5
VCC = from 0 to 12 V, RLIMIT = 15 Ω
VCC = 18 V
9.3
16
15.5
15
9.1
8.9
8.7
8.5
8.3
8.1
7.9
7.7
7.5
14.5
14
13.5
-40
-25
0
25
55
85
125
150
-40
-25
0
25
55
85
125
150
Temperature °C
Temperature °C
Figure 9.
UVLO hysteresis vs. temperature
Figure 10. Off-state voltage vs. temperature
AM09885v1
AM09886v1
1.4
250
200
150
100
50
VCC from 12 to 0 V, RLIMIT = 15 Ω
VCC = 18 V, VGS = 0, RL = infinite
1.2
1
0.8
0.6
0.4
0
0.2
-40
-40
-25
0
25
55
85
125
150
-25
0
25
55
85
125
150
Temperature °C
Temperature °C
Figure 11. Bias current (device operational)
Figure 12. ON resistance vs. temperature
AM09888v1
AM09887v1
90
3
2.5
2
VCC = 12 V, RLIMIT = 15 Ω, ILOAD = 1 A
80
VCC = 12 V, RLIMIT = 15 Ω
70
60
50
40
30
20
1.5
1
0.5
0
-40
-25
0
25
55
85
125
-40
-25
0
25
55
85
125
150
Temperature °C
Temperature °C
12/20
Doc ID 019056 Rev 3
STEF12
Typical performance characteristics
Figure 13. Current limit vs. R
Figure 14. Thermal latch delay vs. power
Limit
AM09890v1
AM09889v1
800
9.00
VCC = 12 V, T = 25 °C
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
T=25 °C
ILIM
80
T=55 °C
T=85 °C
ISHORT
8
0.8
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
External Sensing Resistor (Ω)
Power (W)
Figure 15. V
ramp-up vs. Enable
Figure 16. V
clamping
OUT
OUT
VCC = 12 V, CIN = 10 µF, COUT = 10 µF, RLIMIT = 22 Ω, No
dv/dt, T = 25°C
VCC = 18 V, CIN = 10 µF, RLIMIT = 22 Ω, No Cdv/dt,T = 25°C
C
Figure 17. Line transient
Figure 18. Startup into output short-circuit
VCC = 12 V, RLIMIT = 22 Ω, VOUT = Connected to GND
VCC = from 12 to 18 V RLIMIT = 22 Ω; IOUT = 500 mA, TRISE
= 100 µs
Doc ID 019056 Rev 3
13/20
Typical performance characteristics
STEF12
Figure 19. Thermal latch from 2 A load to
short-circuit
Figure 20. Startup into output short-circuit
(fast rise)
VCC = 12 V, RLIMIT = 22 Ω, VOUT = Connected to GND
14/20
Doc ID 019056 Rev 3
STEF12
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Table 7.
DFN10L mechanical data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
Min.
Max.
A
A1
A3
b
0.70
0
0.75
0.02
0.20
0.25
3
0.80
0.05
0.028
0
0.030
0.001
0.008
0.010
0.118
0.094
0.118
0.065
0.020
0.016
0.031
0.002
0.18
2.90
2.23
2.90
1.49
0.30
3.10
2.48
3.10
1.74
0.007
0.114
0.088
0.114
0.059
0.012
0.122
0.098
0.122
0.069
D
D2
E
2.38
3
E2
e
1.64
0.50
0.40
L
0.30
0.50
0.012
0.020
Doc ID 019056 Rev 3
15/20
Package mechanical data
STEF12
Figure 21. DFN10L package outline
8049731/A
16/20
Doc ID 019056 Rev 3
STEF12
Package mechanical data
Tape & reel QFNxx/DFNxx (3x3) mechanical data
mm.
Typ.
inch.
Typ.
Dim.
Min.
Max.
180
Min.
Max.
7.087
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
14.4
0.567
Ao
Bo
Ko
Po
P
3.3
3.3
1.1
4
0.130
0.130
0.043
0.157
0.315
8
Doc ID 019056 Rev 3
17/20
Package mechanical data
STEF12
Figure 22. DFN10L footprint - recommended data
18/20
Doc ID 019056 Rev 3
STEF12
8
Revision history
Revision history
Table 8.
Document revision history
Revision
Date
Changes
15-Jul-2011
08-Aug-2011
14-Dec-2011
1
2
3
Initial release.
Modified definition for Top in Table 3: Absolute maximum ratings.
Removed Vdv/dt and Idv/dt rows from dv/dt circuit Table 6 on page 6.
Doc ID 019056 Rev 3
19/20
STEF12
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