STEL-1172B/CL [ETC]
Numeric-Controlled Oscillator ; 数字控制振荡器\n
| 型号： | STEL-1172B/CL |
| 厂家： | 
ETC |
| 描述： | Numeric-Controlled Oscillator
|
| 文件： | 总11页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STEL-1172B
Data Sheet
STEL-1172B
(50 MHz)
32-Bit Resolution
CMOS Numerically
Controlled Oscillator
R
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CIRCUIT DESCRIPTION
FEATURES
■ 32 BIT FREQUENCY RESOLUTION
■ PARALLEL SINE AND COSINE
OUTPUTS
■ 50 MHz CLOCK FREQUENCY (0° TO
The STEL-1172B Numerically Controlled Oscillator
(NCO) generates digital sine and cosine signals of very
precise frequency to be used directly in digital signal
processing applications or in conjunction with a D/A
converter in analog frequency generation applications.
The device, implemented with low power CMOS, can
operate with clock frequencies as high as 50 MHz.
(40 MHz over the military temperature range, 55° C to
+125° C). The NCO is designed to interface with an
eight bit microprocessor bus.
70°C)
■ 8-BIT INTERNAL SINE AND COSINE
AMPLITUDE RESOLUTION
■ 10-BIT INTERNAL SINE AND COSINE
PHASE RESOLUTION
■ 12-BIT PHASE OUTPUT AVAILABLE
■ MILITARY AND COMMERCIAL
TEMPERATURE RANGES AVAILABLE
■ MICROPROCESSOR BUS COMPATIBLE
■ PIN COMPATIBLE WITH ST-1172A
■ CASCADABLE FOR ULTRA HIGH
RESOLUTION
■ LOW POWER CMOS
The NCO maintains a record of phase which is accurate
to 32 bits of resolution. At each clock cycle, the number
stored in the 32 bit ∆-phase register is added to the
previous value of the phase accumulator. The number
in the phase accumulator represents the current phase of
thesynthesizedsineandcosinefunctions. Thenumberin
the ∆-phase register represents the change of phase for
each cycle of the clock. This number is directly related
to the output frequency by the following:
APPLICATIONS
■ FREQUENCY SYNTHESIZERS
■ HI-SPEED FREQUENCY HOPPED
SOURCES
■ SINGLE SIDEBAND CONVERTERS
fc x ∆-Phase
fo=
232
■ BASEBAND RECEIVERS
■ DIGITAL SIGNAL PROCESSORS
where: fo is the frequency of the output signal
and: fc is the clock frequency.
BLOCK DIAGRAM
SYNC
CARRY OUT
LDSTB
PHASE
32
2
3-2
Data7-0
WRN
8
COSINE
7-0
COSINE
LOOKUP
TABLE
ADDR.
SELECT
LOGIC
32-BIT
PHASE
ACCUMULATOR
BLOCK
(PHASE
BUFFER
REGISTER
BLOCK
-PHASE
REGISTER
BLOCK
1-0)
32
10
8
BLOCK
BLOCK
MUX
BLOCK
2
PHASE
8
11-4
ADDR1-0
SINE
7-0
CARRY IN
RESET
SINE
LOOKUP
TABLE
(PHASE
11-4)
8
10
CLOCK
BLOCK
2
SELECT A,B
TCP 54836.c
STEL-1172B
2
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FUNCTIONAL DESCRIPTION
The phase noise of the NCO output signal may
be determined by knowing the phase noise of the
clock signal input and the ratio of the output fre-
quency to the clock frequency. This ratio squared
times the phase noise power of the clock specified in a
given bandwidth is the phase noise power that may
be expected in that same bandwidth relative to the
output frequency.
The sine and cosine signals are generated from
the 10 most significant bits of the phase accumulator.
The frequency of the NCO is determined by the
∆−
number stored in the phase register which may be
programmed by an eight-bit microprocessor.
The STEL-1172B NCO generates digitized
sampled sine and cosine signals where the sampling
function is the clock. If the output frequency is very
low with respect to the clock (<fc/1024), then the
NCO output will sequence through each of the 1024
states of the sine function stored in the lookup table.
As the output frequency is increased with respect to
the clock, the sine function appears more discontinu-
ous as there are fewer samples in each cycle. At the
Nyquist limit, when the output frequency is exactly half
the clock, the output waveform reduces to a square
wave. The practical upper limit of the NCO output
frequency is about 40% of the clock frequency
The NCO achieves its high operating frequency
by making extensive use of pipelining in its architec-
ture. The pipeline delays within the NCO represent
34 clock cycles. This effectively limits the minimum
possible frequency switching period of the NCO.
After new frequency data is entered the load com-
mand is given. After the 34 cycle pipeline delay the
output will instantaneously switch frequency while
maintaining phase coherence. After this the next new
frequency may be entered. If a 50 MHz clock were
utilized the NCO could be continuously switched
between programmed frequencies with a minimum
practical average switching time of about 1 µsec.
because spurious components created by sampling,
which are at a frequency greater than half the clock
frequency, become difficult to remove by filtering.
PIN CONFIGURATION
ADDR
COS
ADDR
WRN
1
5
0
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0.2"
max.
0.15" typ.
2
Seating
plane
COS
LDSTB
0.13" typ.
6
3
CARRY IN
CLOCK
V
4
DATA
0
SS
5
0.1" ± 0.01"
COS
DATA
5
2
6
Note: tolerance not cumulative
COS
COS
SIN
DATA
6
1
0
1
7
DATA
2
8
DATA
4
9
0.55"
typ.
SIN
SIN
SIN
DATA
SYNC
DATA
2
3
4
10
11
12
13
14
15
16
17
18
19
20
3
2.00 max.
1
7
SIN
SIN
DATA
RESET
COS
5
7
7
0.6"
(at seating plane)
COS
4
V
V
DD
SS
Package: 40 pin plastic DIP
Thermal coefficient, jc = 15°/W
Note: pin spacing for Ceramic
DIP is the same
SEL B
PHASE
PHASE
SEL A
COS
3
θ
CARRY OUT
2
3
SIN
6
SIN
0
3
STEL-1172B
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FUNCTION BLOCK
DESCRIPTION
INPUT SIGNALS
RESET
The RESET input is synchronous with the CLOCK input.
When RESETgoes to a logic high level all registers except the
32 bit input buffer and ∆-Phase register are cleared within 20
nsecs. of the next rising edge of the CLOCK. The output data
and Phase Accumulator are cleared to zero. After the RESET
returns to a logic zero the chip requires 37 rising clock edges to
resume normal operation. For the first two of these cycles the
output data will be 00H and then 80H, respectively. For the
remaining35clockcyclestheSINandCOSoutputsremainatthe
value corresponding to zero phase, i.e. 129, or 81H. Normal
operation will then commence, starting at zero phase
ADDRESSSELECTLOGICBLOCK
This block controls the writing of data into the device via the
DATA7-0 inputs. Thedataiswrittenintothedeviceonthefalling
edge of the WRN input, and the register into which the data is
written is selected by the ADDR1-0 inputs.
BUFFERREGISTERBLOCK
TheBufferRegisterisusedtotemporarilystorethe∆-Phasedata
written into the device. This allows the data to be written
asynchronouslyasfourbytesper 32-bit∆-Phaseword. Thedata
istransferredfromthisregisterintothe∆-PhaseRegisteraftera
rising edge on the LDSTB input.
CLOCK
All synchronous functions performed within the NCO are
referencedtotherisingedgeoftheCLOCKinput. TheCLOCK
signal should be nominally a square wave at a maximum
frequencyof50MHz. A non-repetitive CLOCK waveformis
permissible as long as the minimum duration positive or
negative pulse on the waveform is always greater than 8
nanoseconds. At each rising edge of the CLOCK signal the
contents of the phase accumulator are added to the number
storedinthe∆-Phaseregister,andtheresultisplacedinthePhase
Accumulator.
∆-PHASEREGISTERBLOCK
This block controls the updating of the ∆-Phase word used in
the Accumulator. The frequency data from the Mux Block is
loaded into this block after a rising edge on the LDSTB input.
The SYNC output, which indicates the instant of frequency
changeattheoutputattheendofthepipelinedelay,isgenerated
in this block.
PHASEACCUMULATORBLOCK
ThisblockformsthecoreoftheNCOfunction. Itisahigh-speed,
pipelined, 32-bit parallel accumulator, generating a new sum in
everyclockcycle. Acarryinput(theCARRYINinput)allowsthe
resolution of the accumulator to be expanded by means of an
auxiliary NCO or phase accumulator. The overflow signal is
discarded (and is available at the CARRY OUT pin), since the
required output is the modulo (232) sum only. This represents
the modulo (2π) phase angle.
WRN
Theinformationonthe8-bitdatabusistransferredtothebuffer
registerselectedby ADDR andADDR onthefallingedgeof
1
0
the WRN input.
LDSTB
On the rising edge of the clock following the rising edge of the
LDSTB input the information in the four buffer registers is
transferredtothe∆-PhaseRegister. ThefrequencyattheNCO
outputwillchange34clockcyclesaftertheLDSTBcommanddue
to pipelining delays.
SINEANDCOSINELOOKUPTABLEBLOCKS
These blocks are the sine and cosine memories. The 10 most
significantbitsfromthePhaseAccumulatorareusedtoaddress
thismemorytogeneratethe8-bit SIN7-0 andCOS7-0 outputs.
ADDR1 andADDR0
TheADDR1andADDR0signalscontroltheuseoftheDATA7-0bus
accordingtothetable:
MUXBLOCK
The twelve most significant bits from the Phase Accumulator
Block are available at the output via the MUX Blocks as
alternativestotheSIN7-0 andCOS7-0 outputs. TheMUXBlocks
are controlled by the SELECT A and SELECT B inputs.
ADDR0 ADDR1
∆-Phase Register Field
1
0
1
0
1
1
0
0
Bits 0 (LSB) through 7
Bits 8 through 15
Bits 16 through 23
Bits 24 through 31 (MSB)
STEL-1172B
4
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OUTPUT SIGNALS
CARRYOUT
The least significant bit oftheinputdatabusalwaysmaps into
the least significant bit of the ∆-Phase Register field.
Each time the contents of the phase accumulator exceeds the
maximum value that can be represented by a 32 bit number the
CARRYOUTsignalgoeshighforoneclockcycle. Whentwo
NCOs are cascaded to obtain 64 bit frequency resolution the
CARRY OUT of the lower order NCO must be connected to
the CARRY IN of the higher order NCO.
DATA7 throughDATA0
TheeightbitDATA7-0 busisusedtoprogramthe32bit∆-Phase
Register. DATA0 istheleastsignificantbitofthebus. Tochange
all 32 bits of the ∆-Phase Register, the DATA7-0 bus must be
sequentially used four times in conjunction with the WRN,
ADDR0 and ADDR1 signals.
SIN7-0 andCOS7-0
Thesineandcosinefunctionswhicharepresentedonthe SIN7-0
andCOS7-0 busesarederivedfromthe10mostsignificantbitsof
the phase accumulator. The 8-bit sine and cosine functions
are presented in offset binary format with a minimum value of
00H andamaximumvalueofFFH. SIN7/COS7 aretheMSBs.
Whenthephaseaccumulatoriszero,thedecimalvalueof theSIN
output is 81H. The nominal phase (in degrees) of the sine and
cosine outputs may be determined by multiplying the decimal
equivalent of the ten most significant bits of the phase
accumulatorby(360/1024)andadding(360/2048). Theaverage
amplitudeoverafullcycleis127.5decimal. Seethedescription
ofSELECTA/BandPHASEforthealternateuseoftheSIN7-
0 and COS7-0 buses.
SELECTA
When SELECTAisalogic0, thesinefunctionappearsonthe
SIN7-0 bus. When SELECT A is a logic 1, the eight most
significantbitsofthephaseaccumulatorappearonthisbus.The
twelvemostsignificantbitsofthe32bitPhaseAccumulatorare
availableexternally. Theeightmostsignificantbitsappearonthe
SIN bus and are labeled PHASE11 (MSB) through PHASE4.
Output
Pin
Pin
Function:
Function:
SELECT A =1
Name SELECT A =0
14
22
13
12
11
10
9
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
SIN7 (MSB)
SIN6
PHASE4
PHASE5
PHASE11-0
SIN5
PHASE6
Thetwelvemostsignificantbitsofthe32bitphaseaccumulator
are available as outputs of the NCO. PHASE11 is the most
significant bit of the 32 bit phase accumulator. The eight most
significant PHASE bits are multiplexed on the SIN bus (see
descriptionofSELECTA input). Thenexttwosignificantbits
(PHASE2 andPHASE3)areavailablecontinuouslyonpins18
and19respectively. Thetwoleastsignificant bits(PHASE1 and
PHASE0) are multiplexed on the COS bus (see description of
SELECT B input).
SIN4
PHASE7
SIN3
PHASE8
SIN2
PHASE9
SIN1
PHASE10
PHASE11 (MSB)
21
SIN0 (LSB)
SELECTB
When SELECT B is a logic 1 the two most significant bits of
thecosinefunctionappearonoutputpins3and15. WhenSelect
B is a logic 0 pin 15 provides the signal PHASE1 and pin 3
provides the signal PHASE0. PHASE1 and PHASE0 are the
eleventh and twelfth most significant bits of the phase
accumulator,withPHASE0 beingtheleastsignificantaccessible
bit.
SYNC
ThenormallyhighSYNCoutputgoeslowforoneclockcycle35
risingclockedgesafteraRESETand34risingclockedgesafter
a LDSTB command. If two NCOs are cascaded for higher
frequencyresolutiontheSYNCoutputofthelowerorderNCO
must be connected to the LDSTB input of the higher order
NCO to insure a phase continuous frequency transition.
CARRYIN
NormaloperationoftheNCOrequiresthattheCARRYINbe
setatalogic0. WhenCARRYINisalogic1theeffectivevalue
of the ∆-phase register is increased by one. If two NCOs are
cascaded together to obtain 64 bits of frequency resolution the
CARRY OUT of the lower order NCO is connected to the
CARRY IN of the higher order NCO.
5
STEL-1172B
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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the device.
Exposure of the device to these conditions for extended periods may also affect device reliability. All
voltages are referenced to VSS.
Symbol
Parameter
Range
Units
Tstg
StorageTemperature
40 to +125
65 to +150
°C (Plasticpackage)
{
°C (Ceramicpackage)
VDDmax
VI(max)
Ii
Supply voltage on VDD
Input voltage
0.3 to + 7
0.3 to VDD + 0.3
± 10
volts
volts
mA
DC input current
RECOMMENDEDOPERATINGCONDITIONS
Symbol
Parameter
Range Units
VDD
Supply Voltage
+5 ± 5%
Volts (Commercial)
Volts (Military)
{
+5 ± 10%
Ta
Operating Temperature (Ambient)
0 to +70
°C
°C
(Commercial)
(Military)
{
55 to +125
D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = 55° to 125° C, Military)
Symbol
Parameter
Min.
Typ.
Max. Units
Conditions
IDD(Q)
IDD
SupplyCurrent,Quiescent
SupplyCurrent,Operational
High Level Input Voltage
Standard Operating Conditions
Extended Operating Conditions
Low Level Input Voltage
High Level Input Current
Low Level Input Current
1.0 mA
Static,noclock
3.0 mA/MHz
VIH(min)
2.0
volts
volts
Logic'1'
2.25
Logic'1'
VIL(max)
IIH(min)
IIL(max)
VOH(min)
VOL(max)
IOS
0.8 volts
10 µA
Logic'0'
VIN = VDD
15
2.4
45
4.5
0.2
65
130 µA
volts
VIN = VSS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
IO = 4.0 mA
IO = +4.0 mA
VOUT = VDD, VDD = max
VOUT = VSS, VDD = max
0.4 volts
130 mA
130 mA
20
10
45
CIN
COUT
InputCapacitance
OutputCapacitance
2
4
pF
pF
All inputs
All outputs
STEL-1172B
6
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A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
DD= 5.0 V ±10%, VSS = 0 V, Ta = 55° to 125° C, Military)
V
(Commercial)
(Military)
Symbol
tRS
Parameter
Min. Max.
Min. Max. Units Conditions
RESET pulse width
RESET to CLOCK Setup
DATA or ADDR
30
10
5
35
10
6
nsec.
nsec.
nsec.
tSR
tSU
to WRN Setup, and
LDSTB to CLOCK Setup
DATA or ADDR
tHD
5
6
nsec.
to WRN Hold, and
LDSTB to CLOCK Hold
CLOCK high
tCH
tCL
tW
8
8
10
10
25
3
nsec. fCLK = max.
nsec. fCLK = max.
nsec.
CLOCK low
WRN or FRLD pulse width
CLOCK to output delay
SEL A/B to SIN/COS delay
20
tCD
tSD
5
10
13
25
nsec. Load = 15 pF
nsec. Load = 15 pF
20
NCO RESET SEQUENCE
t
t
RS
SR
RESET
CLOCK
35 CLOCK EDGES
1
2
3
4
32 33 34 35 36 37
SYNC
SIN
7-0
00
00
80
80
81
FF
VALID
VALID
H
H
H
H
H
COS
7-0
H
7
STEL-1172B
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NCO FREQUENCY CHANGE
ADDR
1-0
DON'T CARE
DON'T CARE
t
SU
WRN
t
HD
t
WR
DON'T CARE
DON'T CARE
DATA
7-0
35 CLOCK
EDGES
CLOCK
1
2
3
34
35 36
37
t
LS
t
t
CL
CH
LDSTB
SYNC
SELECT A
SELECT B
OLD
FREQUENCY
NEW
t
t
CD
SO
FREQUENCY
PHASE
SIN/COS
SIN
COS
7-0,
7-0
STEL-1172B
8
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TYPICAL APPLICATION
HIGH-SPEED HOPPING 66-74 MHz SYNTHESIZER
8
Data7-0
SINE
8
2
BPF
2-10
MHz
BPF
66-74
MHz
66-74 MHz
STEL-1172B
NCO
ADDR1-0
D/A
LDSTB
RESET
CLK
CLK
64 MHz
OSCILLATOR
CLOCK
If the STEL-1172B is combined with a high-speed 8-bit video DAC, signals with spectral purity of better
than 55 dBc can be generated up to 10 MHz. In this way a signal can be generated in the 66 to 74 MHz
band after filtering and upconversion. Because of the phase continuous frequency switching
characteristics of the STEL-1172B this architecture is suitable for Frequency Hopping Spread Spectrum
applications.
SPECTRAL PURITY
spurious levels which are theoretically about -60 dBc.
The highest output frequency the NCO can generate is
half the clock frequency (fc/2), and the spurious
components at frequencies greater than fc/2 can be
removed by filtering. As the output frequency fo of the
NCO approaches fc/2 the "image" spur at fc fo also
approaches fc/2 from above. If the programmed
output frequency is very close to fc/2 it will be virtually
impossible to remove this "image" spur by filtering.
For this reason, the maximum practical output
frequency of the NCO should be limited to about 40%
of the clock frequency.
In many applications the NCO is used with a digital to
analog converter (DAC) to generate an analog
waveform which approximates an ideal sinewave.
The spectral purity of this synthesized waveform is a
function of many variables including the phase and
amplitude quantization, the ratio of the clock
frequency to output frequency, and the dynamic
characteristics of the DAC.
The sine and cosine signals generated by the
STEL-1172B have eight bits of amplitude resolution
and ten bits of phase resolution which results in
9
STEL-1172B
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The higher the resolution of the NCO outputs the
greater the spectral purity. Each additional bit used in
quantizing the phase and amplitude of the sine func-
tion (assuming equal resolution for each) provides 6
dB improvement in spectral purity. For this reason, 12
bits of phase information are brought to the STEL-
1172B outputs. It is possible to use these signals with
an external sine ROM to generate sine waves which
have spurious levels as low as -72 dBc.
when the output frequency is a significant fraction of
the clock frequency.
A spectral plot of the NCO output after conversion
with a DAC (AD9703) is shown below. In this case the
clock frequency is 50 MHz and the output frequency is
programmed to 5.6789 MHz. The maximum spur level
observed over the entire useful output frequency
range in this case is 55 dBc. Under other conditions
the spurious levels may be greater than this due to
DAC limitations or clock feedthrough problems
relating to grounding on the PC board. At higher
output frequencies the waveform produced by the
DAC will have large output changes from sample to
sample. For this reason the settling time of the DAC
should be short in comparison to the clock period . As
a general rule the DAC used should have the lowest
possible glitch energy as well as the shortest possible
settling time.
In some applications the NCO is used with two DACs
to generate analog sine and cosine signals to drive a
single sideband mixer. If the sine and cosine functions
were ideal a typical single sideband mixer would
provide 20 to 30 dB of LO and image suppression. This
performance can be significantly degraded if an NCO
is used to generate these signals near the maximum
NCO frequency. It is recommended that care be taken
when designing the STEL-1172B into such systems
TYPICAL SPECTRUM
Output frequency:
Clock frequency:
Frequency Span:
Reference Level:
5.6789 MHz
50.0 MHz
0 to 20 MHz
0 dBm
Resolution Bandwidth: 1 kHz
Video Bandwidth:
Scale:
3 kHz
Log, 10 dB/div
STEL-1172B
1 0
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