STEL-1173/CM [ETC]
Numeric-Controlled Oscillator ; 数字控制振荡器\n
| 型号： | STEL-1173/CM |
| 厂家： | 
ETC |
| 描述： | Numeric-Controlled Oscillator
|
| 文件： | 总11页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STEL-1173
Data Sheet
STEL-1173
(50 MHz)
48-Bit Resolution
CMOS Numerically
Controlled Oscillator
R
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FEATURES
FUNCTIONAL DESCRIPTION
The STEL-1173 Numerically Controlled Oscillator
(NCO) uses digital techniques to provide a cost-
effective solution for low noise signal sources. The
NCO device combines low power 1.5µ CMOS
technologywithauniquearchitecturaldesignresulting
in a power efficient, high-speed sinusoidal waveform
generator able to achieve fine tuning resolution and
exceptional spectral purity with clock frequencies up to
50 MHz.
■ 48-BIT FREQUENCY RESOLUTION
■ 50 MHz CLOCK FREQUENCY (0 TO 70°C)
■ SINE OR COSINE OUTPUT AVAILABLE
■ 12-BIT AMPLITUDE RESOLUTION AND
13-BIT PHASE RESOLUTION GIVES HIGH
SPECTRAL PURITY, ALL SPURS <–75 dBc
(AT DIGITAL OUTPUT)
■ MICROPROCESSOR BUS COMPATIBLE
CONTROL INPUTS
The NCO generates digital sine or cosine functions of
very precise frequency to be used directly in digital
signal processing applications or, in conjunction with a
D/A converter, in analog frequency generation
applications. The NCO is designed to interface with
and be controlled from an 8-bit microprocessor bus.
■ CASCADABLE ACCUMULATOR FOR
HIGHER FREQUENCY RESOLUTION
■ 2's COMPLEMENT OR OFFSET BINARY
OUTPUT CODES
■ LOW POWER CMOS
■ MILITARY AND COMMERCIAL
TEMPERATURE RANGES AVAILABLE
The NCO maintains a record of phase which is accurate
to 48 bits. At each clock cycle, the number stored in the
48 bit ∆-Phase register is added to the previous value of
the phase accumulator. The number in the phase
accumulator represents the current phase of the
synthesized sine and cosine functions. The number in
the ∆-Phase register represents the change of phase for
each cycle of the clock. This number is directly related
to the output frequency by the following:
APPLICATIONS
■ FREQUENCY SYNTHESIZERS
■ SINGLE SIDEBAND CONVERTERS
■ BASEBAND RECEIVERS
■ DIGITAL SIGNAL PROCESSORS
■ HIGH SPEED HOPPED FREQUENCY
SOURCES
fc x ∆-Phase
fo=
248
where: fo is the frequency of the output signal
and: fc is the clock frequency.
BLOCK DIAGRAM
LDSTB
48
8
DATA 7-0
WRN
48–BIT
48
48
13
12
6
SINE
LOOKUP
TABLE
ADDR.
SELECT
LOGIC
–PHASE
BUFFER
REGISTERS
–PHASE
REGISTER
PHASE
ACCUMU-
LATOR
OUT 11-0
3
CSN
ADDR
2-0
RESET
CLOCK
STEL-1173
2
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PIN CONFIGURATION -- STEL-1173/CL
VSS
CARRY IN
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 4
DATA 6
DATA 7
VDD
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
0.15" typ.
0.2"
max.
ADDR 2
ADDR 1
ADDR 0
CLOCK
I.C.
Seating
plane
0.13" typ.
0.1" ± 0.01"
Note: tolerance not cumulative
N.C.
N.C.
I.C.
9
0.55"
typ.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SYNC
VSS
I.C.
WRN
I.C.
I.C.
I.C.
OUT 11
OUT 10
OUT 9
OUT 8
OUT 7
OUT 6
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
OUT 0
N.C.
2.46 max.
0.6"
(at seating plane)
SIN
48
Package: pin plastic
DIP or ceramic DIP
Thermal coefficient, θjc = 15°/W
Note: pin spacing for Ceramic
DIP is the same
TWOSCOMP
LDSTB
CARRY OUT
CSN
N.C.
I.C.
RESET
VDD
PIN CONFIGURATION -- STEL-1173/CM
Package: 44-pin PLCC
Thermal coefficient, θja = 60° C/W
0.18"
max.
4 4 4 4 4
6 5 4 3 2 1 4 3 2 1 0
7
8
39
38
37
36
35
34
33
32
31
30
29
0.017"
± 0.004" (2)
9
10
11
12
13
14
15
16
17
0.690"
± .005"
0.05"
nom. (1)
0.02"
min.
1 1 2 2 2 2 2 2 2 2 2
8 9 0 1 2 3 4 5 6 7 8
0.653"
± 0.010"
PIN CONNECTIONS
1
2
3
4
5
6
7
8
VSS
9
DATA6
18 LDSTB
19 CARRY OUT
20 CSN
21 I.C.
22 RESET
23 VDD
24 OUT0 (LSB)
25 OUT1
26 OUT2
27 OUT3
28 OUT4
29 OUT5
30 OUT6
31 OUT7
32 OUT8
33 OUT9
34 OUT10
35 OUT11 (MSB)
36 VSS
37 SYNC
38 I.C.
CARRY IN
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
10 DATA7
11 I.C.
12 WRN
13 I.C.
14 I.C.
15 I.C.
39 I.C.
40 CLOCK
41 ADDR0
42 ADDR1
43 ADDR2
44 VDD
16 SINE
17 TWOSCOMP
Notes: 1. Tolerances on pin spacing are not cumulative.
2. I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias.
3. N.C. denotes No Connection. These pins may be used for vias.
3
STEL-1173
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FUNCTION BLOCK DESCRIPTION
CIRCUIT DESCRIPTION
ADDRESS SELECT LOGIC BLOCK
The sine and cosine functions are generated from the
13 most significant bits of the phase accumulator. The
frequency of the NCO is determined by the number
stored in the ∆-Phase register which may be
programmed by an eight-bit microprocessor.
This block controls the writing of data into the device
via the DATA7-0 inputs. The data is written into the
device on the rising edge of the WRN input, and the
register into which the data is written is selected by the
ADDR2-0 inputs. The writing of data is also controlled
with the CSN input; this input must be low to enable
writing.
The frequency programming capability of the NCO is
analogous to sampling a sine wave where the
sampling function is the clock. If the output frequency
is very low with respect to the clock (< fc /8096), then
the NCO output will sequence through each of the
8096 states of the sine function. As the output
frequencyisincreasedwithrespecttotheclockthesine
function will appear to be more discontinuous since
there will be fewer samples in each cycle. At the
Nyquist limit, when the output frequency is exactly
half the clock, the output waveform reduces to a
square wave. The practical upper limit of the NCO
output frequency is about 40% of the clock frequency
because spurious components created by sampling,
which are at a frequency greater than half the clock
frequency, become difficult to remove by filtering.
BUFFER REGISTER BLOCK
TheBufferRegisterisusedtotemporarilystorethe ∆-
Phasedatawrittenintothedevice. Thisallowsthedata
to be written asynchronously as six bytes per 48-bit
∆-Phase word. The data is transferred from this
registerintothe∆-PhaseRegisterafterafallingedgeon
the LDSTB input.
∆-PHASE REGISTER BLOCK
This block controls the updating of the ∆-Phase word
used in the Accumulator. The frequency data from the
Buffer Register Block is loaded into this block after a
falling edge on the LDSTB input. The SYNC output,
which indicates the instant of frequency change at the
output at the end of the pipeline delay, is generated in
this block.
The phase noise of the NCO output signal may be
determined by knowing the phase noise of the clock
signal input, and the ratio of the output frequency to
theclockfrequency. Thisratiosquaredtimesthephase
noise power of the clock specified in a given
bandwidth is the phase noise power that may be
expectedinthatsamebandwidthrelativetotheoutput
frequency.
PHASE ACCUMULATOR BLOCK
This block forms the core of the NCO function. It is a
high-speed, pipelined, 48-bit parallel accumulator,
generating a new sum in every clock cycle. A carry
input (CARRY IN) allows the resolution of the
accumulator to be expanded by means of an auxiliary
NCO or phase accumulator. The overflow signal is
discarded (and is available at the CARRY OUT pin),
since the required output is the modulo (248) sum only.
This represents the modulo (2π) phase angle.
The NCO achieves its high operating frequency by
making extensive use of pipelining in its architecture.
The pipeline delays within the NCO represent 20 clock
cycles. This effectively limits the minimum possible
frequency switching period of the NCO. After new
frequency data is entered, the load command is given.
After the 20 cycle pipeline delay, the output will
instantaneously switch frequency while maintaining
phase coherence. After this, the next new frequency
may be entered. If a 50 MHz clock were utilized, the
NCO could be continuously switched between
programmed frequencies with a minimum practical
average switching time of about 0.4 µsec.
SINE LOOKUP TABLE BLOCK
This block is the sine memory. The 13 most significant
bits from the Phase Accumulator are used to address
this memory to generate the 12-bit OUT11-0 outputs.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low.
When RESET goes low, all registers including the 48-
bit input buffer are cleared within 30 nsecs. The data
on the OUT11-0 bus will then be invalid for 6 clock
cycles, and thereafter will remain at the value
corresponding to zero phase, i.e., 2049 (801H), until a
new frequency is loaded into the ∆-Phase register with
a LDSTB command after the RESET returns to a logic
one.
STEL-1173
4
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CLOCK
CARRY IN
AllsynchronousfunctionsperformedwithintheNCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be nominally a square
wave at a maximum frequency of 50 MHz. A non-
repetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 8 nanoseconds.
At each positive transition of the CLOCK signal, the
number stored in the ∆-Phase register is added to the
contents of the phase accumulator and the result is
placed in the phase accumulator.
Normal operation of the NCO requires that CARRY
IN be set at a logic 0. When CARRY IN is a logic 1, the
effective value of the ∆-Phase register is increased by
one. Two NCOs can be cascaded together to obtain 96
bits of frequency resolution by using the CARRY OUT
of the lower order NCO and the CARRY IN of the
higher order NCO.
TWOSCOMP
When the TWOSCOMP input is set high, the data
appearing on the OUT11-0 bus is presented in two's
complement code, and when it is set low, the data is
presented in offset binary code. The limits of the data
values in both codes is shown below:
WRN
On the rising edge of the WRN input, the information
onthe8-bitdatabusistransferredtothebufferregister
selected by the ADDR2-0 bus.
Code → Offset binary
2's Complement
Minimum value
Maximum value +4095 (FFFH)
Mean value
+1 (001H)
– 2047 (801H)
+2047 (7FFH)
0 (000H)
CSN
The CSN (Chip Select) input is active low and can be
used to control the writing of data into the chip. When
this input is high all data writing via the DATA7-0 bus
is inhibited.
+2048 (800H)
Both number formats produce sine or cosine waves
which are symmetrical about the phase quadrant axis
and the mean-value magnitude axis.
ADDR through ADDR0
The thr2ee address lines ADDR2-0 control the use of the
DATA7-0 bus for writing frequency data to the ∆-Phase
buffer registers as shown in the table below:
SINE
When the SINE input signal is set to a logic low level,
the output signal appearing on the OUT11-0 bus is the
cosine of the 48-bit accumulator’s 13 most significant
bits (bits 47-35, with 47 being the MSB). Normally set
high, thissignalallowstheNCOtogenerateeithersine
or cosine signals. By using two devices, one set in the
sine mode and the other set in the cosine mode,
quadrature outputs may be obtained. The quadrature
phase relationship of the two outputs will be
maintained at all times provided the two devices are
reset simultaneously and operate from a common
clock signal.
ADDR2 ADDR1 ADDR0 ∆-Phase Register Field
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Bits0 (LSB) –7
Bits 8–15
Bits 16–23
Bits 24–31
Bits 32–39
Bits 40–47 (MSB)
To write to all 48 bits of the phase write registers, the
DATA7-0 bus must be used 6 times. Note that it is not
necessarytoreloadunchangedbytes, andthatthebyte
loading sequence may be random.
AhighlevelontheSINE inputsetstheoutputtobethe
sine of the 48-bit accumulator’s 13 most significant
bits. The value of the output for a given phase value
follows the relationship:
DATA7 through DATA0
The eight bit DATA7-0 bus is used to program the 48-
bit ∆-Phase register. DATA0 is the least significant bit
of the bus.
2’s comp = 2047 x sin (360 x phase)
offset bin = 2047 x sin (360 x phase) +2048
The result is accurate to within 1 LSB.
LDSTB
When this input is set low the output will be the cosine
of the 48-bit accumulator’s 13 most significant bits.
Thevalueoftheoutputforagivenphasevaluefollows
the relationship:
On the rising edge of the clock following the falling
edge of the LDSTB input, the information in the 48-bit
buffer register is transferred to the ∆-Phase register.
The frequency of the NCO output will change 20 clock
cycles after the LDSTB command due to pipelining
delays.
2’s comp = 2047 x cos (360 x phase)
offset bin = 2047 x cos (360 x phase) +2048
again, accurate to within 1 LSB.
5
STEL-1173
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OUTPUT SIGNALS
OUT11-0
CARRY OUT
The signal appearing on the OUT11-0 bus is derived
from the 13 most significant bits of the phase
accumulator. The 12-bit sine or cosine function is
presented in offset binary or two's complement
format, depending on the status of the TWOSCOMP
input. When the phase accumulator is zero, e.g., after
a reset, the decimal value of the output is 2049 in offset
binary and 1 in two's complement. The nominal phase
(in degrees) of the sine wave output may be
determined at any point by multiplying the decimal
equivalent of the 13 most significant bits of the phase
accumulator by (360/8192) and then adding
(360/16384). OUT11 is the MSB, and OUT0 is the LSB.
Each time the contents of the phase accumulator
exceeds the maximum value that can be represented
by a 48 bit number the CARRY OUT signal goes high
for one clock cycle.
SYNC
The normally high SYNC output goes low for one
clockcycle,20clockcyclesafteraLDSTBcommand,to
indicate the end of the pipeline delay and the start of
the new steady state condition.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the device.
Exposure of the device to these conditions for extended periods may also affect device reliability. All
voltages are referenced to VSS.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
Supply voltage on VDD
Input voltage
–40 to +125
–0.3 to + 7
–0.3 to VDD + 0.3
± 10
°C (Plastic package)
VDDmax
VI(max)
Ii
volts
volts
mA
DC input current
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Range Units
+5 ± 5%
Supply Voltage
Volts (Commercial)
Ta
Operating Temperature (Ambient)
0 to +70
°C
(Commercial)
STEL-1173
6
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D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
Symbol
Parameter
Min. Typ.
Max. Units
Conditions
IDD(Q)
IDD
Supply Current, Quiescent
Supply Current, Operational
High Level Input Voltage
Standard Operating Conditions
Extended Operating Conditions
Low Level Input Voltage
High Level Input Current
High Level Input Current
Low Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
1.0 mA
Static, no clock
3.0 mA/MHz
VIH(min)
2.0
volts
volts
Logic '1'
2.25
Logic '1'
VIL(max)
IIH(min)
IIH(min)
IIL(max)
IIL(max)
VOH(min)
VOL(max)
IOS
0.8 volts
110 µA
10 µA
Logic '0'
10
35
CIN and CSEL, VIN = VDD
All other inputs, VIN = VDD
CIN and CSEL, VIN = VSS
All other inputs, VIN = VSS
IO = –4.0 mA
–10 µA
–130 µA
volts
–15
2.4
–45
4.5
0.2
65
0.4 volts
130 mA
–130 mA
IO = +4.0 mA
20
VOUT = VDD, VDD = max
VOUT = VSS, VDD = max
–10
–45
CIN
COUT
Input Capacitance
Output Capacitance
2
4
pF
pF
All inputs
All outputs
A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
STEL-1173
(Commercial)
Symbol
tRS
Parameter
Min.
30
Max
Units
nsec.
nsec.
nsec.
Conditions
RESET pulse width
RESET to CLOCK Setup
DATA, ADDR or CSEL
to WRN Setup, and
tSR
10
tSU
18
LDSTB to CLOCK Setup
tHD DATA, ADDR or CSEL
to WRN Hold, and
12
nsec.
LDSTB to CLOCK Hold
tCH
tCL
tW
CLOCK high
8
8
nsec.
nsec.
nsec.
nsec.
fCLK = max.
fCLK = max.
CLOCK low
WRN or FRLD pulse width
CLOCK to output delay
20
5
tCD
10
Load = 15 pF
7
STEL-1173
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NCO RESET SEQUENCE
tRS
RESET
CLOCK
5 CLOCK
EDGES
1
2
3
4
5
OUT 11-0
NOT VALID
801H
NCO FREQUENCY CHANGE
CSN
ADDR 2-0
WRN
DON'T CARE
DON'T CARE
tSU
tHD
tWR
DATA7-0
DON'T CARE
DON'T CARE
20 CLOCK
EDGES
CLOCK
LDSTB
SYNC
tSU
tCH
tCL
tLS
tCD
OLD FREQUENCY NEW FREQUENCY
OUT11-0
STEL-1173
8
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TYPICAL APPLICATION
HIGH PURITY, HIGH RESOLUTION SYNTHESIZER
8
DATA
3
ADDR 0-2
STEL-
SINE
BPF
6-14
MHz
BPF
66-74
MHz
66-74 MHz
D/A
1173
NCO
WR
LDSTB
CLK
12
CLK
RESET
60 MHz
OSCILLATOR
50 MHz CLOCK
If the STEL-1173 is combined with a suitable high-speed DAC, signals with spectral purity of better than
–65 dBc can be generated up to 10 MHz. In this way a signal can be generated in the 70 MHz band for
use in a baseband downconverter tracking oscillator. The very high frequency resolution of the STEL-
1173 allows the incoming signal to be tracked very closely and with minimal "hunting", resulting in low
phase noise. The phase continuous frequency switching characteristics of the STEL-1173 also make it
suitable for use in Frequency Hopping Spread Spectrum applications.
SPECTRAL PURITY
In many applications the NCO is used with a Digital to
Analog converter (DAC) to generate an analog
waveform which approximates an ideal sinewave.
The spectral purity of this synthesized waveform is a
function of many variables including the phase and
amplitude quantization, the ratio of the clock
frequency to output frequency, and the dynamic
characteristics of the DAC.
about –75 dBc. The highest output frequency the NCO
can generate is half the clock frequency (fc /2), and the
spurious components at frequencies greater than fc/2
can be removed by filtering. As the output frequency
fo of the NCO approaches fc /2, the "image" spur at
fc–fo (createdbythesamplingprocess)alsoapproaches
fc/2 from above. If the programmed output frequency
is very close to fc/2 it will be virtually impossible to
remove this image spur by filtering. For this reason,
the maximum practical output frequency of the NCO
should be limited to about 40% of the clock frequency.
The signals generated by the STEL-1173 have 12 bits of
amplitude resolution and 13 bits of phase resolution
whichresultsinspuriouslevelswhicharetheoretically
9
STEL-1173
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A spectral plot of the NCO output after conversion
with a DAC (Sony CX20202A-1) is shown below. In
this case, the clock frequency is 50 MHz and the output
frequency is programmed to 6.789 MHz. This 10-bit
DAC gives better performance than any of the
currently available 12-bit DACs at clock frequencies
higher than 10 or 20 MHz. The maximum non-
harmonic spur level observed over the output
frequency range shown in this case is –74 dBc. The
spur levels are limited by the dynamic linearity of the
DAC. It is important to remember that when the
output frequency exceeds 25% of the clock frequency,
the second harmonic frequency will be higher than the
Nyquist frequency, 50% of the clock frequency. When
this happens, the image of the harmonic at the
frequency fc– 2fo, which is not harmonically related to
the output signal, will become intrusive since its
frequency falls as the output frequency rises,
eventually crossing the fundamental output when its
frequency crosses through fc/3. It would be necessary
to select a DAC with better dynamic linearity to
improve the harmonic spur levels. (The dynamic
linearity of a DAC is a function of both its static
linearity and its dynamic characteristics, such as
settling time and slew rates.) At higher output
frequencies the waveform produced by the DAC will
have large output changes from sample to sample. For
this reason, the settling time of the DAC should be
short in comparison to the clock period. As a general
rule, the DAC used should have the lowest possible
glitch energy as well as the shortest possible settling
time.
TYPICAL SPECTRUM
Center Frequency:
Frequency Span:
Reference Level:
6.7 MHz
10.0 MHz
–5 dBm
Resolution Bandwidth: 1 KHz
Video Bandwidth:
Scale:
3 kHz
Log, 10 dB/div
6.789 MHz
50 MHz
Output frequency:
Clock frequency:
STEL-1173
10
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