STEL-1174/CM [INTEL]
Numeric Controlled Oscillator, CMOS, PQCC44,;
| 型号： | STEL-1174/CM |
| 厂家： | 
INTEL |
| 描述： | Numeric Controlled Oscillator, CMOS, PQCC44, 外围集成电路 |
| 文件： | 总9页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STEL-1174
Data Sheet
STEL-1174
50 MHz, 16-Bit Resolution
CMOS Numerically
Controlled Oscillator
R
FUNCTIONAL DESCRIPTION
FEATURES
The STEL-1174 Numerically Controlled Oscillator
(NCO) uses digital techniques to provide a cost-
effective solution for low noise signal sources. The
NCO device combines low power 1.5µ CMOS
technology with a unique architectural design
resulting in a power efficient, high-speed sinusoidal
waveform generator able to achieve fine tuning
resolution and exceptional spectral purity with clock
frequencies up to 50 MHz.
■ 16-BIT FREQUENCY RESOLUTION
■ 50 MHz CLOCK FREQUENCY (0 TO 70°C)
■ SINE OR COSINE OUTPUT AVAILABLE
■ 12-BIT AMPLITUDE RESOLUTION AND
13-BIT PHASE RESOLUTION GIVES
HIGH SPECTRAL PURITY, ALL SPURS
<–75 dBc (AT DIGITAL OUTPUT)
■ MICROPROCESSOR BUS COMPATIBLE
The NCO generates digital sine or cosine functions of
very precise frequency to be used directly in digital
signal processing applications or, in conjunction with
a D/A converter, in analog frequency generation
applications. The NCO is designed to interface with
and be controlled from an 8-bit microprocessor bus.
CONTROL INPUTS
■ CASCADABLE ACCUMULATOR FOR
HIGHER FREQUENCY RESOLUTION
■ 2's COMPLEMENT OR OFFSET BINARY
OUTPUT CODES
The NCO maintains a record of phase which is
accurate to 16 bits. At each clock cycle, the number
stored in the 16 bit ∆-Phase register is added to the
previous value of the phase accumulator. The number
in the phase accumulator represents the current phase
of the synthesized sine and cosine functions. The
number in the ∆-Phase register represents the change
of phase for each cycle of the clock. This number is
directly related to the output frequency by the
following:
■ LOW POWER CMOS
■ MILITARY AND COMMERCIAL
TEMPERATURE RANGES AVAILABLE
APPLICATIONS
■ FREQUENCY SYNTHESIZERS
■ SINGLE SIDEBAND CONVERTERS
■ BASEBAND RECEIVERS
fc x ∆-Phase
fo=
■ DIGITAL SIGNAL PROCESSORS
216
■ HIGH SPEED HOPPED FREQUENCY
where: fo is the frequency of the output signal
and: fc is the clock frequency.
SOURCES
BLOCK DIAGRAM
LDSTB
16
8
DATA 7-0
WRN
48–BIT
16
16
13
12
6
SINE
LOOKUP
TABLE
ADDR.
SELECT
LOGIC
–PHASE
BUFFER
REGISTERS
–PHASE
REGISTER
PHASE
ACCUMU-
LATOR
OUT 11-0
CSN
ADDR
RESET
CLOCK
STEL-1174
2
CIRCUIT DESCRIPTION
The sine and cosine functions are generated from the
13 most significant bits of the phase accumulator. The
frequency of the NCO is determined by the number
stored in the ∆-Phase register which may be
programmed by an eight-bit microprocessor.
The phase noise of the NCO output signal may be
determined by knowing the phase noise of the clock
signal input, and the ratio of the output frequency to
the clock frequency. This ratio squared times the phase
noise power of the clock specified in a given
bandwidth is the phase noise power that may be
expected in that same bandwidth relative to the
output frequency.
The frequency programming capability of the NCO is
analogous to sampling a sine wave where the
sampling function is the clock. If the output frequency
is very low with respect to the clock (< fc /8096), then
the NCO output will sequence through each of the
8096 states of the sine function. As the output
frequency is increased with respect to the clock the
sine function will appear to be more discontinuous
since there will be fewer samples in each cycle. At the
Nyquist limit, when the output frequency is exactly
half the clock, the output waveform reduces to a
square wave. The practical upper limit of the NCO
output frequency is about 40% of the clock frequency
because spurious components created by sampling,
which are at a frequency greater than half the clock
frequency, become difficult to remove by filtering.
The NCO achieves its high operating frequency by
making extensive use of pipelining in its architecture.
The pipeline delays within the NCO represent 12 clock
cycles. This effectively limits the minimum possible
frequency switching period of the NCO. After new
frequency data is entered, the load command is given.
After the 12 cycle pipeline delay, the output will
instantaneously switch frequency while maintaining
phase coherence. After this, the next new frequency
may be entered. If a 50 MHz clock were utilized, the
NCO could be continuously switched between
programmed frequencies with a minimum practical
average switching time of about 0.24 µsec.
PIN CONFIGURATION
Package: 44 pin PLCC
Thermal coefficient, θja = 40°/W
Package: 44 pin CLDCC
Thermal coefficient, θja = 50°/W
0.14"
max.
0.18"
max.
4 4 4 4 4
6 5 4 3 2 1 4 3 2 1 0
4 4 4 4 4
6 5 4 3 2 1 4 3 2 1 0
7
8
39
38
37
36
35
34
33
32
31
30
29
7
8
39
38
37
36
35
34
33
32
31
30
29
0.017"
± 0.004" (2)
0.016"
± 0.004" (2)
9
9
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
0.690"
± .005"
0.690"
± .010"
Top View
Top View
0.05"
nom. (1)
0.05"
± 0.005 (1)
0.02"
min.
0.045"
nom.
1 1 2 2 2 2 2 2 2 2 2
8 9 0 1 2 3 4 5 6 7 8
1 1 2 2 2 2 2 2 2 2 2
8 9 0 1 2 3 4 5 6 7 8
0.653"
± 0.010"
0.653"
± 0.004"
Notes: (1) Tolerances on pin spacing are not cumulative.
(2) Dimensions apply at seating plane.
(3) PLCC and CLDCC packages have different corners and may not fit into sockets designed
for the other type. Universal sockets are available without alignment locators.
PIN CONNECTIONS
10 DATA7
11 I.C.
12 WRN
13 VDD
14 I.C.
15 I.C.
16 SINE
17 TWOSCOMP
18 LDSTB
19 I.C.
20 CSN
21 VSS
22 RESET
23 VDD
24 OUT0 (LSB)
25 OUT1
26 OUT2
27 OUT3
37 I.C.
38 I.C.
39 I.C.
40 CLOCK
41 ADDR
42 I.C.
43 VDD
44 VDD
1
2
3
4
5
6
7
8
9
VSS
VSS
28 OUT4
29 OUT5
30 OUT6
31 OUT7
32 OUT8
33 OUT9
34 OUT10
35 OUT11 (MSB)
36 VSS
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
Note: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias.
3
STEL-1174
FUNCTION BLOCK DESCRIPTION
ADDRESS SELECT LOGIC BLOCK
wave at a maximum frequency of 50 MHz. A non-
repetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 8 nanoseconds.
At each positive transition of the CLOCK signal, the
number stored in the ∆-Phase register is added to the
contents of the phase accumulator and the result is
placed in the phase accumulator.
This block controls the writing of data into the device
via the DATA7-0 inputs. The data is written into the
device on the rising edge of the WRN input, and the
register into which the data is written is selected by
the ADDR input. The writing of data is also controlled
with the CSN input; this input must be low to enable
writing.
BUFFER REGISTER BLOCK
WRN
The Buffer Register is used to temporarily store the ∆-
Phase data written into the device. This allows the
data to be written asynchronously as two bytes per
16-bit ∆-Phase word. The data is transferred from this
register into the ∆-Phase Register after a falling edge
on the LDSTB input.
On the rising edge of the WRN input, the information
on the 8-bit data bus is transferred to the buffer
register selected by the ADDR2-0 bus.
CSN
The CSN (Chip Select) input is active low and can be
used to control the writing of data into the chip. When
this input is high all data writing via the DATA7-0 bus
is inhibited.
∆-PHASE REGISTER BLOCK
This block controls the updating of the ∆-Phase word
used in the Accumulator. The frequency data from the
Buffer Register Block is loaded into this block after a
falling edge on the LDSTB input.
ADDR
The address line ADDR controls the use of the
DATA7-0 bus for writing frequency data to the ∆-
Phase buffer registers as shown in the table below:
PHASE ACCUMULATOR BLOCK
This block forms the core of the NCO function. It is a
high-speed, pipelined, 16-bit parallel accumulator,
generating a new sum in every clock cycle. The
overflow signal is discarded), since the required
output is the modulo (216) sum only. This represents
the modulo (2π) phase angle.
ADDR
∆-Phase Register Field
0
1
Bits0 (LSB) –7
Bits 8–15 (MSB)
To write to all 16 bits of the phase write registers, the
DATA7-0 bus must be used twice. Note that it is not
necessary to reload unchanged bytes, and that the byte
loading sequence may be random.
SINE LOOKUP TABLE BLOCK
This block is the sine memory. The 13 most significant
bits from the Phase Accumulator are used to address
this memory to generate the 12-bit OUT11-0 outputs.
DATA7 through DATA0
The eight bit DATA7-0 bus is used to program the 16-
bit ∆-Phase register. DATA0 is the least significant bit
of the bus.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low.
When RESET goes low, all registers including the 16-
bit input buffer are cleared within 30 nsecs. The data
on the OUT11-0 bus will then be invalid for 6 clock
cycles, and thereafter will remain at the value
corresponding to zero phase, i.e., 2049 (801H), until a
new frequency is loaded into the ∆-Phase register with
a LDSTB command after the RESET returns to a logic
one.
LDSTB
On the rising edge of the clock following the falling
edge of the LDSTB input, the information in the 16-
bit buffer register is transferred to the ∆-Phase register.
The frequency of the NCO output will change 12 clock
cycles after the LDSTB command due to pipelining
delays.
TWOSCOMP
When the TWOSCOMP input is set high, the data
appearing on the OUT11-0 bus is presented in two's
complement code, and when it is set low, the data is
presented in offset binary code. The limits of the data
values in both codes is shown in the table:
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be nominally a square
STEL-1174
4
Code → Offset binary
2's Complement
The result is accurate to within 1 LSB.
When this input is set low the output will be the cosine
of the 16-bit accumulator’s 13 most significant bits.
The value of the output for a given phase value follows
the relationship:
Minimum value
Maximum value +4095 (FFFH)
Mean value
+1 (001H)
– 2047 (801H)
+2047 (7FFH)
0 (000H)
+2048 (800H)
Both number formats produce sine or cosine waves
which are symmetrical about the phase quadrant axis
and the mean-value magnitude axis.
2’s comp = 2047 x cos (360 x phase)
offset bin = 2047 x cos (360 x phase) +2048
again, accurate to within 1 LSB.
SINE
When the SINE input signal is set to a logic low level,
the output signal appearing on the OUT11-0 bus is the
cosine of the 16-bit accumulator’s 13 most significant
bits (bits 47-35, with 47 being the MSB). Normally set
high, this signal allows the NCO to generate either
sine or cosine signals. By using two devices, one set in
the sine mode and the other set in the cosine mode,
quadrature outputs may be obtained. The quadrature
phase relationship of the two outputs will be
maintained at all times provided the two devices are
reset simultaneously and operate from a common
clock signal.
OUTPUT SIGNALS
OUT11-0
The signal appearing on the OUT11-0 bus is derived
from the 13 most significant bits of the phase
accumulator. The 12-bit sine or cosine function is
presented in offset binary or two's complement
format, depending on the status of the TWOSCOMP
input. When the phase accumulator is zero, e.g., after
a reset, the decimal value of the output is 2049 in offset
binary and 1 in two's complement. The nominal phase
(in degrees) of the sine wave output may be
determined at any point by multiplying the decimal
equivalent of the 13 most significant bits of the phase
accumulator by (360/8192) and then adding
(360/16384). OUT11 is the MSB, and OUT0 is the LSB.
A high level on the SINE input sets the output to be
the sine of the 16-bit accumulator’s 13 most significant
bits. The value of the output for a given phase value
follows the relationship:
2’s comp = 2047 x sin (360 x phase)
offset bin = 2047 x sin (360 x phase) +2048
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the device.
Exposure of the device to these conditions for extended periods may also affect device reliability.
All voltages are referenced to VSS.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
–40 to +125
–65 to +150
–0.3 to + 7
–0.3 to VDD + 0.3
± 10
°C (Plastic package)
°C (Ceramic package)
VDDmax
VI(max)
Ii
Supply voltage on VDD
Input voltage
volts
volts
mA
DC input current
5
STEL-1174
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Range Units
+5 ± 5%
VDD
Supply Voltage
Volts (Commercial)
Volts (Military)
+5 ± 10%
Ta
Operating Temperature (Ambient)
0 to +70
°C
°C
(Commercial)
(Military)
–55 to +125
D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
DD= 5.0 V ±10%, VSS = 0 V, Ta = –55° to 125° C, Military)
V
Symbol
Parameter
Min. Typ.
Max. Units
Conditions
IDD(Q)
IDD
Supply Current, Quiescent
Supply Current, Operational
High Level Input Voltage
Standard Operating Conditions
Extended Operating Conditions
Low Level Input Voltage
High Level Input Current
High Level Input Current
Low Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
1.0 mA
Static, no clock
3.0 mA/MHz
VIH(min)
2.0
volts
volts
Logic '1'
2.25
Logic '1'
VIL(max)
IIH(min)
IIH(min)
IIL(max)
IIL(max)
VOH(min)
VOL(max)
IOS
0.8 volts
110 µA
10 µA
Logic '0'
10
35
CIN and CSEL, VIN = VDD
All other inputs, VIN = VDD
CIN and CSEL, VIN = VSS
All other inputs, VIN = VSS
IO = –4.0 mA
–10 µA
–130 µA
volts
–15
2.4
–45
4.5
0.2
65
0.4 volts
130 mA
–130 mA
IO = +4.0 mA
20
VOUT = VDD, VDD = max
VOUT = VSS, VDD = max
–10
–45
CIN
COUT
Input Capacitance
Output Capacitance
2
4
pF
pF
All inputs
All outputs
NCO RESET SEQUENCE
tRS
RESET
CLOCK
5 CLOCK
EDGES
1
2
3
4
5
OUT 11-0
NOT VALID
801H
STEL-1174
6
A.C. CHARACTERISTICS (Operating Conditions:VDD= 5.0 V ± 5%, VSS=0 V, Ta= 0° to 70° C (Commercial)
VDD= 5.0 V ± 10%, VSS=0 V, Ta=–55° to 125° C (Military)
(Commercial)
(Military)
Symbol
Parameter
Min. Max. Min. Max. Units Conditions
tRS
tSR
tSU
RESET pulse width
RESET to CLOCK Setup
DATA, ADDR or CSEL
to WRN Setup, and
LDSTB to CLOCK Setup
DATA, ADDR or CSEL
to WRN Hold, and
LDSTB to CLOCK Hold
CLOCK high
30
10
18
35
10
25
nsec.
nsec.
nsec.
tHD
12
15
nsec.
tCH
tCL
tW
8
8
10
10
25
3
nsec.
nsec.
nsec.
nsec.
fCLK = max.
fCLK = max.
CLOCK low
WRN or FRLD pulse width 20
CLOCK to output delay
tCD
5
10
13
Load = 15 pF
NCO FREQUENCY CHANGE
CSN
ADDR
WRN
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
tSU
tHD
tWR
DATA 7-0
12 CLOCK
EDGES
CLOCK
LDSTB
SYNC
tSU
tCH
tCL
tLS
tCD
OLD FREQUENCY
NEW FREQUENCY
OUT 11-0
7
STEL-1174
SPECTRAL PURITY
In many applications the NCO is used with a D to A
converter (DAC to generate an analog signal. The
spectral purity of this signal is a function of many
variables including the phase and amplitude
quantization, the ratio of the clock frequency to output
frequency, and the dynamic characteristics of the
DAC. The signals generated by the STEL-1174 have 12
bits of amplitude resolution and 13 bits of phase
resolution which results in spurious levels which are
theoretically about –75 dBc. The highest output
frequency the NCO can generate is half the clock
frequency (fc /2), and the spurious components at
frequencies greater than fc/2 can be removed by
filtering. As the output frequency fo of the NCO
approaches fc /2, the "image" spur at fc–fo (created by
the sampling process) also approaches fc/2 from
above. If the programmed output frequency is very
close to fc/2 it will be virtually impossible to remove
this image spur by filtering. For this reason, the
maximum practical output frequency of the NCO
should be limited to about 40% of the clock frequency.
frequency is programmed to 6.789 MHz. This 10-bit
DAC gives better performance than any of the
currently available 12-bit DACs at clock frequencies
higher than 20-25 MHz. The spur levels are limited by
the dynamic linearity of the DAC. It is important to
remember that when the output frequency exceeds
25% of the clock frequency, the second harmonic
frequency will be higher than the Nyquist frequency,
50% of the clock frequency. When this happens, the
image of the harmonic at the frequency fc– 2fo, which
is not harmonically related to the output signal, will
become intrusive since its frequency falls as the output
frequency rises, eventually crossing the fundamental
output when its frequency crosses through fc/3. A
DAC with better dynamic linearity would be needed
to improve the spur levels. (The dynamic linearity of a
DAC is a function of both its static linearity and its
dynamic characteristics, such as settling time and slew
rates.) At higher output frequencies the waveform
produced by the DAC will have larger steps from
sample to sample and the DAC performance will
degrade. As a general rule, the DAC used should have
the lowest possible glitch energy as well as the shortest
possible settling time.
A spectral plot of the NCO output after conversion
with a DAC (Sony CX20202A-1) is shown below. In
this case, the clock frequency is 50 MHz and the output
TYPICAL SPECTRUM
Center Frequency:
Frequency Span:
Reference Level:
6.7 MHz
10.0 MHz
–5 dBm
Resolution Bandwidth: 1 KHz
Video Bandwidth:
Scale:
3 kHz
Log, 10 dB/div
6.789 MHz
50 MHz
Output frequency:
Clock frequency:
STEL-1174
8
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Intel® products. No license, express or implied, by estoppel
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ditions of Sale for such products, Intel assumes no liability
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warranty, relating to sale and/or use of Intel® products in-
cluding liability or warranties relating to fitness for a particu-
lar purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sus-
taining applications.
Intel may make changes to specifications and product de-
scriptions at any time, without notice.
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