STEL-1108/CR [ETC]
RF MODULATOR|CMOS|QFP|80PIN|PLASTIC ; 射频调制器| CMOS | QFP | 80PIN |塑料\n
| 型号： | STEL-1108/CR |
| 厂家： | 
ETC |
| 描述： | RF MODULATOR|CMOS|QFP|80PIN|PLASTIC
|
| 文件： | 总22页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STEL-1108
Data Sheet
STEL-1108/CR
126 MHz BPSK/QPSK
Digital Modulator
R
Powered by ICminer.com Electronic-Library Service CopyRight 2003
TCP 960257
TABLE OF CONTENTS
FEATURES/ BENEFITS ................................................................................................................
BLOCK DIAGRAM.......................................................................................................................
PACKAGE OUTLINE...................................................................................................................
PIN CONFIGURATION................................................................................................................
INTRODUCTION.........................................................................................................................
FUNCTION BLOCKS – DESCRIPTION.........................................................................................
Clock Generator Block ......................................................................................................
Input Data Processor Block................................................................................................
FIR Filter Block.................................................................................................................
Interpolating Filter Block...................................................................................................
Frequency Control Word Buffer Block................................................................................
Phase Accumulator & Sine/ Cosine Lookup Table Block......................................................
Complex Modulator Block.................................................................................................
Adder Block .....................................................................................................................
INPUT SIGNAL DESCRIPTIONS ..................................................................................................
OUTPUT SIGNAL DESCRIPTIONS...............................................................................................
3
3
4
4
5
6
6
6
6
6
6
6
6
6
7
9
MODE CONTROL REGISTERS ..................................................................................................... 10
DECIMAL, HEX AND BINARY ADDRESS EQUIVALENTS ........................................................... 13
REGISTER SUMMARY................................................................................................................. 14
ELECTRICAL CHARACTERISTICS............................................................................................... 15
ABSOLUTE MAXIMUM RATINGS ................................................................................... 15
RECOMMENDED OPERATING CONDITIONS................................................................. 15
D.C. CHARACTERISTICS................................................................................................. 15
FREQUENCY CHANGE AND OUTPUT TIMING.............................................................. 16
REGISTER WRITE TIMING............................................................................................... 16
INPUT DATA AND CLOCK TIMING ............................................................................... 17
BURST MODE TIMING .................................................................................................... 19
RECOMMENDED INTERFACE CIRCUIT...................................................................................... 21
SYNCHRONIZING THE 1108 BIT CLOCK .................................................................................... 21
STEL-1 1 0 8
2
Powered by ICminer.com Electronic-Library Service CopyRight 2003
FEATURES
BENEFITS
■ Complete BPSK/ DBPSK/ QPSK/ DQPSK
■ High performance and high reliability with
modulator in a CMOS ASIC
reduced manufacturing costs
■ Operates at up to 6.3 Mbps in BPSK mode
■ Supports data rates for voice and other
and up to 12.6 Mbps in QPSK mode.
applications
■ Programmable over a wide range of data
■ Supports multiple data rate applications
rates
■ Rapidly retunable to any frequency in the
■ NCO modulator provides fine frequency
operating band
resolution
■ Simplifies upconversion of signal to higher
■ 126 MHz maximum clock rate generates
frequencies
modulated carrier at frequencies to 50 MHz
■ Low cost, small, allows quick prototyping
■ Optimizes performance in all modes
■ Optimum interfacing to suitable DAC
■ Eliminates most analog circuitry
■ Operates in continuous and burst mode
■ Selectable 10- or 12-bit outputs
■ Optimum spectral purity of output
■ 32-tap FIR filter for signal shaping before
minimizes external filtering
modulation
■ Small Footprint, Surface Mount
■ 80-Pin MQFP Package
BLOCK DIAGRAM
3
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
PACKAGE OUTLINE
0.913"
±0.008"
0.787"
±0.008"
64
65
41
40
Detail of pins
0.551"
0.677"
± 0.008" ± 0.008"
Top View
Pin 1 Identifier
0.01" max.
0.029"/
0.041"
80
1
25
24
0.0315"
±0.008"
0.012"/0.018"
0.130" max.
Note: Tolerance on pin spacing is not cumulative
Package style: 80-pin MQFP. Thermal coefficient, qja = 58° C/W
WCP 51833.c-8/21/96
PIN CONFIGURATION
––––––––
1
2
3
4
5
6
7
8
9
VDD
17 TSDATA
18 DATAENI
19 TCLK
20 FCWSEL0
21 FCWSEL1
22 I.C.
33 VSS
49 VSS
65 RFCLKD
DATA4
DATA5
DATA6
DATA7
VSS
34 I.C.
50 RFDATA4
51 VDD
66 VSS
––––––
35 I.C.
67 RESET
36 I.C.
52 RFDATA5
53 VSS
68 RFCLKD
69 VSS
37 ACLKOUT
38 VDD
54 RFDATA6
55 VSS
70 DIFFEN
VSS
23 I.C.
39 DATAENO
40 BITCLK
41 VDD
71 NCO LD
–––––
ADDR5
ADDR4
24 I.C.
56 RFDATA7
57 RFDATA8
58 VSS
72 CSEL
–––
25 VDD
73 WR
10 ADDR3
11 VDD
26 CLKEN
27 VSS
42 RFCLK
43 VSS
74 I.C.
59 RFDATA9
60 RFDATA10
61 VSS
75 VDD
12 ADDR2
13 ADDR1
14 ADDR0
15 VSS
28 CLK
44 RFDATA0
45 RFDATA1
46 VSS
76 DATA0
77 DATA1
78 DATA2
79 DATA3
80 VSS
29 NC
30 VDD
62 RFDATA11
63 VDD
31 5VDD
32 N.C.
47 RFDATA2
48 RFDATA3
16 VSS
64 VSS
Notes: I.C. denotes Internal Connection. Do not use for vias.
STEL-1 1 0 8
4
Powered by ICminer.com Electronic-Library Service CopyRight 2003
INTRODUCTION
The STEL-1108 is a BPSK/ QPSK modulator in a single
ASIC.* It is capable of operating at data rates up to
6.3 Mbps in BPSK mode and 12.6 Mbps in QPSK
change filters, providing the ability to operate a single
system in many channels. Signal level scaling is
provided after the FIR filter to allow the maximum
dynamic range of the arithmetic to be utilized since
the signal levels can be changed over a wide range
according to how the device is programmed. To
facilitate interfacing the STEL-1108 to a Digital to
Analog Converter (DAC) an output clock with
programmable delay is provided. In addition, the
STEL-1108 is designed to operate from a 3.3 volt
power supply; provision is made to allow the device
to interface with other logic operating at 5 volts.
mode.
The STEL-1108 will operate at a clock
frequency of up to 126 MHz, allowing it to generate
output signals at carrier frequencies up to 50 MHz.
The STEL-1108 uses digital FIR filtering to optimally
shape the spectrum of the modulating data prior to
modulation, thereby optimizing the spectrum of the
modulated signal while minimizing the analog
filtering required after the modulator. The filters are
designed to have
a symmetrical (mirror image)
polynomial transfer function, thereby making the
phase response of the filter linear and eliminating
inter symbol interference as a result of group delay
distortion. In this way it is possible to change the
carrier frequency over a wide range without having to
See Application Note 125 for example calculations of
control register values.
*The STEL-1108 utilizes advanced signal processing
techniques which are covered by U.S. Patent Number
5,412,352.
5
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
FUNCTION BLOCKS – DESCRIPTION
Cloc k Ge ne ra tor Bloc k
frequency of the FIR filter is set to be four times the
symbol rate. This frequency is determined by the data,
“n”, written into address 29H, with the sampling
frequency set to fCLK/ (n+1), where n can be from 4 to
255.
The timing of the STEL-1108 is controlled by the Clock
Generator Block. This block generates all the clocks
required in the device from the CLK input, as well as
the output clocks. The divider which determines the bit
rate, symbol rate and sampling rate of the FIR filter is
programmed by the data “n” written into address 29H,
with the sampling frequency set to fCLK/ (n+1), where n
can be from 4 to 255. A second divider is used to
generate the auxiliary output clock (ACLKOUT) from
the clock input. This divider is controlled by the data,
“n”, stored in bit 3-0 in address 2A H, with the frequency
set to fCLK/ (n+1), where n can be from 2 to 15. Of all
the clock signals generated, only the auxiliary clock
continues to run when the clock enable is low. The bit
clock output runs at twice the symbol rate, even in
BPSK mode.
Inte rpola ting Filte r Bloc k
The output of the FIR filter is interpolated up to the
clock frequency, fCLK, in a one, two or three stage
interpolating filter. Since the gain of the integrators in
the interpolating filter can vary over a wide range, a
gain control function is provided at its input to select
the significance of the 14-bit outputs of the FIR filter
relative to the 24-bit inputs of the interpolating filter.
This level shift function is controlled by the data stored
in bit 7-4 in address 2AH.
Fre que nc y Control Word Buffe r Bloc k
The STEL-1108 incorporates a Numerically Controlled
Oscillator (NCO) to synthesize the carrier in the mod-
ulator. The frequency of the NCO is programmed by
means of the Frequency Control Word (FCW) registers
Input Da ta Proc e s s or Bloc k
The STEL-1108 is designed to operate as a BPSK, QPSK,
DBPSK or DQPSK modulator according to the setting of
bit 3 in address 2CH and the DIFFEN input. When
operating in QPSK mode the input data processor
assembles pairs of data bits for each symbol to be
modulated. The symbol data can then be differentially
encoded in a way which depends on whether the
modulation format is to be DBPSK or DQPSK. For
DBPSK, the encoding algorithm is straightforward:
at addresses 00H through 08H.
The STEL-1108
incorporates provision for three separate FCWs (FCW
A, FCW B and FCW C) to be stored in these registers.
The modulator frequency can be switched between
these values by means of the FCWSEL1-0 inputs. The
fourth setting of this 2-bit input selects a zero-frequency
value, causing the modulator output to stop instantly at
its current phase.
output bit(k) = input bit(k) Å output bit(k–1),
Pha s e Ac c um ula tor a nd Sine /Cos ine
Lookup Ta ble Bloc k
where Å represents the logical EXOR function. For
DQPSK, however, the differential encoding algorithm is
more complex since there are now sixteen possible new
states depending on the four possible previous output
states and four possible new input states, as shown in
the table below:
The 24-bit NCO gives
a frequency resolution of
approximately 6 Hz at a clock frequency of 100 MHz.
The 12-bit sine and cosine lookup tables (LUTs)
synthesize a carrier with very high spectral purity, typi-
cally better than 75 dBc at the digital outputs.
New Input Previously Encoded OUT(I, Q)k–1
Com ple x Modula tor Bloc k
IN(I, Q)k
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
0
1
1
The interpolated I and Q data signals are fed into the
Complex Modulator Block to be multiplied by the sine
and cosine carriers from the Sin/ Cos LUT Block.
0
0
1
1
0
1
1
0
Adde r Bloc k
The modulated sine and cosine carriers are fed into the
Adder Block where they are either added or subtracted
together to form the sum:
Newly Encoded OUT(I, Q)k
.
.
Sum = ± I cos(wt) ± Q sin(wt)
FIR Filte r Bloc k
The encoded data is filtered to minimize the sidelobes of
its spectrum using a 32-tap, linear phase FIR filter. The
10-bit filter coefficients are completely programmable
for any symmetrical (mirror image) polynomial and are
stored in the registers at addresses 09H to 28H, giving
the user full control (apart from the symmetry
constraint) of the filter response. The clock (sampling)
The signs of the I and Q components can be controlled
by the settings of bits 0 and 1 in address 2BH, giving
complete control over the characteristics of the RF signal
generated.
STEL-1 1 0 8
6
Powered by ICminer.com Electronic-Library Service CopyRight 2003
INPUT SIGNAL DESCRIPTIONS
–––––––
––––––
CSEL (Pin 7 2 )
Chip Select. CSEL is provided to enable or disable
RESET (Pin 6 7 )
––––––
–––––
Reset. RESET is the master reset of the STEL-1108 and
clears or presets all registers when it is set low. Setting
––––––
the microprocessor operation of the STEL-1108. When
–––––
RESET high enables operation of the circuitry. After
CSEL is set high all write operations are disabled.
–––––
the STEL-1108 is powered up, it is necessary to assert
––––––
When CSEL is set low the data bus become active and
the RESET pin low for greater than 100 nS prior to
write operations are enabled.
configuring the chip.
NCO LD (Pin 7 1 )
CLK (Pin 2 8 )
NCO Load Input. The frequency control word selected
by the FCWSEL1-0 inputs will be loaded into the NCO
on the rising edge of NCO LD . This function is also
executed automatically each time the DATAENI input
is set high. There is a pipeline delay of 16 CLK cycles
Master Clock. CLK is the master clock of all the blocks.
Its frequency must be an integer multiple of four times
the data rate used (i.e., an integer multiple of the FIR
Filter sampling rate) so that the programmable binary
divider in the Clock Generator Block can generate the
bit clock from the CLK signal.
from the rising edges of both
NCO LD and
DATAENI to the point where the NCO outputs are
multiplied by the modulating signal in the Modulator
Block. There is a further pipeline delay of 11 CLK
cycles to the output pins, making a total of 27 CLK
cycles from the load command to the output.
CLKEN (Pin 2 6 )
Clock Enable. CLKEN provides a gate to control the
master clock. Setting CLKEN low will disable all
functions in the STEL-1108 (except for the auxiliary
clock output) by stopping the clock internally, thereby
reducing the power consumption almost to the static
level. Setting CLKEN high enables normal operation.
When bit 7 is set high in address 2CH, the STEL-1108
will be configured to operate with an externally
provided data clock, TCLK. When CLKEN is set high
BITCLK will be resynchronized to the first rising edge
of TCLK after the rising edge of CLKEN.
FCWSEL1 -0 (Pins 2 0 , 2 1 )
Frequency Control Word Select. FCWSEL1-0 is a 2-bit
input that permits the selection of one of four frequency
control words for the NCO. In this way the NCO can be
rapidly switched between these four frequencies
without having to reload the FCW data in the FCW
registers. The FCW is selected as follows:
FCWSEL1-0
FCW data register/ addresses
CAUTION: CLKEN must be held low con-
tinuously while programming addresses 2AH and
2BH. Failure to do so will cause the interpolator
to lock up, requiring the STEL-1108 to be reset
before normal operation resumes.
00
01
10
11
FCW ’A’
FCW ’B’
FCW ’C’
FCW = 0 (zero frequency)
Whenever FCWSEL1-0 is changed the NCO frequency
will change after the NCO is reloaded with a rising edge
on either the NCO LD or the DATAENI inputs.. When
FCWSEL1-0 = 11 the FCW data is unconditionally set to
00 00 00 00H, setting the NCO to zero frequency. When
this occurs the NCO output will remain at its current
phase value until FCWSEL1-0 is changed and the NCO
is reloaded.
––––
WR (Pin 7 3 )
–––
Write. WR is used to control the writing of data to the
–––
DATA7-0 bus. When WR is set low the register selected
by the ADDR5-0 lines will become transparent and the
–––
data on the DATA7-0 bus will be latched in when WR
goes high again.
DATA7 -0 (Pins 2 - 5 , 7 6 - 7 9 )
DATAENI (Pin 1 8 )
Data Bus. DATA7-0 is an 8-bit microprocessor interface
Data Enable Input. The DATAENI input is used to
signify the beginning and end of a burst of data. It
should be set high before the first (when the STEL-1108
is configured for BPSK modulation by setting bit 3 in
address 2CH high) or second (when the STEL-1108 is
configured for QPSK modulation by setting bit 3 in
address 2CH low) falling edge of BITCLK (the edge on
which the Q-channel bit is loaded in the QPSK mode) of
each burst and set low again after the last falling edge of
BITCLK of each burst. DATAENO will go high after
the first two symbol periods of eachburst. At this time
the NCO will be reloaded according to the current
bus that provides access to all internal mode control
register inputs for programming. DATA7-0 is used in
–––
conjunction with WR
and ADDR5-0 to write the
information into the control and coefficient registers.
ADDR5 -0 (Pins 8 - 1 0 , 1 2 - 1 4 )
Address Bus. ADDR5-0 is a 6-bit address bus that
selects the mode control register location into which the
information provided on the DATA7-0 bus will be
–––
written. ADDR5-0 is used in conjunction with WR and
DATA7-0 to write the information into the control and
coefficient registers.
setting of FCWSEL1-0
.
7
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DIFFEN (Pin 7 0 )
2CH, the data is latched in on the falling edges of the
BITCLK output. When this bit is set high the data is
latched in on the rising edges of the TCLK input.
Differential Encode enable Input. When DIFFEN is set
low the data will be transmitted without any differential
encoding. When this pin is set high the data will be
TCLK (Pin 1 9 )
differentially
encoded
before
modulation
and
Transmit Clock Input. The STEL-1108 is designed to
operate either in a slave mode, when an external bit
clock is required, or in a master mode, when it provides
its own clock, according to the setting of bit 7 in address
transmission as follows:
DBPSK modulation (bit 3 in address 2CH set high):
The data will be differentially encoded starting with the
bit entering the TSDATA input during the symbol in
which DIFFEN goes high. This bit will be differentially
encoded relative to a logic zero, regardless of the value
of the previous bit.
algorithms:
2CH.
Although the TSDATA signal is sampled
internally on the falling edges of the internally
generated BITCLK signal, a synchronizing circuit is
provided to allow the use of the external data clock,
TCLK, by setting bit 7 high in address 2CH. The TCLK
input must be set to the correct frequency in relation to
the CLK input, i.e., its frequency must be the same as
the bit rate. In this mode the clock generator will free-
run until the first rising edge on TCLK and will then
synchronize BITCLK to this edge to allow TCLK to be
used as the data input clock. The falling edges of
BITCLK will occur n+4 cycles of CLK after the rising
edges of TCLK, where n is the value of the data stored
in the Sampling Rate Control Register at address 29H.
The data will then be latched in on the rising edges of
TCLK before being re-sampled internally with BITCLK.
In the event that the mutual synchronization of the
clocks is lost, the clock generator can be made to
resynchronize itself to TCLK by setting bit 0 in address
2EH high and then low again. BITCLK will be
resynchronized to the first rising edge of TCLK after bit
0 is set low.
The differential encoding
output bit(k) = input bit(k) Å output bit(k–1)
where Å represents the logical XOR function.
DQPSK modulation (bit 3 in address 2CH set low):
The data will be differentially encoded starting with the
bit pair entering the TSDATA input during the symbol
in which DIFFEN goes high. The bits in that symbol
will be differentially encoded relative to a 00 symbol,
regardless of the value of the previous symbol. The
differential encoding algorithm is shown in the table
below:
New Input
IN(I, Q)k
Previously Encoded OUT(I, Q)
k–1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
1
1
0
5 VDD (Pin 3 1 )
To allow the STEL-1108 to be operated with drive
circuits operating from conventional +5 volt logic levels
the input buffers are powered from a separate power
supply pin called 5VDD. This pin should be connected
to the supply from which the drive circuits are powered.
If the drive circuits operate from the same supply
voltage as the STEL-1108 then 5VDD and VDD (+3.3
volts) should be connected together.
Newly Encoded OUT(I, Q)k
TSDATA (Pin 1 7 )
Transmit Serial Data Input. The data to be transmitted
is input at this pin. When bit 7 is set low in address
STEL-1 1 0 8
8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
OUTPUT SIGNAL DESCRIPTIONS
RFDATA1 1 -0 (Pins 4 4 , 4 5 , 4 7 , 4 8 , 5 0 , 5 2 ,
5 4 , 5 6 , 5 7 , 5 9 , 6 0 , 6 2 )
RF Output Data. The 12 MSBs of the internal 15-bit sum
RFCLK (Pin 4 2 )
The RFCLK output is a replica of the input clock signal,
CLK. It is intended to be used to strobe the DAC
connected to the RFDATA11-0 output. To cater for
different DAC characteristics and requirements it is
possible to set the actual timing of RFCLK by means of
bits 6-5 in address 2CH, as shown in the following table:
.
.
of the I cos and Q sin products are brought out as
RFDATA11-0. In some applications it may be desirable
to use a 10-bit DAC with the STEL-1108. In this case the
two MSBs, RFDATA11-10, can be disabled by setting bit
3 high in address 2BH. The signal should then be scaled
after the FIR filter so that the peak amplitude of the
output is no more than 10 bits and the DAC connected
RFCLK Delay
Bits 6-5
0 0
(TYP)
5 nsec
to pins RFDATA9-0
.
DATAENO (Pin 3 9 )
0 1
7 nsec
Data En able Output. DATAENO is a modified replica
of the DATAENI input. It will be set high two symbols
after DATAENI goes high and it will be set low eleven
symbols after DATAENI goes low. In this way,
DATAENO indicates the entire activity period of the
RFDATA11-0 output during the burst.
1 0
9 nsec
1 1
Disabled
Setting 11 disables the RFCLK output, making it pos-
sible to turn off the DAC output in this way. Please refer
to the timing diagrams for further details.
BITCLK (Pin 4 0 )
–––––––––
Bit Clock Output. BITCLK is a 50% duty cycle clock at
twice the symbol rate, which is determined by the value
of the data stored in the Sampling Rate Control Register
at address 29H. If an external transmit data clock is not
available, BITCLK can be used as the clock in QPSK
mode (divide by 2 externally for BPSK mode). When bit
7 in address 2CH is set high the TSDATA signal is first
sampled internally on the rising edges of the TCLK
signal The falling edges of BITCLK will then occur n+4
cycles of CLK after the rising edges of TCLK, where n is
the value of the data stored in the Sampling Rate
Control Register at address 29H. When bit 7 in address
2CH is set low the TSDATA signal will be sampled
directly on the falling edges of BITCLK.
RFCLKD , RFCLKD (Pins 6 5 , 6 8 )
––––––––
The RFCLKD
and RFCLKD outputs are delayed
replicas of the output clock signal, RFCLK. They are
not normally used and are not shown in the block
diagram.
ACLKOUT (Pin 3 7 )
Auxiliary Clock Output. CLK is divided by a factor of
3 to 16 to generate the ACLKOUT signal. The division
factor is determined by the data stored in bits 3-0 of
address 2AH. The frequency is then set to the frequency
of CLK/ (n+1), where n is the value stored in address
2AH and must range from 2 to 15.
ACLKOUT will be high for two cycles of CLK and low
for (n–1) cycles of CLK.
In all cases,
9
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
MODE CONTROL REGISTERS - WRITE ADDRESSES
Addre s s e s 0 0 H - 0 8 H:
NCO Fre que nc y Control Words
Address
09H
FCW Data
Taps 0 and 31, bits 7-0
Taps 0 and 31, bits 9-8
Taps 1 and 30, bits 7-0
Taps 1 and 30, bits 9-8
The internal Carrier NCO is driven by a frequency
control word that is stored in the FCW registers. The
nine 8-bit registers at addresses 00H through 08H are
used to store the three 24-bit frequency control words
FCW ‘A’, FCW ‘B’ and FCW ‘C’ as shown in Table 1.
The LSB of each byte is stored in bit 0 of each register.
0AH
0BH
0CH
…
…
…
…
Address FCW Data
25H
26H
27H
28H
Taps 14 and 17, bits 7-0
Taps 14 and 17, bits 9-8
Taps 15 and 16, bits 7-0
Taps 15 and 16, bits 9-8
00H
01H
02H
03H
04H
05H
06H
07H
08H
FCW ‘A’, bits 7-0
FCW ‘A’, bits 15-8
FCW ‘A’, bits 23-16
FCW ‘B’, bits 7-0
FCW ‘B’, bits 15-8
FCW ‘B’, bits 23-16
FCW ‘C’, bits 7-0
FCW ‘C’, bits 15-8
FCW ‘C’, bits 23-16
Table 2. FIR Filter Coefficient Storage
The filter is always constrained to have symmetrical
coefficients, resulting in a linear phase response. This
allows each coefficient to stored once for two taps, as
shown in the table.
Addre s s 2 9 H:
Sa m pling Ra te , Sym bol Ra te a nd Bit Ra te
Control
Table 1. Carrier NCO FCW Storage
The frequency of the NCO will be:
The timing of the STEL-1108 is controlled by the Clock
Generator Block. This block generates all the clocks
required in the device from the CLK input, as well as
the output clocks. The divider which determines the bit
rate, symbol rate and sampling rate of the FIR filter is
programmed by the data written into address 29H, with
the sampling frequency ranging from fCLK/ 5 to
fCLK/ 256. The sampling rate is then set to the frequency
of CLK/ (n+1), where n is the value stored in address
29H and must range from 4 to 255, unless n is a multiple
of 16. If n is a multiple of 16 the sampling rate will be
set to the frequency of CLK/ (n+17) In all cases this is
further divided by 2 to generate BITCLK. Note that at
CLK frequencies below approximately 64 MHz it is also
permissible to set the sampling rate to 3, giving a
sampling frequency of fCLK/ 4.
.
fCLK FCW
fCARR
=
224
where:
fCLK is the frequency of the CLK input.
and FCW is the FCW data stored in addresses 00H
through 08H as selected by the setting of the FCWSEL1-0
inputs. When FCWSEL1-0 is set to 11 the frequency of
the NCO is set to zero.
Addre s s e s 0 9 H - 2 8 H:
FIR Filte r Coe ffic ie nts
The coefficients of the FIR filter are stored in addresses
09H - 28H, using two addresses for each 10-bit coefficient
as shown in Table 2. The LSB of each byte is stored in
bit 0 of each register, so that bits 9-8 of each coefficient
are stored in bits 1-0 of the corresponding register. The
coefficients are stored as Two’s Complement numbers
in the range –512 to +511 (200H to 1FFH).
Addre s s 2 AH:
CAUTION: CLKEN must be held low con-
tinuously while programming address 2AH.
Failure to do so will cause the interpolator to lock
up, requiring the STEL-1108 to be reset before
normal operation resumes.
STEL-1 1 0 8
10
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Bits 0 through 3 -- Auxilia ry Cloc k Ra te
Control
The timing of the ACLKOUT signal is controlled by the
Clock Generator Block. The divider which determines
the frequency of ACLKOUT is programmed by the data
written into bits 3-0 in address 2AH, with the frequency
ranging from fCLK/ 3 to fCLK/ 16. The frequency is then
set to the frequency of CLK/ (n+1), where n is the value
stored in address 2AH and the valid range is 2 to 15. If
n is set to 1 the ACLKOUT output will remain set high,
thereby disabling this function. If the ACLKOUT signal
is not required, it is recommended that it be set in this
mode to conserve power consumption.
Bits 1-0
0 0
Output of Adder Block
.
.
Sum = I cos(wt) + Q sin(wt)
. .
Sum = –I cos(wt) + Q sin(wt)
0 1
. .
Sum = I cos(wt) – Q sin(wt)
1 0
. .
Sum = –I cos(wt) – Q sin(wt)
1 1
Table 4. Signal Inversion Control
This capability gives complete flexibility to the control
of the output signal.
Bits 4 through 7 -- Inte rpola tion Filte r
Input Ga in Control
Bit 2 -- Te s t Mode
Bit 2 in address 2B sets the STEL-1108 into a test mode
H
Since the gain of the integrators in the interpolation
filter can vary over a wide range, a gain control function
is provided at its input to select the significance of the
14-bit outputs of the FIR filter relative to the 24-bit
inputs of the interpolation filter. This function is
and should always be set low during normal operation.
Bit 3 -- Dis a ble Output MSBs
The STEL-1108 generates a 12-bit output signal OUT11-0
and is designed to be used with a 12-bit DAC. In some
applications it may be desirable to use a 10-bit DAC; in
this case the output signal level should be set so that the
2 MSBs of the output, OUT11-10, are unused. These two
bits can then be disabled to reduce power consumption
by setting bit 3 high in address 2BH. Care should be
taken when this feature is used since no overflow
protection is provided.
controlled by the data stored in bit 7-4 in address 2AH
as shown in Table 3:
,
Bits 7-4
0H
Input signal level of Interpolation Filter
Bits 13-0 Lowest Gain
1H
Bits 14-1
Bits 5 - 4 -- Inte rpola tion Filte r Bypa s s
Control
.....
....
.....
....
Bits 4 and 5 in address 2BH determine the number of
stages of interpolation used in the Interpolation Filter
Block. Three cascaded sections of interpolation are
provided and up to two of these can be bypassed
according to the settings of bits 4 and 5, as shown in
Table 5:
7H
Bits 20-7
8H
Bits 21-8 Highest Gain
Table 3. Interpolation Filter Signal Level Control
Addre s s 2 BH:
Bits 5-4
0 0
Number of Interpolations selected
CAUTION: CLKEN must be held low con-
tinuously while programming address 2BH.
Failure to do so will cause the interpolator to lock
up, requiring the STEL-1108 to be reset before
normal operation resumes.
3
2
2
1
0 1
1 0
Bits 1 - 0 -- Inve rt I/Q Cha nne ls
1 1
The I channel signal is multiplied by the cosine output
from the NCO and the Q channel Signal is multiplied by
the sine output prior to being added together. Bits 0
and 1 in address 2BH allow the two products to be
inverted prior to the addition, as shown in Table 4:
Table 5. Interpolation Filter Bypass Control
Bits 7 - 6 -- Te s t Mode
Bits 6 and 7 in address 2BH set the STEL-1108 into a test
mode and should always be set low.
11
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Addre s s 2 CH:
Bit 0 -- Te s t Mode
Bit 0 in address 2CH sets the STEL-1108 into a test mode
and should always be set low during normal operation.
the clock generator will free-run until the first rising
edge on TCLK and will then synchronize BITCLK to
this edge to allow TCLK to be used as the data input
clock. The data will then be latched in on the rising
edges of TCLK before being re-sampled internally with
BITCLK. In the event that the mutual synchronization
of the clocks is lost, the clock generator can be made to
resynchronize itself to TCLK by setting bit 0 in address
2EH high and then low again. BITCLK will be
resynchronized to the first rising edge of TCLK after bit
0 is set low. When bit 7 is set low in address 2CH the
TSDATA signal will be sampled directly by the falling
edges of BITCLK.
Bit 1 -- FIR Filte r Bypa s s Control
The FIR filters in the STEL-1108 can be bypassed by
setting bit 1 high in address 2CH.
Bit 2 -- Te s t Mode
Bit 2 in address 2CH sets the STEL-1108 into a test mode
and should always be set low during normal operation.
Bit 3 -- BPSK Se le c t
The STEL-1108 is capable of operating as either a BPSK
or a QPSK modulator according to the setting of bit 0 in
address 2CH. Setting this bit low puts the device into the
QPSK mode, generating the output signal:
Addre s s 2 DH:
Bit 0 -- PN Da ta Mode
The STEL-1108 incorporates a pseudo random number
(PN) generator, primarily for test purposes.
When bit 0 is set high in address 2DH the PN generator
will be connected to the data path in place of the normal
input data at the TSDATA input. When this bit is set
low the device will operate in the normal mode,
transmitting the input data.
.
.
RFOUT = ± I cos(wt) ± Q sin(wt)
Setting this bit high puts the device into the BPSK
mode, generating the output signal:
.
RFOUT = ± I cos(wt)
In this case many of the circuits in the Q channel signal
path are disabled to conserve power.
Bit 1 -- PN Code Se le c t
When bit 0 is set high in address 2D H the STEL-1108 PN
generator will be connected to the data path in place of
the normal input data at the TSDATA input. Two
different PN codes can be selected, according the setting
of bit 1 in address 2DH. When this bit is set low the
code will be (10,3) and when it is set high the code will
be (23,18). The latter code is the same as that used in a
TTC FIREBERD 6000 BER test set, allowing the system
to be tested without a second FIREBERD at the transmit
site when the transmitter and receiver are located at
different sites.
Bit 4 -- Te s t Mode
Bit 4 in address 2CH sets the STEL-1108 into a test mode
and should normally be set low. Setting this bit high
complements the frequency control word.
Bits 6 - 5 -- RFCLK De la y Control
Bits 5 and 6 in address 2CH control the delay or phase of
the RFCLK output, as shown in Table 6:
RFCLK Delay
Bits 6-5
0 0
(TYP)
5 nsec
Bit 2 -- Offs e t Bina ry Se le c t
The output signal RFOUT11-0 can be in either two’s
complement or offset binary format , according to the
setting of bit 2 in address 2DH. Setting this bit high
selects two’s complement and setting it low selects
offset binary, as shown in Table 7:
0 1
7 nsec
1 0
9 nsec
1 1
Disabled
Table 6. RFCLK Delay Control
Bit 7 -- Exte rna l Tra ns m it Cloc k Se le c t
RFOUT11-0
The STEL-1108 is designed to operate either in a slave
mode, when an external bit clock is required, or in a
master mode, when it provides its own clock, according
to the setting of bit 7 in address 2CH. Although the
TSDATA signal is sampled internally on the falling
edges of the internally generated BITCLK signal, a
synchronizing circuit is provided to allow the use of the
external data clock, TCLK, by setting bit 7 high in
address 2CH. The TCLK input must be set to the correct
frequency in relation to the CLK input, i.e., its frequency
must be the same as the bit rate. In this mode
Signal
level
Bit 2 = 1 (2’s Comp) Bit 2 = 0 (O. Bin)
Max. +
7FFH (12-bit mode) FFFH
Zero
000H
800H
000H
Max. –
800H (12-bit mode)
Table 7. RFOUT11-0 Signal Formats
STEL-1 1 0 8
12
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Bits 7 - 3 -- Not Us e d
Addre s s 2 EH
Bit 0 -- Bit Cloc k Sync Control
When bit 7 is set high in address 2CH, the STEL-1108
will be configured to operate with an externally
provided data clock, TCLK. The internally generated
BITCLK will be synchronized to the first rising edge of
this clock. In the event that the mutual synchronization
of the clocks is lost, the clock generator can be made to
resynchronize itself to TCLK by setting bit 0 in address
2EH high and then low again. BITCLK will be
resynchronized to the first rising edge of TCLK after bit
0 is set low.
––––––––––––––––––––––––––––––––––––––––––––––––––––
DECIMAL, HEX AND BINARY ADDRESS EQUIVALENTS
Dec.
0
Hex.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Binary
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
Dec.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Hex.
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Binary
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
Dec.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Hex.
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
Binary
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
13
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
REGISTER SUMMARY - WRITE ADDRESSES
Address
Contents
Bit 4 Bit 3
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
00-02H
03-05H
06-08H
09-28H
29H
NCO Frequency Control Word ‘A’ (24 bits)
NCO Frequency Control Word ‘B’ (24 bits)
NCO Frequency Control Word ‘C’ (24 bits)
FIR Filter Coefficients
Sampling Rate, Symbol Rate and Bit Rate Control
2AH
Interpolation Filter Input Gain Control
Set to zero
Auxiliary Clock Rate Control
2BH
Int. Filt. Bypass Control Dis. MSBs Set to zero
Invert I/ Q Channels
2CH
Ext. Tx
Clock Sel.
RFCLK Control
Set to zero
BPSK
Select
Set to zero
FIR
Bypass
Control
Set to zero
2DH
2EH
Offset Bin. PN Code
Select Select
PN Data
Mode
Bit Clock
Sync Cont.
EXAMPLE SOFTWARE INITIALIZATION SEQUENCE
1.
2.
3.
4.
5.
Disable the clock by setting pin 26 (CLKEN) low
Reset the STEL-1108 by pulsing pin 67 (RESETB) low (this clears all internal registers)
Write to all 47 registers
Enable the clock by setting pin 26 (CLKEN) high
Force the internal NCO to load the new frequency register data by pulsing pin 71 (NCO LD) high
STEL-1 1 0 8
14
Powered by ICminer.com Electronic-Library Service CopyRight 2003
ELECTRICAL CHARACTERISTICS
WABaSOrnLiUnTgE: MStArXesIMseUsMgrReAatTeIrNGthSan those shown below may cause permanent damage to
the device. Exposure of the device to these conditions for extended periods may also
affect device reliability. All voltages are referenced to VSS.
Symbol
Tstg
Parameter
Range
Units
°C
Storage Temperature
Supply voltage on VDD
Input voltage
–40 to +125
–0.3 to + 7
–0.3 to 5VDD+0.3
± 30
VDDmax
VI(max)
Ii
volts
volts
mA
DC input current
PDiss (max) Power dissipation, CLKEN = 1
PDiss (max) Power dissipation, CLKEN = 0
690
mW
mW
50
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Range
Units
volts
°C
Supply Voltage
+3.3 ± 10%
–40 to +85
Ta
Operating Temperature (Ambient)
D.C. CHARACTERISTICS Ope ra ting Conditions : VDD = 3.3 V ±10% , V = 0 V, T = –4 0 ° to 8 5 ° C
SS
a
Symbol
IDDQ
Parameter
Min. Typ.
Max. Units
1.0 mA
Conditions
Supply Current, Quiescent
Supply Current, Operational
Clock High Level Input Voltage
Clock Low Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Static, no clock
IDD
2.2
mA/ MHz fCLK = 126 MHz
VIH(min)
VIL(max)
VIH(min)
VIL(max)
IIH
2.0
volts
0.8 volts
volts
CLK, Logic '1'
CLK, Logic '0'
2.0
Other inputs, Logic '1'
Other inputs, Logic '0'
VIN = 5VDD
0.8 volts
10
µA
IIL
–10
µA
VIN = VSS
VOH(min) High Level Output Voltage
VOL(max) Low Level Output Voltage
VOH(min) High Level Output Voltage
2.4
2.4
3.0
0.2
3.0
VDD
volts
IO = –4.0 mA, RFDATA, RFCLK
IO = + 4.0 mA, RFDATA, RFCLK
IO = –2.0 mA, All other
outputs
0.4 volts
VDD
volts
VOL(max) Low Level Output Voltage
0.2
0.4 volts
IO = +2.0 mA, All other
outputs
IOS
Output Short Circuit Current
Input Capacitance
20
65
2
130
mA
pF
VOUT = VDD, VDD = max
All inputs
CIN
COUT
Output Capacitance
4
10
pF
All outputs
15
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
REGISTER WRITE TIMING
CSEL
ADDR 5-0
WR
DON'T CARE
DON'T CARE
tSU1
tHD1
tWR
DATA 7-0
DON'T CARE
DON'T CARE
FREQUENCY CHANGE AND OUTPUT SIGNAL TIMING
tSU
27 CLOCK
EDGES
CLK
tSU2
tCLK
tCRC
tCLK
**
NCO LD
tW
RFCLK
tCRD
OLD FREQUENCY NEW FREQUENCY
RFDATA 11-0
ACLKOUT *
* Shown for ÷5 case (n = 4)
**Insert NCOLD when CLKEN is "HIGH."
TCP 52113.c 9/6/96
STEL-1 1 0 8
16
Powered by ICminer.com Electronic-Library Service CopyRight 2003
INPUT DATA AND CLOCK TIMING
SLAVE MODE
MASTER MODE
DON'T CARE
TCLK
BITCLK
DON'T CARE
tSU3
tHD3
tSU3
tHD3
TSDATA
External Clock ( slave) mode
Internal Clock (master) mode
DON'T
CARE
BITCLK* DON'T CARE
DON'T
CARE
TCLK*
DON'T CARE
tSU3
tHD3
DATAENI
TSDATA DON'T CARE
I
Q
I
Q
Q
I
Q
DON'T CARE
* Depending on clock mode selected
TCP 52111.c 11/25/96
A.C. CHARACTERISTICS
Ope ra ting Conditions : V = 3 .3 V ±1 0 % , V = 0 V, T = –4 0 ° to 8 5 ° C,
DD
SS
a
Symbol
fCLK
Parameter
Min.
Max.
126
Units
MHz
Conditions
See Note
CLK Frequency
tCLK
tWR
tSU1
tHD1
tW
CLK Pulse width, High or Low
2
10
5
nsec.
nsec.
nsec.
nsec.
nsec.
nsec.
nsec.
nsec.
nsec.
–––
WR Pulse width
–––––
–––
–––
DATA7-0, ADDR5-0, CSEL to WR setup
–––––
DATA7-0, ADDR5-0, CSEL to WR hold
NCO LD Pulse width
5
10
5*
tCRC
tCRD
tSU3
tHD3
CLK to RFCLK delay, bits 6-5 in Address 2CH
CLK to RFDATA11-0 delay
9*
12
Load = 10 pF
Load = 10 pF
TSDATA to TCLK or BITCLK setup
TSDATA to TCLK or BITCLK hold
2.5
2.5
*These are the minimum and maximum nominal values programmable.
17
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
INPUT DATA AND CLOCK TIMING
CLKEN
tCT
tDC
DATAENI
DATAENO
DON'T
CARE
TCLK
DON'T CARE (AFTER DATAENI GOES LOW)
TCP 52112.c 11/25/96
A.C. CHARACTERISTICS
Ope ra ting Conditions : V = 3 .3 V ±1 0 % , V = 0 V, T = –4 0 ° to 8 5 ° C,
DD
SS
a
Symbol
Parameter
Min.
Max.
Units
Conditions
tCT
tDC
CLKEN to TCLK setup
2
0
cycles
cycles
of CLK
of CLK
DATAENO to CLKEN hold
STEL-1 1 0 8
18
Powered by ICminer.com Electronic-Library Service CopyRight 2003
BURST TIMING (Sla ve Mode ): FULL VIEW
PIN
NAME
(1)
19
TCLK
(A)
(B)
(C)
(G)
17 TSDATA
26 CLKEN
(F)
(J)
(I)
18 DATAENI
39 DATAENO
(D)
(K)
(2)
(E)
(H)
70 DIFFEN
Preamble
User Data
Guard Time
TCP 52032.c 8/22/96
NOTES:
(1) All input signals shown are derived from TCLK. Each edge is delayed from a TCLK edge by typically 6 to 18
nsec. DATAENO does not depend on TCLK but its edges are synchronized to TCLK. TCLK itself can be turned
off after DATAENI goes low.
(2) If the preamble is not encoded the same as the user data, the DIFFEN control can be toggled in mid transmission
as shown. Otherwise, the DIFFEN control can be held high or low depending on encoding desired.
(A) First data bit transition on falling edge of TCLK (first of 14 preamble symbols). The data will be valid on the next
rising edge of TCLK.
(B) CLKEN rises on the same edge of TCLK that the data starts on. CLKEN is allowed to rise any time earlier than
shown.
(C) DATAENI rises on the first rising edge of TCLK (middle of the first preamble bit).
(D) DATAENO rises on the falling edge of TCLK (at the end of the second symbol).
(E) DIFFEN rises on the rising edge of TCLK immediately preceding the first user data bit.
(F) User data bits are clocked by the falling edge of TCLK and must be valid during the next rising edge of TCLK.
(G) End of user data. Note that the data is allowed to go away immediately after it is latched in by the rising of
TCLK which occurs in the middle of the last user data bit.
H) DIFFEN goes low on rising edge of TCLK (middle of last user data bit).
(I) DATAENI goes low on rising edge of TCLK (on the cycle of TCLK after the last user data bit).
(J) CLKEN must stay high until any time on or after the point where DATAENO goes low.
(K) DATAENO stays high for a period of time about 11 symbols long after DATAENI goes low.
19
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
BURST MODE TIMING: USER BURST DATA INPUT DETAIL
PIN
NAME
TCLK(1)
TSDATA
CLKEN
19
(G)
(F)
1 0
0
1
1
1 0
0
0
0
1
1
1
1
1 0
0
0
0
0
17
26
(I)
18 DATAENI
39 DATAENO
70 DIFFEN(2)
(E)
(H)
TCP 52033.c 8/22/96
BURST MODE TIMING: PREAMBLE START DETAIL
PIN
19
17
26
18
NAME
(1)
TCLK
TSDATA
CLKEN
(A)
I
Q
I
Q
I
(B)
DATAENI
(C)
39 DATAENO
(D)
(2)
70 DIFFEN
TCP 52034.c-8/22/96
STEL-1 1 0 8
20
Powered by ICminer.com Electronic-Library Service CopyRight 2003
RECOMMENDED INTERFACE CIRCUIT (Sla ve Mode )
D
D
Q
Q
TSDATA
CLKEN
TSDATA
OR
CLKEN
DATAENO
STEL-1108
D
Q
DATAENI
DATAENI
D
D
Q
Q
DIFFEN
FCWSEL 1-0
TCLK
DIFFEN
FCWSEL 1-0
TCLK
2
TCP 52118.c 8/16/96
RECOMMENDED INTERFACE CIRCUIT (Ma s te r Mode )
STEL-1108
TSDATA
DATAENI
D
D
Q
Q
D
D
Q
Q
TSDATA
BITCLK
DATAENI
DIFFEN
D
Q
D
D
Q
Q
DIFFEN
TCLK
CLKEN*
*CLKEN may be turned off between bursts to conserve power as long as it is turned on at least
three cycles of BITCLK before TSDATA arrives and kept on until after DATAENO goes low.
Note that the BITCLK output goes inactive whenever CLKEN is low.
TCP 52115.c 9/6/96
SYNCHRONIZING THE 1 1 0 8 BIT CLOCK (Ma s te r Mode )
1) With TCLK Low
2) Preset the bit clock sync circuit by either
A) cycling clock enable from low to high
B) cycling software bit 0 in address 2EH from zero to one and back to zero
3) Bit clock will be in sync after first rising edge of TCLK
4) To keep I/ Q bits synchronized with symbol boundaries, either have an integer number of symbols
(i.e. an even # of bit clocks) between bursts, or resynchronize at the beginning of each burst.
21
STEL-1 1 0 8
Powered by ICminer.com Electronic-Library Service CopyRight 2003
Information in this document is provided in connection with
Intel® products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by
this document. Except as provided in Intels Terms and Con-
ditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel® products in-
cluding liability or warranties relating to fitness for a particu-
lar purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sus-
taining applications.
Intel may make changes to specifications and product de-
scriptions at any time, without notice.
For Further Information Call or Write
INTEL CORPORATION
Cable Network Operation
350 E. Plumeria Drive, San Jose, CA 95134
Customer Service Telephone: (408) 545-9700
Technical Support Telephone: (408) 545-9799
FAX: (408) 545-9888
WCP 970301A
015-140258
Copyright © Intel Corporation, December 15, 1999. All rights reserved
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相关型号：
©2020 ICPDF网 联系我们和版权申明