ESDA14V2SC6 [STMICROELECTRONICS]

QUAD TRANSIL ARRAY FOR ESD PROTECTION; QUAD TRANSIL阵列,用于ESD保护
ESDA14V2SC6
型号: ESDA14V2SC6
厂家: ST    ST
描述:

QUAD TRANSIL ARRAY FOR ESD PROTECTION
QUAD TRANSIL阵列,用于ESD保护

文件: 总7页 (文件大小:72K)
中文:  中文翻译
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ESDAxxSC5  
ESDAxxSC6  
®
QUAD TRANSIL ARRAY  
FOR ESD PROTECTION  
Application Specific Discretes  
A.S.D.  
APPLICATIONS  
Where transient overvoltage protection in ESD  
sensitive equipment is required, such as :  
-COMPUTERS  
- PRINTERS  
- COMMUNICATION SYSTEMS  
- GSM HANDSETS AND ACCESSORIES  
- OTHER TELEPHONE SET  
SOT23-6L (SC-59)  
ESDAxxSC6  
FEATURES  
SOT23-5L (SC-59)  
ESDAxxSC5  
4 UNIDIRECTIONAL TRANSIL FUNCTIONS  
LOW LEAKAGE CURRENT: IR max. < 20 µA at  
VBR  
FUNCTIONAL DIAGRAM  
SOT23-5L  
500 W PEAK PULSE POWER (8/20 µs)  
DESCRIPTION  
The ESDAxxSC5 and ESDAxxSC6 are monolithic  
voltage suppressors designed to protect  
components which are connected to data and  
transmission lines against ESD.  
1
2
5
4
They clamp the voltage just above the logic level  
supply for positive transients, and to a diode drop  
below ground for negative transient.  
3
BENEFITS  
High ESD protection level : up to 25 kV  
High integration  
SOT23-6L  
Suitable for high density boards  
1
2
6
5
COMPLIES WITH THE FOLLOWING STAN-  
DARDS:  
IEC61000-4-2 : level 4  
3
4
MIL STD 883C-Method 3015-6 : class3  
(human body model)  
March 2000 Ed: 5D  
1/7  
ESDAxxSC5 / ESDAxxSC6  
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)  
Symbol  
Test conditions  
Value  
Unit  
VPP  
ESD discharge - MIL STD 883C - Method 3015-6  
IEC61000-4-2 air discharge  
25  
16  
9
kV  
IEC61000-4-2 contact discharge  
PPP  
Tj  
Peak pulse power (8/20µs) note1  
Junction temperature  
500  
150  
W
°C  
°C  
°C  
°C  
Tstg  
TL  
Storage temperature range  
-55 to +150  
260  
Lead solder temperature (10 second duration)  
Operating temperature range  
Top  
-40 to +125  
note 1 : 300 W for ESDA14V2SC5 AND ESDA14V2SC6  
note 2: Evolution of functional parameters is given by curves.  
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)  
I
Symbol  
VRM  
VBR  
VCL  
IRM  
Parameter  
Stand-off voltage  
I
F
Breakdown voltage  
Clamping voltage  
V
BR  
V
V
F
Leakage current  
RM  
V
I
I
IPP  
Peak pulse current  
Voltage temperature coefficient  
Capacitance  
RM  
αT  
C
Rd  
Dynamic resistance  
Forward voltage drop  
1
Rd  
Slope:  
PP  
VF  
VBR  
@
IR  
IRM @ VRM  
Rd  
αT  
C
VF  
@
IF  
min.  
max.  
max.  
typ.  
max.  
typ.  
max.  
Types  
note 1 note 2 0V bias  
V
V
mA  
1
µA  
V
3
mΩ  
10-4/°C  
pF  
V
mA  
ESDA5V3SC5  
ESDA5V3SC6  
5.3  
5.9  
2
230  
5
280  
1.25  
200  
ESDA6V1SC5  
ESDA6V1SC6  
6.1  
14.2  
25  
7.2  
15.8  
30  
1
1
1
20  
5
5.25  
12  
350  
650  
6
190  
100  
60  
1.25  
1.25  
1.2  
200  
200  
10  
ESDA14V2SC5  
ESDA14V2SC6  
10  
10  
ESDA25SC6  
1
24  
1000  
note 1 : Square pulse, Ipp = 15A, tp=2.5µs.  
note 2 : V  
= αT* (Tamb -25°C) * V  
(25°C)  
BR  
BR  
2/7  
ESDAxxSC5 / ESDAxxSC6  
CALCULATION OF THE CLAMPING VOLTAGE  
USE OF THE DYNAMIC RESISTANCE  
The ESDA family has been designed to clamp fast  
spikes like ESD. Generally the PCB designers  
need to calculate easily the clamping voltage VCL.  
This is why we give the dynamic resistance in  
addition to the classical parameters. The voltage  
across the protection cell can be calculated with  
the following formula:  
As the value of the dynamic resistance remains  
stable for a surge duration lower than 20µs, the  
2.5µs rectangular surge is well adapted. In  
addition both rise and fall times are optimized to  
avoid any parasitic phenomenon during the  
measurement of Rd.  
V
CL  
= V + Rd I  
BR PP  
Where Ipp is the peak current through the ESDA cell.  
DYNAMIC RESISTANCE MEASUREMENT  
The short duration of the ESD has led us to prefer  
a more adapted test wave, as below defined, to the  
classical 8/20µs and 10/1000µs surges.  
I
Ipp  
t
2µs  
tp = 2.5µs  
2.5µs duration measurement wave.  
3/7  
ESDAxxSC5 / ESDAxxSC6  
Fig. 1: Peak power dissipation versus initial  
junction temperature.  
Fig. 2: Peak pulse power versus exponential pulse  
duration (Tj initial = 25 °C).  
Ppp[Tj initial]/Ppp[Tj initial=25°C]  
Ppp(W)  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
5000  
ESDA5V3SC5/SC6  
&
ESDA6V1SC5/SC6  
1000  
ESDA14V2SC5/SC6  
&
ESDA25SC6  
Tj initial(°C)  
tp(µs)  
0.1  
0.0  
100  
0
25  
50  
75  
100  
125  
150  
1
10  
100  
Fig. 4: Capacitance versus reverse applied  
voltage (typical values).  
Fig. 3: Clamping voltage versus peak pulse  
current (Tj initial = 25 °C).  
Rectangular waveform tp = 2.5 µs.  
C(pF)  
Ipp(A)  
500  
50.0  
F=1MHz  
Vosc=30mV  
ESDA5V3SC5/SC6  
ESDA25SC5/SC6  
200  
10.0  
ESDA14V2SC5/SC6  
ESDA6V1SC5/SC6  
100  
ESDA6V1SC5/SC6  
50  
ESDA5V3SC5/SC6  
ESDA14V2SC5/SC6  
1.0  
ESDA25SC6  
20  
tp=2.5µs  
VR(V)  
Vcl(V)  
10  
0.1  
1
2
5
10  
20  
50  
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80  
Fig. 5: Relative variation of leakage current versus  
junction temperature (typical values).  
Fig. 6: Peak forward voltage drop versus peak  
forward current (typical values).  
IFM(A)  
IR[Tj] / IR[Tj=25°C]  
5.00  
200  
ESDA5V3SC5/SC6  
ESDA14V2SC5/SC6  
ESDA14V2SC5/SC6  
&
ESDA6V1SC5/SC6  
100  
&
ESDA6V1SC5/SC6  
1.00  
ESDA25SC6  
ESDA25SC6  
10  
0.10  
ESDA5V3SC5/SC6  
Tj(°C)  
Tj=25°C  
VFM(V)  
1
0.01  
25  
50  
75  
100  
125  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4/7  
ESDAxxSC5 / ESDAxxSC6  
ESD protection by ESDAXXXSCX  
Electrostatic discharge (ESD) is a major cause of  
failure in electronic systems.  
They serve as parallel protection elements,  
connected between the signal line and ground. As  
the transient rises above the operating voltage of  
the device, the TVS array becomes a low  
impedance path diverting the transient current to  
ground.  
Transient Voltage Suppressors (TVS) are an ideal  
choice for ESD protection. They are capable of  
clamping the incoming transient overvoltage to a  
low enough level such that damage to the  
protected semiconductor is prevented.  
Surface mount TVS arrays offer the best choice for  
minimal lead inductance.  
I/ O LINES  
ESD  
sensitive  
device  
GND  
ESDA6V1SC6 (1connection to GND for ESDAxxSC5)  
The ESDAxxSCx array is the ideal board level  
protection of ESD sensitive semiconductor  
components.  
The tiny SOT23-5L and SOT23-6L packages allow  
design flexibility in the high density boards where  
the space saving is at a premium. This enables to  
shorten the routing and contributes to hardening  
against ESD.  
ADVICE FOR OPTIMIZING CIRCUIT BOARD  
LAYOUT  
The path length between the ESD suppressor  
and the protected line should be minimized  
Circuit board layout is a critical design step in the  
suppression of ESD induced transients. The  
following guidelines are recommended :  
The ESDAxxSC5/6 should be placed as close as  
possible to the input terminals or connectors.  
All conductive loops, including power and  
ground loops should be minimized  
The ESD transient return path to ground should  
be kept as short as possible.  
Ground planes should be used whenever possi-  
ble.  
5/7  
ESDAxxSC5 / ESDAxxSC6  
ORDER CODE  
ESDA 6V1 SC6  
PACKAGE :  
ESD ARRAY  
SC5: SOT23-5L  
SC6: SOT23-6L  
VBR min  
MARKING  
MARKING  
Type  
Marking  
ES53  
Type  
Marking  
ESDA5V3SC6  
ESDA14V2SC5  
ESDA14V2SC6  
ESDA25SC6  
ESDA6V1SC5  
ESDA6V1SC6  
ESDA5V3SC5  
EC61  
ES61  
EC53  
EC15  
ES15  
ES25  
Packaging: Standard packaging is tape and reel.  
Packaging: Standard packaging is tape and reel.  
PACKAGE MECHANICAL DATA  
SOT23-5L  
A
DIMENSIONS  
H
A2  
REF.  
Millimeters  
Inches  
Min. Typ. Max. Min. Typ. Max.  
e
A
A1  
A2  
b
0.90  
0
1.45 0.035  
0.15  
0.057  
0.006  
0.0512  
0.02  
D
b
0
e
0.90  
0.35  
0.09  
2.80  
1.50  
1.30 0.035  
0.50 0.0137  
0.20 0.004  
3.00 0.11  
1.75 0.059  
A1  
L
c
0.008  
0.118  
0.0689  
D
E
c
M
E
e
0.95  
0.0374  
FOOT PRINT  
H
L
2.60  
0.10  
3.00 0.102  
0.60 0.004  
10°  
0.118  
0.024  
10°  
0.65  
0.025  
M
mm  
inch  
0.95  
0.037  
6/7  
ESDAxxSC5 / ESDAxxSC6  
DIMENSIONS  
PACKAGE MECHANICAL DATA  
SOT23-6L  
A
H
A2  
REF.  
Millimeters  
Inches  
Min. Typ. Max. Min. Typ. Max.  
e
A
A1  
A2  
b
0.90  
0
1.45 0.035  
0.15  
0.057  
0.006  
0.0512  
0.02  
D
b
e
0
0.90  
0.35  
0.09  
2.80  
1.50  
1.30 0.035  
0.50 0.0137  
0.20 0.004  
3.00 0.11  
1.75 0.059  
A1  
C
D
E
0.008  
0.118  
0.0689  
L
c
M
E
e
0.95  
0.0374  
H
L
2.60  
0.10  
3.00 0.102  
0.60 0.004  
10°  
0.118  
0.024  
10°  
FOOT PRINT  
0.65  
0.025  
M
mm  
inch  
0.95  
0.037  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of  
use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by  
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to  
change without notice. This publication supersedes and replaces all information previously supplied.  
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-  
proval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
© 2000 STMicroelectronics - Printed in Italy - All rights reserved.  
STMicroelectronics GROUP OF COMPANIES  
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Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.  
http://www.st.com  
7/7  

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