ESDA18-1F [STMICROELECTRONICS]
Transil, transient voltage suppressor; TRANSIL ，瞬态电压抑制器
| 型号： | ESDA18-1F |
| 厂家： | 
ST |
| 描述： | Transil, transient voltage suppressor |
| 文件： | 总8页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESDA18-1F2
Transil™, transient voltage suppressor
Features
■ Stand-off voltage 16V
■ Unidirectional device
■ Low clamping factor V /V
CL BR
■ Fast response time
■ Very thin package: 0.65 mm
Flip Chip
(4 bumps)
Complies with the following standards
■ IEC 61000-4-2 Level 4
– 15 kV (air discharge)
– 8 kV (contact discharge)
Figure 1.
Pin configuration (bump side)
Description
A
B
The ESDA18-1F2 is a single line Transil diode
designed specifically for the protection of
integrated circuits into portable equipment and
miniaturized electronics devices subject to ESD
and EOS transient overvoltages.
1
2
K
K
A
A
K
A
TM: Transil is a trademark of STMicroelectronics.
April 2008
Rev 2
1/8
www.st.com
8
Characteristics
ESDA18-1F2
1
Characteristics
Table 1.
Symbol
Absolute ratings (limiting value, per diode)
Parameter and test conditions
Value
Unit
Peak pulse power dissipation
10 / 1000 µs pulse
100
700
8
PPP
Tj initial = Tamb
W
Peak pulse power dissipation
8 / 20 µs pulse
tp=10 ms
IFSM
Non repetitive surge peak forward current
A
Tj initial = Tamb
Tj
Maximum operating junction temperature
Storage temperature range
125
°C
°C
Tstg
- 65 to + 175
Table 2.
Symbol
Electrical characteristics (T
= 25 °C)
amb
Parameter
I
IF
VBR
IRM
VRM
VCL
Rd
Breakdown voltage
Leakage current
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Capacitance
VF
V
CLVBR VRM
V
IRM
IPP
C
Slope: 1/Rd
IPP
(1)
(2)
VBR
IRM
VRM VCL
IPP
VF
αT
C
IR
max.
max.
typ.
Order
number
min. max.
max.
max.
IF = 850 mA
VR=0 V
V
V
mA
µA
V
V
A
V
10-4/°C
pF
ESDA18-1F2 16
18
1
0.5
10
20
1
1.3
8.5
230
1. 8 / 20 µs pulse waveform.
2. A DC current is not recommended for more than 5 sec. Even if Transil failure mode is short circuit the
bumps could exceed melting temperature and the component disassembled from the board.
2/8
ESDA18-1F2
Figure 2.
Characteristics
Relative variation of peak pulse
power versus initial junction
temperature
Figure 3.
Peak pulse power versus
exponential pulse duration
P
PP
[T initial] / P [T initial=25°C)
j
PP
j
P (W)
PP
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
10000
1000
100
Tj initial=25°C
T (°C)
j
t (µs)
p
10
0
25
50
75
100
125
150
1
10
100
1000
Figure 4.
Clamping voltage versus peak
pulse current (typical values,
exponential waveform)
Figure 5.
Forward voltage drop versus peak
forward current (typical values)
I
(A)
PP
I
(A)
FM
100.0
10.0
1.0
1.E+01
1.E+00
1.E-01
1.E-02
1.E-03
8/20µs
Tj initial=25°C
Tj=125°C
Tj=25°C
V
(V)
CL
V
(V)
FM
0.1
10
12
14
16
18
20
22
24
26
28
30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 6.
Junction capacitance versus
reverse voltage applied (typical
values)
Figure 7.
Relative variation of leakage
current versus junction
temperature (typical values)
C(pF)
I [T ] / I [T =25°C]
R
j
R
j
300
250
200
150
100
50
100
10
1
VR=10V
F=1MHz
VOSC=30mVRMS
Tj=25°C
V (V)
R
T (°C)
j
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
25
50
75
100
125
3/8
Application information
ESDA18-1F2
2
Application information
One major point is that the ESDA18-1F2 has to ensure the safety during reverse battery
operation. Indeed, during this operation the device must clamp the DC reverse voltage
below 1.3 V @ 0.85 A (max current). Thus reverse battery operation has been simulated by
inverting the polatrity of the Transil (please see figures 8 and 9)
Figure 8.
Reverse battery operation setup
Equivalent
mobile phone
impedance
PTC
I
V
mains
1 nF
4.7 kΩ
V
ESDA18-1F2
Figure 9.
Reverse battery operation results
A short calculation based on Reverse battery operation results figures clearly show that in
such real phone application the ESDA18-1F2 clamp the DC voltage below 1.3 V.
Typically the ESDA18-1F2 can clamp the DC voltage @ 0.9 V @ 0.76 A DC current:
2 × Vmax
2 × 1.4
---------------------- -----------------
VDC
=
≈
≈ 0.9V
Π
3.14
2 × Imax
2 × 1.2
-------------------- -----------------
IDC
=
≈
≈ 0.76A
Π
3.14
4/8
ESDA18-1F2
Ordering information scheme
3
Ordering information scheme
Figure 10. Ordering information scheme
ESDA 18 - 1 Fx
ESD Array
Breakdown Voltage
18 = 18 Volts max.
Number of line
1 = signle line
Package
F = Flip Chip
x = 2: Lead-free, pitch = 500 µm, bump = 315 µm
4
Packing information
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 11. Flip Chip package dimensions
650 µm 65
500 µm 50
315 µm 50
225 µm
0.92 mm 30 µm
5/8
Packing information
ESDA18-1F2
Figure 12. Footprint recommendations Figure 13. Marking
Dot, ST logo
xx = marking
Copper pad Diameter:
250 µm recommended, 300µm max
z = manufacturing location
yww = datecode
(y = year
E
ww = week)
x x z
Solder stencil opening: 330 µm
y
w w
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location
Ø 1.5 0.1
4
0.1
1.0
ST
ST
ST
0.73 0.05
4
0.1
User direction of unreeling
All dimensions in mm
Note:
More packing information is available in the application notes:
AN1235: “Flip Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
6/8
ESDA18-1F2
Ordering information
5
Ordering information
Table 3.
Order code
ESDA18-1F2
Ordering Information
Marking
Package
Weight
Base qty
5000
Delivery mode
EE
Flip Chip
1.25 mg
Tape and reel 7”
6
Revision history
Table 4.
Date
Document revision history
Revision
Changes
09-May-2005
18-Apr-2008
1
2
First issue.
Updated ECOPACK statement. Updated Figure 11, Figure 13, and
Figure 14. Reformatted to current standards.
7/8
ESDA18-1F2
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