CY28409ZXCT [SPECTRALINEAR]
Clock Synthesizer with Differential SRC and CPU Outputs; 时钟合成器与差分SRC和CPU输出
| 型号： | CY28409ZXCT |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Clock Synthesizer with Differential SRC and CPU Outputs |
| 文件： | 总16页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28409
Clock Synthesizer with Differential SRC and CPU Outputs
• Three differential CPU clock pairs
• One differential SRC clock
• I2C support with readback capabilities
Features
• Supports Intel£ Pentium£ꢀ4-type CPUs
• Selectable CPU frequencies
• 3.3V power supply
• Ideal Lexmark Spread Spectrum profile for maximum
EMI reduction
• Ten copies of PCI clocks
• 56-pin SSOP and TSSOP packages
• Five copies of 3V66 with one optional VCH
• Two copies 48 MHz USB clocks
CPU
x 3
SRC
x 1
3V66
x 5
PCI
REF
x 2
48M
x 2
x 10
Pin Configuration[1]
Block Diagram
VDD_REF
REF0:1
REF_0
REF_1
VDD_REF
XIN
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_B
VDD_A
VSS_A
VSS_IREF
IREF
FS_A
CPU_STP#
PCI_STP#
VDD_CPU
CPUT2
CPUC2
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
XIN
XTAL
OSC
XOUT
PLL Ref Freq
VDD_CPU
CPUT[0:2], CPUC[0:2]
Divider
CPU_STP#
PCI_STP#
PLL1
XOUT
Network
VDD_SRC
VSS_REF
PCIF0
PCIF1
SRCT, SRCC
FS_[A:B]
VTT_PWRGD#
PCIF2
9
IREF
VDD_PCI
VSS_PCI
PCI0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD_3V66
3V66_[0:3]
PCI1
PCI2
PCI3
VDD_PCI
PCIF[0:2]
PLL2
2
PCI[0:6]
VDD_PCI
VSS_PCI
PCI4
3V66_4/VCH
PCI5
PCI6
PD#
VDD_48MHz
DOT_48
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
USB_48
DOT_48
USB_48
SDATA
3V66_4/VCH
2
SDATA
SCLK
I C
Logic
56 SSOP/TSSOP
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Rev 1.0, November 22, 2006
Page 1 of 16
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
CY28409
Pin Description
Pin No.
Name
REF(0:1)
XIN
Type
Description
1, 2
4
O, SE Reference Clock. 3.3V 14.318-MHz clock output.
I
Crystal Connection or External Reference Frequency Input. This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
5
XOUT
O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output.
41,44,47
CPUT(0:2)
O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency config-
uration.
40,43,46
CPUC(0:2)
O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency config-
uration.
38, 37
SRCT, SRCC
O, DIF Differential serial reference clock.
22,23,26,27 3V66(0:3)
O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.
O, SE 48-/66-MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz.
O, SE Free-running PCI Output. 33-MHz clocks divided down from 3V66.
O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66.
29
3V66_4VCH
PCIF(0:2)
PCI(0:6)
7,8,9
12,13,14,
15,18,19,20
31,
32
USB_48
DOT_48
FS_A, FS_B
IREF
O, SE Fixed 48-MHz clock output.
O, SE Fixed 48-MHz clock output.
51,56
52
I
I
3.3V LVTTL input for CPU frequency selection.
Current Reference. A precision resistor is attached to this pin which is connected to
the internal current reference.
21
50
49
35
PD#
I, PU 3.3V LVTTL input for Power-Down# active LOW.
I, PU 3.3V LVTTL input for CPU_STP# active LOW.
I, PU 3.3V LVTTL input for PCI_STP# active LOW.
CPU_STP#
PCI_STP#
VTT_PWRGD#
I
3.3V LVTTL input is a level sensitive strobe used to latch the FS_A and FS_B
inputs (active LOW).
30
SDATA
I/O
I
SMBus-compatible SDATA.
SMBus-compatible SCLOCK.
28
SCLK
53
VSS_IREF
VDD_A
GND Ground for current reference.
PWR 3.3V power supply for PLL.
GND Ground for PLL.
55
54
VSS_A
42,48
45
VDD_CPU
VSS_CPU
VDD_SRC
VSS_SRC
VDD_48
PWR 3.3V power supply for outputs.
GND Ground for outputs.
36
PWR 3.3V power supply for outputs.
GND Ground for outputs.
39
34
PWR 3.3V power supply for outputs.
GND Ground for outputs.
33
VSS_48
10,16
11,17
24
VDD_PCI
VSS_PCI
VDD_3V66
VSS_3V66
VDD_REF
VSS_REF
PWR 3.3V power supply for outputs.
GND Ground for outputs.
PWR 3.3V power supply for outputs.
GND Ground for outputs.
25
3
PWR 3.3V power supply for outputs.
GND Ground for outputs.
6
Rev 1.0,November 22, 2006
Page 2 of 16
CY28409
Table 1. Frequency Select Table (FS_A, FS_B)
FS_A
FS_B
0
CPU
100 MHz
REF/N
SRC
3V66
66 MHz
REF/N
66 MHz
66 MHz
Hi-Z
PCIF/PCI
33 MHz
REF/N
33 MHz
33 MHz
Hi-Z
REF0
14.3 MHz
REF/N
REF1
14.31 MHz
REF/N
USB/DOT
48 MHz
REF/N
48 MHz
48 MHz
Hi-Z
0
0
0
1
1
100/200 MHz
REF/N
MID
1
200 MHz
133 MHz
Hi-Z
100/200 MHz
100/200 MHz
Hi-Z
14.3 MHz
14.3 MHz
Hi-Z
14.31 MHz
14.31 MHz
Hi-Z
0
MID
Table 2. Frequency Select Table (FS_A, FS_B) SMBus Bit 5 of Byte 6 = 1
FS_A
FS_B
CPU
SRC
3V66
PCIF/PCI
33 MHz
33 MHz
33 MHz
REF0
REF1
USB/DOT
48 MHz
48 MHz
48 MHz
0
0
1
0
1
0
200 MHz
400 MHz
266 MHz
100/200 MHz
100/200 MHz
100/200 MHz
66 MHz
66 MHz
66 MHz
14.3 MHz
14.3 MHz
14.3 MHz
14.31 MHz
14.31 MHz
14.31 MHz
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels
of FS_A and FS_B except MID, VTT_PWRGD# employs a
Data Protocol
one-shot functionality in that once
a valid LOW on
VTT_PWRGD# has been sampled LOW, all further
VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In
the case where FS_B is at mid level when VTT_PWRGD# is
sampled LOW, the clock chip will assume “Test Clock Mode.”
Once “Test Clock Mode” has been invoked, all further FS_B
transitions will be ignored and FS_A will asynchronously
select between the Hi-Z and REF/N mode. Exiting test mode
is accomplished by cycling power with FS_B in a HIGH or
LOW state.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 3.
Serial Data Interface
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'00000000' stands for block operation
11:18
Command Code – 8 bits
'00000000' stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
Rev 1.0,November 22, 2006
Page 3 of 16
CY28409
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Bit
20:27
28
Description
Bit
20
Byte Count – 8 bits
Repeat start
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
21:27
28
Slave address – 7 bits
Read = 1
29:36
37
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
38:45
46
30:37
38
....
39:46
47
....
Data Byte (N–1) – 8 bits
Acknowledge from slave
Data Byte N – 8 bits
Acknowledge from slave
Stop
....
48:55
56
....
....
....
....
....
....
Table 5. Byte Read and Byte Write protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of the
command code represents the offset of the byte to
be accessed
'100xxxxx' stands for byte operation, bits[4:0] of
the command code represents the offset of the
byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
30:37
38
39
Control Registers
Byte 0:Control Register 0
Bit
7
@Pup
Name
Description
0
1
Reserved
Reserved, Set = 0
6
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
5
4
0
0
Reserved
Reserved
Reserved, Set = 0
Reserved, Set = 0
Rev 1.0,November 22, 2006
Page 4 of 16
CY28409
Byte 0:Control Register 0 (continued)
Bit
@Pup
Name
Description
3
Externally PCI_STP#
Selected
PCI_STP# reflects the current value of the external PCI_STP# pin.
0 = PCI_STP# pin is LOW.
2
1
0
Externally CPU_STP#
Selected
CPU_STP# reflects the current value of the external CPU_STP# pin.
0 = CPU_STP# pin is LOW.
Externally FS_B
Selected
FS_B reflects the value of the FS_B pin sampled on power-up.
Externally FS_A
Selected
FS_A reflects the value of the FS_A pin sampled on power-up.
Byte 1: Control Register 1
Bit
@Pup
Name
SRCT, SRCC
Description
7
0
Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRCT, SRCC
Reserved
SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Reserved, Set = 1
Reserved
Reserved, Set = 1
Reserved
Reserved, Set = 1
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
0
SRCT, SRCC
SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SRCT, SRCC
SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C1 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C0 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C1 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C0 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SW PCI STOP
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6
1
PCI6
PCI6 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0,November 22, 2006
Page 5 of 16
CY28409
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
5
1
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCI5 Output Enable
0 = Disabled, 1 = Enabled
4
3
2
1
0
1
1
1
1
1
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
USB_48
USB_48
PCIF2
PCIF1
PCIF0
PCIF2
PCIF1
PCIF0
USB_48 Drive Strength
0 = High drive strength, 1 = Low drive strength
6
5
4
3
2
1
0
1
0
0
0
1
1
1
USB_48 Output Enable
0 = Disabled, 1 = Enabled
Allow control of PCIF2 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
1
DOT_48
DOT_48 Output Enable
0 = Disabled, 1 = Enabled
6
5
1
0
Reserved
Reserved, Set = 1
3V66_4/VCH
3V66_4/VCH
3V66_3
VCH Select 66-MHz/48-MHz
0 = 3V66 mode, 1 = VCH (48-MHz) mode
4
3
2
1
0
1
1
1
1
1
3V66_4/VCH Output Enable
0 = Disabled, 1 = Enabled
3V66_3 Output Enable
0 = Disabled, 1 = Enabled
3V66_2
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
3V66_1
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
3V66_0
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0,November 22, 2006
Page 6 of 16
CY28409
Byte 6: Control Register 6
Bit
7
@Pup
Name
Description
0
0
0
Reserved
Reserved
Reserved, Set = 0
Reserved, Set = 0
6
5
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
3
2
0
0
Reserved
Reserved, Set = 0
PCIF
PCI
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
1
0
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit @Pup
Name
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
7
6
5
4
3
2
1
0
0
1
0
0
1
0
0
0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Table 6. Crystal Recommendations
Frequency
(Fund)
Drive
(max.)
ShuntCap Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
Cut
Loading Load Cap
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28409 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1. Crystal Capacitive Clarification
Rev 1.0,November 22, 2006
Page 7 of 16
CY28409
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
1
Ce2 + Cs2 + Ci2
1
Ce1 + Cs1 + Ci1
(
)
+
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
C lo ck C h ip
(C Y 2 8 4 0 9 )
Ce..................................................... External trim capacitors
Cs..............................................Stray capacitance (terraced)
C i2
C i1
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
P in
3 to 6 p
PD# (Power-down) Clarification
X 2
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so as not to cause
glitches while changing to the low ‘stopped’ state.
X 1
C s2
C s1
T ra ce
2 .8 p F
X T A L
C e 1
C e 2
T rim
3 3 p F
Figure 2. Crystal Loading Example
PD# Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPU) clocks
must be held LOW on their next HIGH-to-LOW transition. CPU
clocks must be held with CPU clock pin driven HIGH with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0,November 22, 2006
Page 8 of 16
CY28409
PD# Deassertion
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal
will not be driven. Due to the external pull-down circuitry,
CPUC will be LOW during this stopped state.
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising edges of the internal CPUT clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
Tstable
<1.8 ms
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Tdrive_PWRDN#
<300 Ps, >200 mV
Figure 4. Power-down Deassertion Timing Waveform
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPU Internal
Tdrive_CPU_STP#, 10 ns > 200 mV
Figure 6. CPU_STP# Deassertion Waveform
Rev 1.0,November 22, 2006
Page 9 of 16
CY28409
PCI_STP# Assertion[2]
PCI_STP# Deassertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 7.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 7. PCI_STP# Assertion Waveform
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 8. PCI_STP# Deassertion Waveform
Note:
2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.
Rev 1.0,November 22, 2006
Page 10 of 16
CY28409
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3 ms
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 9. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay
>0.25 ms
Sample
Inputs straps
VDDA = 2.0V
Wait for <1.8 ms
S0
S3
VDDA = off
Normal
Operation
Enable Outputs
Power Off
VTT_PWRGD# = toggle
Figure 10. Clock Generator Power-up/Run State Diagram
Rev 1.0,November 22, 2006
Page 11 of 16
CY28409
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
Max.
4.6
Unit
V
VDD_A
VIN
Analog Supply Voltage
4.6
V
Input Voltage
Relative to VSS
–0.5 VDD + 0.5 VDC
TS
Temperature, Storage
Non-functional
–65
150
70
150
15
45
–
°C
°C
TA
Temperature, Operating Ambient
Temperature, Junction
Functional
0
–
TJ
Functional
°C
ØJC
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
MIL-STD-883, Method 3015
@ 1/8 in.
–
°C/W
°C/W
V
ØJA
–
ESDHBM
UL–94
MSL
2000
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VDD_A,
3.3V Operating Voltage
3.3 5ꢀ
3.135
3.465
V
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
VILI2C
VIHI2C
VIL
Input Low Voltage
SDATA, SCLK
SDATA, SCLK
–
2.2
1.0
–
V
V
Input High Voltage
Input Low Voltage
VSS – 0.5
2.0
0.8
V
VIH
Input High Voltage
VDD + 0.5
V
IIL
Input Low Leakage Current
Input High Leakage Current
Output Low Voltage
Output High Voltage
High-impedance Output Current
Dynamic Supply Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
except internal pull-ups resistors, 0 < VIN < VDD
except internal pull-down resistors, 0 < VIN < VDD
IOL = 1 mA
–5
PA
PA
V
IIH
5
0.4
–
VOL
VOH
IOZ
–
IOH = –1 mA
2.4
V
–10
10
PA
mA
pF
pF
nH
V
IDD
All outputs loaded per Table 9 and Figure 11
–
350
5
CIN
2
COUT
LIN
3
6
–
7
VXIH
VXIL
IPD3.3V
Xin High Voltage
0.7VDD
VDD
0.3VDD
1
Xin Low Voltage
0
–
V
Power-down Supply Current
PD# Asserted
mA
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max.
Unit
XIN Duty Cycle
The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle
will not be within specification
47.5
52.5
ꢀ
TPERIOD
XIN Period
When XIN is driven from an external clock
source
69.841
71.0
ns
TR / TF
TCCJ
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Measured between 0.3VDD and 0.7VDD
As an average over 1-Ps duration
Over 150 ms
–
–
10.0
500
300
ns
ps
LACC
ppm
Rev 1.0,November 22, 2006
Page 12 of 16
CY28409
AC Electrical Specifications (continued)
Parameter
CPU at 0.7V
TDC
Description
Condition
Min.
Max.
Unit
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
45
9.9970
7.4978
4.9985
–
55
10.003
7.5023
5.0015
100
ꢀ
ns
ns
ns
ps
ps
ps
ꢀ
TPERIOD
TPERIOD
TPERIOD
TSKEW
TCCJ
100-MHz CPUT and CPUC Period
133-MHz CPUT and CPUC Period
200-MHz CPUT and CPUC Period
Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX
CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX
CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V
–
125
TR / TF
TRFM
175
–
700
Rise/Fall Matching
Determined as a fraction of 2*(TR – TF)/(TR + TF)
20
'TR
'TF
VHIGH
VLOW
VOX
Rise Time Variation
–
125
ps
ps
mV
mV
mV
V
Fall Time Variation
–
125
Voltage High
Math averages Figure 11
Math averages Figure 11
660
–150
250
–
850
Voltage Low
–
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
Minimum Undershoot Voltage
Ring Back Voltage
550
VOVS
VHIGH + 0.3
–
VUDS
–0.3
–
V
VRB
See Figure 11. Measure SE
0.2
V
SRC
TDC
SRCT and SRCC Duty Cycle
100 MHz SRCT and SRCC Period
200 MHz SRCT and SRCC Period
SRCT/C Cycle to Cycle Jitter
SRCT/C Long Term Accuracy
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
45
9.9970
4.9985
–
55
10.003
5.0015
125
ꢀ
ns
ns
ps
ppm
ps
ꢀ
TPERIOD
TPERIOD
TCCJ
LACC
–
300
TR / TF
TRFM
SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V
175
–
700
Rise/Fall Matching
Determined as a fraction of 2*(TR – TF)/(TR + TF)
20
'TR
'TF
VHIGH
VLOW
VOX
Rise Time Variation
–
125
ps
ps
mV
mV
mV
V
Fall Time Variation
–
125
Voltage High
Math averages Figure 11
Math averages Figure 11
660
–150
250
–
850
Voltage Low
–
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
Minimum Undershoot Voltage
Ring Back Voltage
550
VOVS
VHIGH + 0.3
–
VUDS
–0.3
–
V
VRB
See Figure 11. Measure SE
0.2
V
3V66
TDC
3V66 Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.0V
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
45
55
ꢀ
ns
ns
ns
ns
ns
ps
ps
TPERIOD
TPERIOD
THIGH
TLOW
Spread Disabled 3V66 Period
Spread Enabled 3V66 Period
3V66 High Time
14.9955 15.0045
14.9955 15.0799
4.9500
–
3V66 Low Time
4.5500
–
TR / TF
TSKEW
TCCJ
3V66 Rise and Fall Times
Any 3V66 to Any 3V66 Clock Skew
3V66 Cycle to Cycle Jitter
0.5
–
2.0
250
250
–
PCI/PCIF
TDC
PCI Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.0V
Measurement at 0.8V
45
55
ꢀ
ns
ns
ns
ns
TPERIOD
TPERIOD
THIGH
TLOW
Spread Disabled PCIF/PCI Period
Spread Enabled PCIF/PCI Period
PCIF and PCI high time
PCIF and PCI low time
29.9910 30.0009
29.9910 30.1598
12.0
12.0
–
–
Rev 1.0,November 22, 2006
Page 13 of 16
CY28409
AC Electrical Specifications (continued)
Parameter
TR / TF
TSKEW
TCCJ
Description
Condition
Min.
0.5
–
Max.
2.0
Unit
ns
PCIF and PCI rise and fall times
Measured between 0.8V and 2.0V
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
500
250
ps
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
ps
DOT
TDC
Duty Cycle
Measurement at 1.5V
45
55
ꢀ
ns
ps
ns
ns
ns
ps
TPERIOD
TSKEW
THIGH
TLOW
Period
Measurement at 1.5V
20.8271 20.8396
Any 48-MHz to 48-MHz Clock Skew
USB high time
Measured at crossing point VOX
Measurement at 2.0V
–
500
10.486
10.386
1.0
8.994
8.794
0.5
USB low time
Measurement at 0.8V
TR / TF
TCCJ
Rise and Fall Times
Cycle to Cycle Jitter
Measured between 0.8V and 2.0V
Measurement at 1.5V
–
350
USB
TDC
Duty Cycle
Measurement at 1.5V
45
55
ꢀ
ns
ps
ns
ns
ns
ps
TPERIOD
TSKEW
THIGH
TLOW
Period
Measurement at 1.5V
20.8271 20.8396
Any 48-MHz to 48-MHz Clock Skew
USB high time
Measured at crossing point VOX
Measurement at 2.0V
–
500
10.036
9.836
2.0
8.094
7.694
1.0
USB low time
Measurement at 0.8V
TR / TF
TCCJ
Rise and Fall Times
Cycle to Cycle Jitter
Measured between 0.8V and 2.0V
Measurement at 1.5V
–
350
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
69.827
–
55
69.855
500
ꢀ
ns
ps
ns
ps
TPERIOD
TSKEW
TR / TF
TCCJ
REF Period
Measurement at 1.5V
Any REF to REF Clock Skew
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Measured at crossing point VOX
Measured between 0.8V and 2.0V
Measurement at 1.5V
0.5
2.0
–
1000
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS
–
10.0
0
1.8
–
ms
ns
ns
Stopclock Set-up Time
Stopclock Hold Time
TSH
–
Table 7. Group Timing Relationship and Tolerances
Offset
Group
Conditions
Min.
Max.
3V66 to PCI
3V66 Leads PCI
1.5 ns
3.5 ns
Table 8. USB to DOT Phase Offset
Parameter
DOT Skew
USB Skew
VCH SKew
Typical
0°
Value
Tolerance
1000 ps
1000 ps
1000 ps
0.0 ns
0.0 ns
0.0 ns
180°
0°
Table 9. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
pF
PCI Clocks
3V66 Clocks
USB Clock
DOT Clock
REF Clock
30
30
20
10
30
pF
pF
pF
pF
Rev 1.0,November 22, 2006
Page 14 of 16
CY28409
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
M easurem ent
Point
TPCB
33:
CPUT
49.9:
2 pF
M easurem ent
Point
TPCB
49.9:
33:
CPUC
IREF
2 pF
475:
Figure 11. 0.7V Load Configuration
O u tp u t u n d e r Te s t
P ro b e
L o a d C a p
3.3V sig n als
tD C
-
-
3 .3V
2 .0 V
1 .5 V
0 .8 V
0 V
T r
T f
Figure 12. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, IREF – VDD (3*RREF
)
Output Current
Voh @ Z
50 Ohms
RREF = 475 1ꢀ, IREF = 2.32 mA
IOH = 6*IREF
0.7V @ 50
Ordering Information
Part Number
Package Type
Product Flow
CY28409OC
CY28409OCT
CY28409ZC
CY28409ZCT
PB-Free
56-pin SSOP
56-pin SSOP – Tape and Reel
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
56-pin TSSOP
56-pin TSSOP – Tape and Reel
CY28409OXC
CY28409OCXT
CY28409ZXC
CY28409ZXCT
56-pin SSOP
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
56-pin SSOP – Tape and Reel
56-pin TSSOP
56-pin TSSOP – Tape and Reel
Rev 1.0,November 22, 2006
Page 15 of 16
CY28409
Package Drawings and Dimensions
56-lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
7.950[0.313]
8.255[0.325]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.508[0.020]
0.762[0.030]
0.051[0.002]
0.152[0.006]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0°-8°
0.100[0.003]
0.200[0.008]
0.170[0.006]
0.279[0.011]
SEATING
PLANE
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 22, 2006
Page 16 of 16
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