CY28410OC [SPECTRALINEAR]
Clock Generator for Intel Grantsdale Chipset; 时钟发生器为英特尔的Grantsdale芯片组型号: | CY28410OC |
厂家: | SPECTRALINEAR INC |
描述: | Clock Generator for Intel Grantsdale Chipset |
文件: | 总17页 (文件大小:220K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY28410
Clock Generator for Intel£ Grantsdale Chipset
• 33 MHz PCI clock
Features
• Low-voltage frequency select input
• I2C support with readback capabilities
• Compliant with Intel£ CK410
• Supports Intel P4 and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU
SRC
PCI
x 9
REF
x 1
DOT96
x 1
USB_48
x 1
x2 / x3
x6 / x7
Block Diagram
Pin Configuration
VDD_REF
REF
VDD_PCI
VSS_PCI
PCI3
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI2
PCI1
PCI0
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
SRCT6
XIN
XTAL
OSC
XOUT
PLL Ref Freq
VDD_CPU
PCI4
PCI5
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
VDD_SRC
Divider
PLL1
Network
SRCT[1:6], SRCC[1:6]
FS_[C:A]
VTT_PWRGD#
9
IREF
PCIF2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD_PCI
PCI[0:5]
VDD_48
USB_48
VSS_48
DOT96T
DOT96C
VDD_PCIF
PCIF[0:2]
PD
VDD_48 MHz
FS_B/TEST_MODE
VTT_PWRGD#/PD
FS_A
DOT96T
DOT96C
PLL2
USB_48
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRC4-SATAT
SRC4_SATAC
VDD_SRC
SRCC6
SRCT5
SRCC5
VSS_SRC
2
SDATA
SCLK
I C
Logic
56 SSOP/TSSOP
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 17
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
CY28410
Pin Definitions
Pin No.
Name
CPUT/C
Type
Description
44,43,41,40
36,35
O, DIF Differential CPU clock outputs.
CPUT2_ITP/SRCT7, O, DIF Selectable Differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
CPUC2_ITP/SRCC7
14,15
18
DOT96T, DOT96C
FS_A
O, DIF Fixed 96-MHz clock output.
I
3.3V tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
16
53
39
FS_B/TEST_MODE
FS_C/TEST_SEL
IREF
I
3.3V tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z,1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
I
I
3.3V tolerant input for CPU frequency selection. Selects test mode if pulled
to VIHFS_C when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
A Precision resistor is attached to this pin, which is connected to the internal
current reference.
54,55,56,3,4,5 PCI
O, SE 33-MHz clocks.
O, SE 33-MHz clocks.
9,10
8
PCIF
PCIF0/ITP_EN
I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
52
REF
O, SE Reference clock. 3.3V 14.318 MHz clock output.
46
SCLK
SDATA
I
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
47
I/O
26,27
SRC4_SATAT,
SRC4_SATAC
O, DIF Differential serial reference clock. recommended output for SATA.
19,20,22,23,2 SRCT/C
4,25,31,30,33,
32
O, DIF Differential serial reference clocks.
12
USB_48
I/O, SE Fixed 48 MHz clock output.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
GND Ground for outputs.
11
VDD_48
42
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
1,7
48
21,28,34
37
13
VSS_48
45
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
GND Ground for outputs.
2,6
51
GND Ground for outputs.
GND Ground for outputs.
29
GND Ground for outputs.
38
GND Ground for PLL.
17
VTT_PWRGD#/PD
I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a realtime input for asserting
power-down (active high)
50
49
XIN
I
14.318-MHz Crystal Input
XOUT
O, SE 14.318-MHz Crystal Output
Rev 1.0,November 21, 2006
Page 2 of 17
CY28410
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
one-shot functionality in that once
a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
FS_B
FS_A
CPU
100 MHz
133 MHz
200 MHz
266 MHz
Hi-Z
SRC
100 MHz
100 MHz
100 MHz
100 MHz
Hi-Z
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
Hi-Z
USB
48 MHz
48 MHz
48 MHz
48 MHz
Hi-Z
MID
0
0
0
1
0
0
1
1
1
1
0
0
x
0
1
0
0
1
1
REF/2
REF/8
REF/24
REF/24
REF
REF
REF
1
REF/2
REF/8
REF
REF
REF
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
28
36:29
37
Acknowledge from slave
Data byte 1 – 8 bits
27:21
28
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte 2 – 8 bits
29
Acknowledge from slave
Byte Count from slave – 8 bits
45:38
37:30
Rev 1.0,November 21, 2006
Page 3 of 17
CY28410
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Bit
46
....
....
....
....
Description
Acknowledge from slave
Bit
38
Acknowledge
Data Byte /Slave Acknowledges
Data Byte N –8 bits
Acknowledge from slave
Stop
46:39
47
Data byte 1 from slave – 8 bits
Acknowledge
55:48
56
Data byte 2 from slave – 8 bits
Acknowledge
....
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
....
....
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
27:21
28
Slave address – 7 bits
Read
29
29
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
37:30
38
39
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
Description
7
1
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
CPU[T/C]2_ITP/SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
Reserved
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Reserved, Set = 1
Rev 1.0,November 21, 2006
Page 4 of 17
CY28410
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
DOT_96T/C
USB_48
REF
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF Output Enable
0 = Disabled, 1 = Enabled
3
2
0
1
Reserved
Reserved
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1
0
1
0
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPUT/C
SRCT/C
PCIF
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
PCI
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF2
PCIF1
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
6
5
4
3
2
0
0
0
0
0
SRC6
SRC5
SRC4
SRC3
SRC2
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Rev 1.0,November 21, 2006
Page 5 of 17
CY28410
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
0
0
Reserved
Reserved, Set = 0
Byte 4: Control Register 4
Bit
7
@Pup
Name
Description
0
0
Reserved
DOT96[T/C]
Reserved, Set = 0
6
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
4
3
0
0
0
PCIF2
PCIF1
PCIF0
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
2
1
0
1
1
1
Reserved
Reserved
Reserved
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
6
5
4
3
0
0
0
0
Reserved
Reserved
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
Reserved
SRC[T/C][7:0]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2
1
0
0
0
0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
REF/N or Hi-Z Select
1 = REF/N Clock, 0 = Hi-Z
6
0
Test Clock Mode Entry Control
1 = REF/N or Hi-Z mode, 0 = Normal operation
5
4
0
1
Reserved
REF
Reserved, Set = 0
REF Output Drive Strength
0 = Low, 1 = High
3
1
PCIF, SRC, PCI
SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Rev 1.0,November 21, 2006
Page 6 of 17
CY28410
Byte 6: Control Register 6 (continued)
Bit
@Pup
Name
Description
2
Externally
selected
CPUT/C
FS_C. Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
1
0
Externally
selected
CPUT/C
CPUT/C
FS_B. Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
Externally
selected
FS_A. Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
7
@Pup
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
1
0
1
0
0
0
6
5
4
3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Crystal Recommendations
Crystal Loading
The CY28410 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28410 to
operate at the wrong frequency and \violate the ppm specifi-
cation. For most applications there is a 300ppm frequency shift
between series and parallel crystals due to incorrect loading.
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Table 5. Crystal Recommendations
Frequency
(Fund)
Drive
(max.)
ShuntCap Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
Cut
Loading Load Cap
Parallel 20 pF
(max.)
14.31818 MHz
AT
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
Rev 1.0,November 21, 2006
Page 7 of 17
CY28410
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Clock Chip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs2
Cs1
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tance loading on both sides.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
1
CLe
=
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
1
Ce2 + Cs2 + Ci2
1
Ce1 + Cs1 + Ci1
(
)
+
CL ................................................... Crystal load capacitance
(lead frame, bond wires etc.)
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
Rev 1.0,November 21, 2006
Page 8 of 17
CY28410
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks are driven to a
low value and held prior to turning off the VCOs and the crystal
oscillator.
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,166,200,266,333, and 400
MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10 uS
after asserting VTT_PWRGD#.
PD (Power-down) – Assertion
PD Deassertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must be held high
or Hi-Z (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within 4
clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output must be held
with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#”
tristate. If the control register PD drive mode bit corresponding
to the output of interest is programmed to “1”, then both the
“Diff clock” and the “Diff clock#” are Hi-Z. Note the example
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power-down must be driven high in
less than 300 Ps of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0,November 21, 2006
Page 9 of 17
CY28410
Tstable
<1.8nS
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 5. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay
>0.25mS
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8ms
S0
S3
VDD_A = off
Normal
Operation
Enable Outputs
Power Off
VTT_PWRGD# = toggle
Figure 6. Clock Generator Power-up/Run State Diagram
Rev 1.0,November 21, 2006
Page 10 of 17
CY28410
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
Max.
4.6
Unit
V
VDD_A
VIN
Analog Supply Voltage
Input Voltage
4.6
V
Relative to VSS
–0.5 VDD + 0.5 VDC
TS
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Non-functional
Functional
Functional
SSOP
–65
0
150
70
°C
°C
TA
TJ
–
150
°C
ØJC
Dissipation, Junction to Case
(Mil-Spec 883E Method 1012.1)
39.56
°C/W
TSSOP
20.62
45.29
62.26
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
SSOP
°C/W
V
TSSOP
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model)
Flammability Rating
MIL-STD-883, Method 3015
At 1/8 in.
2000
–
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VDD_A,
3.3V Operating Voltage
3.3 5%
3.135
3.465
V
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
VILI2C
VIHI2C
VIL_FS
VIH_FS
VILFS_C
VIMFS_C
VIH FS_C
VIL
Input Low Voltage
SDATA, SCLK
SDATA, SCLK
–
2.2
1.0
–
V
V
Input High Voltage
FS_A/FS_B Input Low Voltage
FS_A/FS_B Input High Voltage
FS_C Low Range
VSS – 0.3
0.7
0.35
V
VDD + 0.5
0.35
V
0
V
FS_C Mid Range
0.7
1.7
V
FS_C High Range
2.1
VDD
V
Input Low Voltage
VSS – 0.5
2.0
0.8
V
VIH
Input High Voltage
VDD + 0.5
V
IIL
Input Low Leakage Current
Input High Leakage Current
Output Low Voltage
except internal pull-up resistors, 0 < VIN < VDD
except internal pull-down resistors, 0 < VIN < VDD
IOL = 1 mA
–5
PA
PA
V
IIH
5
0.4
–
VOL
–
VOH
Output High Voltage
High-impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
IOH = –1 mA
2.4
V
IOZ
–10
10
PA
pF
pF
nH
V
CIN
2
5
COUT
LIN
3
6
–
7
VXIH
Xin High Voltage
0.7VDD
VDD
0.3VDD
550
70
VXIL
Xin Low Voltage
0
–
–
V
IDD3.3V
IPD3.3V
Dynamic Supply Current
Power-down Supply Current
At max load and freq per Figure 8
mA
mA
PD asserted, Outputs driven
Rev 1.0,November 21, 2006
Page 11 of 17
CY28410
DC Electrical Specifications (continued)
Parameter
Description
Condition
PD asserted, Outputs Hi-Z
Min.
Max.
Unit
IPD3.3V
Power-down Supply Current
–
2
mA
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
XIN Period
The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5
52.5
71.0
%
TPERIOD
When XIN is driven from an external clock
source
69.841
ns
TR / TF
TCCJ
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Measured between 0.3VDD and 0.7VDD
As an average over 1-Ps duration
Over 150 ms
–
–
–
10.0
500
300
ns
ps
LACC
ppm
CPU at 0.7V
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
43
57
%
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIODSS
100-MHz CPUT and CPUC Period
133-MHz CPUT and CPUC Period
200-MHz CPUT and CPUC Period
266-MHz CPUT and CPUC Period
9.997001 10.00300 ns
7.497751 7.502251 ns
4.998500 5.001500 ns
3.748875 3.751125 ns
100-MHz CPUT and CPUC Period,
SSC
9.997001 10.05327 ns
7.497751 7.539950 ns
4.998500 5.026634 ns
3.748875 3.769975 ns
9.912001 10.08800 ns
7.412751 7.587251 ns
9.912001 10.13827 ns
7.412751 7.624950 ns
4.913500 5.111634 ns
3.663875 3.854975 ns
2.414250 2.598317 ns
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODAbs
TPERIODAbs
133-MHz CPUT and CPUC Period,
SSC
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
200-MHz CPUT and CPUC Period,
SSC
266-MHz CPUT and CPUC Period,
SSC
100-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period
133-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
TPERIODSSAbs 133-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
TPERIODSSAbs 200-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
TPERIODSSAbs 266-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
TPERIODSSAbs 400-MHz CPUT and CPUC Absolute Measured at crossing point VOX
period, SSC
TSKEW
Any CPUT/C to CPUT/C Clock Skew, Measured at crossing point VOX
SSC
–
100
ps
TCCJ2
TCCJ
CPU2_ITP Cycle to Cycle Jitter
CPUT/C Cycle to Cycle Jitter
CPU2_ITP to CPU0 Clock Skew
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
–
–
–
125
115
150
ps
ps
ps
TSKEW2
TR / TF
CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH
0.525V
=
175
1100
ps
Rev 1.0,November 21, 2006
Page 12 of 17
CY28410
AC Electrical Specifications (continued)
Parameter
TRFM
Description
Rise/Fall Matching
Condition
Min.
Max.
Unit
Determined as a fraction of 2*(TR – TF)/(TR
+ TF)
–
20
%
'TR
Rise Time Variation
–
–
125
125
850
–
ps
ps
'TF
Fall Time Variation
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 8
Math averages Figure 8
660
–150
250
mV
mV
mV
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
550
VOVS
VHIGH
0.3
+
–
V
VUDS
VRB
Minimum Undershoot Voltage
Ring Back Voltage
–0.3
–
–
V
V
See Figure 8. Measure SE
0.2
SRC
TDC
SRCT and SRCC Duty Cycle
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
45
55
%
TPERIOD
100-MHz SRCT and SRCC Period
9.997001 10.00300 ns
9.997001 10.05327 ns
TPERIODSS
100-MHz SRCT and SRCC Period,
SSC
TPERIODAbs
100-MHz SRCT and SRCC Absolute Measured at crossing point VOX
Period
10.12800 9.872001 ns
9.872001 10.17827 ns
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Measured at crossing point VOX
Period, SSC
TSKEW
TCCJ
SRC Skew
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
–
–
–
250
125
300
ps
ps
SRCT/C Cycle to Cycle Jitter
SRCT/C Long Term Accuracy
LACC
ppm
TR / TF
SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH
0.525V
=
175
–
1100
20
ps
%
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR – TF)/(TR
+ TF)
'TR
Rise Time Variation
–
–
125
125
850
–
ps
ps
'TF
Fall Time Variation
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 8
Math averages Figure 8
660
–150
250
mV
mV
mV
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
550
VOVS
VHIGH
0.3
+
–
V
VUDS
VRB
Minimum Undershoot Voltage
Ring Back Voltage
–0.3
–
–
V
V
See Figure 8. Measure SE
0.2
PCI/PCIF
TDC
PCI Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled PCIF/PCI Period
29.99100 30.00900 ns
29.9910 30.15980 ns
29.49100 30.50900 ns
29.49100 30.65980 ns
TPERIODSS
Spread Enabled PCIF/PCI Period,
SSC
TPERIODAbs
Spread Disabled PCIF/PCI Period
Measurement at 1.5V
Measurement at 1.5V
TPERIODSSAbs Spread Enabled PCIF/PCI Period,
SSC
THIGH
TLOW
PCIF and PCI high time
Measurement at 2.4V
11.5
11.5
0.5
–
–
ns
ns
ns
PCIF and PCI low time
Measurement at 0.4V
TR / TF
PCIF and PCI rise and fall times
Measured between 0.8V and 2.0V
2.0
Rev 1.0,November 21, 2006
Page 13 of 17
CY28410
AC Electrical Specifications (continued)
Parameter
TSKEW
Description
Condition
Min.
Max.
500
Unit
ps
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
–
–
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
500
ps
DOT
TDC
DOT96T and DOT96C Duty Cycle
DOT96T and DOT96C Period
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
45
55
%
TPERIOD
10.41354 10.41979 ns
10.16354 10.66979 ns
TPERIODAbs
DOT96T and DOT96C Absolute
Period
TCCJ
DOT96T/C Cycle to Cycle Jitter
DOT96T/C Long Term Accuracy
Measured at crossing point VOX
Measured at crossing point VOX
–
–
250
100
ps
LACC
ppm
TR / TF
DOT96T and DOT96C Rise and Fall Measured from VOL = 0.175 to VOH =
175
–
1100
20
ps
%
Times
0.525V
TRFM
Rise/Fall Matching
Determined as a fraction of 2*(TR – TF)/(TR
+ TF)
'TR
Rise Time Variation
–
–
125
125
850
–
ps
ps
'TF
Fall Time Variation
VHIGH
VLOW
VOX
Voltage High
Math averages Figure 8
Math averages Figure 8
660
–150
250
mV
mV
mV
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
550
VOVS
VHIGH
0.3
+
–
V
VUDS
VRB
Minimum Undershoot Voltage
Ring Back Voltage
–0.3
–
–
V
V
See Figure 8. Measure SE
0.2
USB
TDC
Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.4V
Measurement at 0.4V
Measured between 0.8V and 2.0V
Measurement at 1.5V
45
55
%
TPERIOD
TPERIODAbs
THIGH
Period
20.83125 20.83542 ns
20.48125 21.18542 ns
Absolute Period
USB high time
USB low time
8.094
7.694
0.475
–
10.036
9.836
1.4
ns
ns
ns
ps
TLOW
TR / TF
TCCJ
Rise and Fall Times
Cycle to Cycle Jitter
USB Long Term Accuracy
350
LACC
–
100
ppm
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
TPERIODAbs
TR / TF
REF Period
Measurement at 1.5V
69.8203 69.8622 ns
68.82033 70.86224 ns
REF Absolute Period
REF Rise and Fall Times
REF Cycle to Cycle Jitter
Measurement at 1.5V
Measured between 0.8V and 2.0V
Measurement at 1.5V
0.35
–
2.0
V/ns
ps
TCCJ
1000
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS
–
10.0
0
1.8
–
ms
ns
ns
Stopclock Set-up Time
Stopclock Hold Time
TSH
–
Rev 1.0,November 21, 2006
Page 14 of 17
CY28410
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
Measurement
Point
ꢂꢃ:
ꢂꢃ:
ꢀꢁ:
5pF
PCI/
USB
Measurement
Point
ꢀꢁ:
5pF
Measurement
Point
5pF
ꢂꢃ:
ꢂꢃ:
ꢂꢃ:
ꢀꢁ:
Measurement
Point
5pF
ꢀꢁ:
REF
Measurement
Point
ꢀꢁ:
5pF
Figure 7. Single-ended Load Configuration
For Differential CPU, SRC and DOT96 Output Signals
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
M e a s u re m e n t
P o in t
ꢄ ꢄ :
C P U T
S R C T
D O T 9 6 T
2 p F
ꢅ ꢆ ꢇꢆ :
ꢀ ꢃ ꢃ : ꢊD iffe re n tia l
M e a s u re m e n t
P o in t
2 p F
ꢄ ꢄ :
C P U C
S R C C
D O T 9 6 C
IR E F
ꢅ ꢆ ꢇꢆ :
ꢅ ꢈ ꢉ :
Figure 8. 0.7V Single-ended Load Configuration
3 .3 V s ig n a ls
T D C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0 V
T R
T F
Figure 9. Single-ended Output Signals (for AC Parameters Measurement)
Rev 1.0,November 21, 2006
Page 15 of 17
CY28410
Ordering Information
Part Number
Standard
Package Type
Product Flow
CY28410OC
56-pin SSOP
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
CY28410OCT
CY28410ZC
56-pin SSOP – Tape and Reel
56-pin TSSOP
CY28410ZCT
Lead-free (Planned)
CY28410OXC
CY28410OXCT
CY28410ZXC
CY28410ZXCT
56-pin TSSOP – Tape and Reel
56-pin SSOP
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
56-pin SSOP – Tape and Reel
56-pin TSSOP
56-pin TSSOP – Tape and Reel
Rev 1.0,November 21, 2006
Page 16 of 17
CY28410
Package Drawing and Dimensions
56-lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
7.950[0.313]
8.255[0.325]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.508[0.020]
0.762[0.030]
0.051[0.002]
0.152[0.006]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0°-8°
0.100[0.003]
0.200[0.008]
0.170[0.006]
0.279[0.011]
SEATING
PLANE
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 21, 2006
Page 17 of 17
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