CY28410OC_技术文档

CY28410

Clock Generator for Intel^Grantsdale Chipset

• 33-MHz PCI clock

Features

• Low-voltage frequency select input

• Compliant with Intel^CK410

• I²C support with readback capabilities

• Supports Intel P4 and Tejas CPU

• Selectable CPU frequencies

• Differential CPU clock pairs

• 100-MHz differential SRC clocks

• 96-MHz differential dot clock

• 48-MHz USB clocks

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 56-pin SSOP and TSSOP packages

CPU

SRC

PCI

x 9

REF

x 1

DOT96

x 1

USB_48

x 1

x2 / x3

x6 / x7

Block Diagram

Pin Configuration

VDD_REF

REF

VDD_PCI

VSS_PCI

PCI3

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PCI2

XIN

XTAL

OSC

2

PCI1

PCI0

XOUT

PLL Ref Freq

3

VDD_CPU

PCI4

4

FS_C/TEST_SEL

REF

CPUT[0:1], CPUC[0:1],

CPU(T/C)2_ITP]

VDD_SRC

Divider

PLL1

PCI5

5

Network

VSS_PCI

VDD_PCI

PCIF0/ITP_EN

PCIF1

6

VSS_REF

XIN

SRCT[1:6], SRCC[1:6]

7

FS_[C:A]

VTT_PWRGD#

8

XOUT

9

VDD_REF

SDATA

IREF

PCIF2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VDD_PCI

PCI[0:5]

VDD_PCIF

PCIF[0:2]

VDD_48

USB_48

VSS_48

DOT96T

DOT96C

SCLK

VSS_CPU

CPUT0

CPUC0

VDD_CPU

CPUT1

PD

VDD_48 MHz

FS_B/TEST_MODE

VTT_PWRGD#/PD

FS_A

DOT96T

DOT96C

USB_48

CPUC1

PLL2

IREF

SRCT1

VSSA

SRCC1

VDDA

VDD_SRC

SRCT2

CPUT2_ITP/SRCT7

CPUC2_ITP/SRCC7

VDD_SRC

SRCT6

SRCC2

SRCT3

SRCC3

SRCC6

SRC4-SATAT

SRC4_SATAC

VDD_SRC

SRCT5

2

SDATA

SCLK

I C

Logic

SRCC5

VSS_SRC

56 SSOP/TSSOP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07593 Rev. *C

Revised Sept. 28, 2204

CY28410

Pin Definitions

Pin No.

Name

Type

Description

44,43,41,40

CPUT/C

O, DIF Differential CPU clock outputs.

36,35

CPUT2_ITP/SRCT7, O, DIF Selectable Differential CPU or SRC clock output.

CPUC2_ITP/SRCC7

ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7

ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2

14,15

18

DOT96T, DOT96C

FS_A

O, DIF Fixed 96-MHz clock output.

I

3.3V tolerant input for CPU frequency selection.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

16

53

39

FS_B/TEST_MODE

FS_C/TEST_SEL

IREF

I

3.3V tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when

in test mode

0 = Hi-Z,1 = Ref/N

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

I

3.3V tolerant input for CPU frequency selection. Selects test mode if pulled

to V_{IHFS_C}when VTT_PWRGD# is asserted low.

Refer to DC Electrical Specifications table for V_{ILFS_C},V_{IMFS_C},V_{IHFS_C}specifi-

cations.

A Precision resistor is attached to this pin, which is connected to the internal

current reference.

54,55,56,3,4,5 PCI

O, SE 33-MHz clocks.

9,10

8

PCIF

PCIF0/ITP_EN

I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).

1 = CPU2_ITP, 0 = SRC7

52

REF

O, SE Reference clock. 3.3V 14.318 MHz clock output.

46

47

SCLK

SDATA

I

SMBus-compatible SCLOCK.

SMBus-compatible SDATA.

I/O

26,27

SRC4_SATAT,

O, DIF Differential serial reference clock. recommended output for SATA.

SRC4_SATAC

19,20,22,23,2 SRCT/C

4,25,31,30,33,

32

O, DIF Differential serial reference clocks.

12

11

42

1,7

48

21,28,34

37

13

USB_48

VDD_48

I/O, SE Fixed 48 MHz clock output.

PWR 3.3V power supply for outputs.

PWR 3.3V power supply for PLL.

GND Ground for outputs.

VDD_CPU

VDD_PCI

VDD_REF

VDD_SRC

VDDA

VSS_48

45

2,6

51

29

38

VSS_CPU

VSS_PCI

VSS_REF

VSS_SRC

VSSA

GND Ground for outputs.

GND Ground for PLL.

17

VTT_PWRGD#/PD

I, PU 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,

FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#

(active low) assertion, this pin becomes a realtime input for asserting

power-down (active high)

50

49

XIN

XOUT

I

14.318-MHz Crystal Input

O, SE 14.318-MHz Crystal Output

Document #: 38-07593 Rev. *C

Page 2 of 18

CY28410

samples the FS_A, FS_B and FS_C input values. For all logic

levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a

Frequency Select Pins (FS_A, FS_B and FS_C)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A, FS_B, FS_C inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip

one-shot functionality in that once

a

valid low on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FS_A, FS_B and FS_C transitions will be ignored, except in

test mode.

Table 1. Frequency Select Table FS_A, FS_B and FS_C

FS_C

MID

0

1

FS_B

FS_A

CPU

100 MHz

133 MHz

200 MHz

266 MHz

Hi-Z

SRC

100 MHz

Hi-Z

PCIF/PCI

33 MHz

Hi-Z

REF0

14.318 MHz

Hi-Z

DOT96

96 MHz

Hi-Z

USB

48 MHz

Hi-Z

0

1

0

1

0

x

0

1

REF/2

REF/8

REF/24

REF

Serial Data Interface

Data Protocol

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface initial-

izes to their default setting upon power-up, and therefore use

of this interface is optional. Clock device register changes are

normally made upon system initialization, if any are required.

The interface cannot be used during system operation for pow-

er management functions.

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in se-

quential order from lowest to highest byte (most significant bit

first) with the ability to stop after any complete byte has been

transferred. For byte write and byte read operations, the sys-

tem controller can access individually indexed bytes. The off-

set of the indexed byte is encoded in the command code, as

described in Table 2.

The block write and block read protocol is outlined in Table 3

while Table 4 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Table 2. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

18:11

19

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

10

18:11

19

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeat start

27:20

Byte Count – 8 bits

20

(Skip this step if I²C_EN bit set)

28

36:29

37

45:38

46

Acknowledge from slave

Data byte 1 – 8 bits

Acknowledge from slave

Data byte 2 – 8 bits

27:21

28

29

37:30

38

Slave address – 7 bits

Read = 1

Acknowledge from slave

Byte Count from slave – 8 bits

Acknowledge

Acknowledge from slave

Document #: 38-07593 Rev. *C

Page 3 of 18

CY28410

Table 3. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Description

Data byte 1 from slave – 8 bits

Bit

....

Description

Data Byte /Slave Acknowledges

Data Byte N –8 bits

Bit

46:39

47

Acknowledge

Acknowledge from slave

Stop

55:48

56

Data byte 2 from slave – 8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave – 8 bits

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

18:11

19

27:20

28

29

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Data byte – 8 bits

Acknowledge from slave

Stop

10

18:11

19

20

27:21

28

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeated start

Slave address – 7 bits

Read

29

37:30

38

Acknowledge from slave

Data from slave – 8 bits

NOT Acknowledge

Stop

39

Control Registers

Byte 0:Control Register 0

Bit

@Pup

Name

Description

7

1

CPUT2_ITP/SRCT7

CPU[T/C]2_ITP/SRC[T/C]7 Output Enable

CPUC2_ITP/SRCC7

0 = Disable (Hi-Z), 1 = Enable

6

5

4

3

2

1

0

1

SRC[T/C]6

SRC[T/C]5

SRC[T/C]4

SRC[T/C]3

SRC[T/C]2

SRC[T/C]1

Reserved

SRC[T/C]6 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]5 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]4 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]3 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]2 Output Enable

0 = Disable (Hi-Z), 1 = Enable

SRC[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enable

Reserved, Set = 1

Document #: 38-07593 Rev. *C

Page 4 of 18

CY28410

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

1

PCIF0

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

1

DOT_96T/C

USB_48

REF

DOT_96 MHz Output Enable

0 = Disable (Hi-Z), 1 = Enabled

USB_48 MHz Output Enable

0 = Disabled, 1 = Enabled

REF Output Enable

0 = Disabled, 1 = Enabled

3

2

0

1

Reserved

CPU[T/C]1

Reserved

CPU[T/C]1 Output Enable

0 = Disable (Hi-Z), 1 = Enabled

1

0

1

0

CPU[T/C]0

CPU[T/C]0 Output Enable

0 = Disable (Hi-Z), 1 = Enabled

CPUT/C

SRCT/C

PCIF

Spread Spectrum Enable

0 = Spread off, 1 = Spread on

PCI

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

PCI5

PCI5 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

3

2

1

0

1

PCI4

PCI3

PCI2

PCI1

PCI0

PCIF2

PCIF1

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2 Output Enable

0 = Disabled, 1 = Enabled

PCI1 Output Enable

0 = Disabled, 1 = Enabled

PCI0 Output Enable

0 = Disabled, 1 = Enabled

PCIF2 Output Enable

0 = Disabled, 1 = Enabled

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

0

SRC7

Allow control of SRC[T/C]7 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

6

5

4

3

2

0

SRC6

SRC5

SRC4

SRC3

SRC2

Allow control of SRC[T/C]6 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Allow control of SRC[T/C]5 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Allow control of SRC[T/C]4 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Allow control of SRC[T/C]3 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Allow control of SRC[T/C]2 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Document #: 38-07593 Rev. *C

Page 5 of 18

CY28410

Byte 3: Control Register 3 (continued)

Bit

@Pup

Name

Description

1

0

SRC1

Allow control of SRC[T/C]1 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

0

Reserved

Reserved, Set = 0

Byte 4: Control Register 4

Bit

7

@Pup

Name

Reserved

Description

0

Reserved, Set = 0

6

0

DOT96[T/C]

DOT_PWRDWN Drive Mode

0 = Driven in PWRDWN, 1 = Hi-Z

5

4

3

0

PCIF2

PCIF1

PCIF0

Allow control of PCIF2 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Allow control of PCIF1 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

Allow control of PCIF0 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

2

1

0

1

Reserved

Reserved, Set = 1

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

0

SRC[T/C][7:0]

SRC[T/C] Stop Drive Mode

0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#

asserted

6

5

4

3

0

Reserved

Reserved, Set = 0

SRC[T/C][7:0]

SRC[T/C] PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Hi-Z when PD asserted

2

1

0

CPU[T/C]2

CPU[T/C]1

CPU[T/C]0

CPU[T/C]2 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Hi-Z when PD asserted

CPU[T/C]1 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Hi-Z when PD asserted

CPU[T/C]0 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Hi-Z when PD asserted

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

REF/N or Hi-Z Select

1 = REF/N Clock, 0 = Hi-Z

6

0

Test Clock Mode Entry Control

1 = REF/N or Hi-Z mode, 0 = Normal operation

5

4

0

1

Reserved

REF

Reserved, Set = 0

REF Output Drive Strength

0 = Low, 1 = High

3

1

PCIF, SRC, PCI

SW PCI_STP# Function

0=SW PCI_STP assert, 1 = SW PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

Document #: 38-07593 Rev. *C

Page 6 of 18

CY28410

Byte 6: Control Register 6 (continued)

Bit

@Pup

Name

Description

2

Externally

CPUT/C

FS_C. Reflects the value of the FS_C pin sampled on power-up

selected

0 = FS_C was low during VTT_PWRGD# assertion

1

0

Externally

selected

CPUT/C

FS_B. Reflects the value of the FS_B pin sampled on power-up

0 = FS_B was low during VTT_PWRGD# assertion

Externally

FS_A. Reflects the value of the FS_A pin sampled on power-up

selected

0 = FS_A was low during VTT_PWRGD# assertion

Byte 7: Vendor ID

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

Vendor ID Bit 2

Vendor ID Bit 1

Vendor ID Bit 0

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

Vendor ID Bit 2

Vendor ID Bit 1

Vendor ID Bit 0

0

1

0

1

0

Crystal Recommendations

Crystal Loading

The CY28410 requires a Parallel Resonance Crystal. Substi-

tuting a series resonance crystal will cause the CY28410 to

operate at the wrong frequency and \violate the ppm specifi-

cation. For most applications there is a 300ppm frequency shift

between series and parallel crystals due to incorrect loading.

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

The following diagram shows a typical crystal configuration

using the two trim capacitors. An important clarification for the

following discussion is that the trim capacitors are in series

with the crystal not parallel. It’s a common misconception that

load capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

Table 5. Crystal Recommendations

Frequency

Drive

ShuntCap Motional

Tolerance

(max.)

35 ppm

Stability

(max.)

30 ppm

Aging

(max.)

5 ppm

Cut

Loading Load Cap

Parallel 20 pF

(Fund)

(max.)

14.31818 MHz

AT

0.1 mW

5 pF

0.016 pF

Document #: 38-07593 Rev. *C

Page 7 of 18

CY28410

Figure 1. Crystal Capacitive Clarification

Calculating Load Capacitors

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

Clock Chip

Ci2

Ci1

3 to 6p

X2

X1

Cs2

Cs1

Trace

2.8pF

XTAL

Ce1

Ce2

Trim

33pF

Figure 2. Crystal Loading Example

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the total capac-

itance on each side of the crystal must be twice the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capac-

itors(Ce1,Ce2) should be calculated to provide equal capaci-

tance loading on both sides.

Load Capacitance (each side)

Ce = 2 * CL – (Cs + Ci)

Total Capacitance (as seen by the crystal)

1

+

CLe

=

Use the following formulas to calculate the trim capacitor

1

(

)

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

values fro Ce1 and Ce2.

Document #: 38-07593 Rev. *C

Page 8 of 18

CY28410

CL ...................................................Crystal load capacitance

mode bit) on the next diff clock# high to low transition within 4

clock periods. When the SMBus PD drive mode bit corre-

sponding to the differential (CPU, SRC, and DOT) clock output

of interest is programmed to ‘0’, the clock output must be held

with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#”

tristate. If the control register PD drive mode bit corresponding

to the output of interest is programmed to “1”, then both the

“Diff clock” and the “Diff clock#” are Hi-Z. Note the example

below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all

differential outputs. This diagram and description is applicable

to valid CPU frequencies 100,133,166,200,266,333, and 400

MHz. In the event that PD mode is desired as the initial

power-on state, PD must be asserted high in less than 10 uS

after asserting VTT_PWRGD#.

CLe .........................................Actual loading seen by crystal

using standard value trim capacitors

Ce .....................................................External trim capacitors

Cs.............................................. Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

PD (Power-down) Clarification

The VTT_PWRGD# /PD pin is a dual function pin. During initial

power-up, the pin functions as VTT_PWRGD#. Once

VTT_PWRGD# has been sampled low by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active high input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD is also an asynchronous input for powering up the

system. When PD is asserted high, all clocks are driven to a

low value and held prior to turning off the VCOs and the crystal

oscillator.

PD Deassertion

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a three-state

condition resulting from power-down must be driven high in

less than 300 µs of PD deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each other. Below is an example showing the relationship of

clocks coming up.

PD (Power-down) – Assertion

When PD is sampled high by two consecutive rising edges of

CPUC, all single-ended outputs will be held low on their next

high to low transition and differential clocks must be held high

or Hi-Z (depending on the state of the control register drive

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 3. Power-down Assertion Timing Waveform

Document #: 38-07593 Rev. *C

Page 9 of 18

CY28410

Tstable

<1.8nS

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33MHz

REF

Tdrive_PW RDN#

<300µS, >200mV

Figure 4. Power-down Deassertion Timing Waveform

FS_A, FS_B,FS_C

VTT_PWRGD#

PWRGD_VRM

0.2-0.3mS

Delay

Wait for

Device is not affected,

VTT_PWRGD# is ignored

Sample Sels

State 2

VDD Clock Gen

Clock State

VTT_PWRGD#

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 5. VTT_PWRGD# Timing Diagram

S2

S1

VTT_PWRGD# = Low

Delay

>0.25mS

Sample

Inputs straps

VDD_A = 2.0V

Wait for <1.8ms

S0

S3

VDD_A = off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 6. Clock Generator Power-up/Run State Diagram

Document #: 38-07593 Rev. *C

Page 10 of 18

CY28410

Absolute Maximum Conditions

Parameter

V_DD

V_{DD_A}

V_IN

Description

Core Supply Voltage

Analog Supply Voltage

Input Voltage

Condition

Min.

–0.5

Max.

4.6

Unit

V

Relative to V_SS

–0.5 V_DD+ 0.5 VDC

T_S

T_A

T_J

Ø_JC

Temperature, Storage

Temperature, Operating Ambient

Temperature, Junction

Non-functional

Functional

SSOP

TSSOP

SSOP

TSSOP

MIL-STD-883, Method 3015

At 1/8 in.

–65

0

–

150

70

150

°C

Dissipation, Junction to Case

39.56

°C/W

(Mil-Spec 883E Method 1012.1)

20.62

45.29

62.26

Ø_JA

Dissipation, Junction to Ambient

JEDEC (JESD 51)

°C/W

V

ESD_HBM

UL-94

MSL

ESD Protection (Human Body Model)

Flammability Rating

Moisture Sensitivity Level

2000

–

V–0

1

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing

is NOT required.

DC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

VDD_A_,

3.3V Operating Voltage

3.3 ± 5%

3.135

3.465

V

VDD_REF,

VDD_PCI,

VDD_3V66,

VDD_48,

VDD_CPU

V_ILI2C

V_IHI2C

V_{IL_FS}

V_{IH_FS}

V_{ILFS_C}

V_{IMFS_C}

V_{IH FS_C}

V_IL

Input Low Voltage

Input High Voltage

FS_A/FS_B Input Low Voltage

FS_A/FS_B Input High Voltage

FS_C Low Range

FS_C Mid Range

FS_C High Range

Input Low Voltage

Input High Voltage

SDATA, SCLK

–

2.2

V_SS– 0.3

0.7

1.0

–

0.35

V

V_DD+ 0.5

0.35

1.7

V_DD

0.8

V_DD+ 0.5

0

0.7

2.1

V_SS– 0.5

2.0

V_IH

I_IL

I_IH

V_OL

V_OH

Input Low Leakage Current

Input High Leakage Current

Output Low Voltage

except internal pull-up resistors, 0 < V_IN< V_DD

except internal pull-down resistors, 0 < V_IN< V_DD

I_OL= 1 mA

–5

µA

V

5

0.4

–

2.4

Output High Voltage

I_OH= –1 mA

V

I_OZ

C_IN

C_OUT

L_IN

V_XIH

High-impedance Output Current

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

Xin High Voltage

Xin Low Voltage

Dynamic Supply Current

Power-down Supply Current

–10

2

3

–

10

5

6

7

V_DD

0.3V_DD

550

70

µA

pF

nH

V

0.7V_DD

V_XIL

0

–

V

I_DD3.3V

I_PD3.3V

At max load and freq per Figure 8

PD asserted, Outputs driven

PD asserted, Outputs Hi-Z

mA

2

Document #: 38-07593 Rev. *C

Page 11 of 18

CY28410

AC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

Crystal

T_DC

XIN Duty Cycle

XIN Period

The device will operate reliably with input

duty cycles up to 30/70 but the REF clock

duty cycle will not be within specification

47.5

52.5

71.0

%

T_PERIOD

When XIN is driven from an external clock

69.841

ns

source

T_R/ T_F

T_CCJ

L_ACC

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Long-term Accuracy

Measured between 0.3V_DDand 0.7V_DD

As an average over 1-µs duration

Over 150 ms

–

10.0

500

300

ns

ps

ppm

CPU at 0.7V

T_DC

CPUT and CPUC Duty Cycle

Measured at crossing point V_OX

43

57

%

T_PERIOD

T_PERIODSS

100-MHz CPUT and CPUC Period

133-MHz CPUT and CPUC Period

200-MHz CPUT and CPUC Period

266-MHz CPUT and CPUC Period

9.997001 10.00300 ns

7.497751 7.502251 ns

4.998500 5.001500 ns

3.748875 3.751125 ns

100-MHz CPUT and CPUC Period,

9.997001 10.05327 ns

7.497751 7.539950 ns

4.998500 5.026634 ns

3.748875 3.769975 ns

9.912001 10.08800 ns

7.412751 7.587251 ns

9.912001 10.13827 ns

7.412751 7.624950 ns

4.913500 5.111634 ns

3.663875 3.854975 ns

2.414250 2.598317 ns

SSC

T_PERIODSS

T_PERIODAbs

133-MHz CPUT and CPUC Period,

SSC

Measured at crossing point V_OX

200-MHz CPUT and CPUC Period,

SSC

266-MHz CPUT and CPUC Period,

SSC

100-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period

133-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period

T_PERIODSSAbs100-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period, SSC

T_PERIODSSAbs133-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period, SSC

T_PERIODSSAbs200-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period, SSC

T_PERIODSSAbs266-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period, SSC

T_PERIODSSAbs400-MHz CPUT and CPUC Absolute Measured at crossing point V_OX

period, SSC

T_SKEW

Any CPUT/C to CPUT/C Clock Skew, Measured at crossing point V_OX

SSC

–

100

ps

T_CCJ2

T_CCJ

T_SKEW2

T_R/ T_F

CPU2_ITP Cycle to Cycle Jitter

CPUT/C Cycle to Cycle Jitter

CPU2_ITP to CPU0 Clock Skew

Measured at crossing point V_OX

–

125

115

150

ps

CPUT and CPUC Rise and Fall Times Measured from V_OL= 0.175 to V_OH

=

175

–

1100

20

ps

%

0.525V

T_RFM

Rise/Fall Matching

Determined as a fraction of 2*(T_R– T_F)/(T_R

+ T_F)

∆T_R

∆T_F

V_HIGH

Rise Time Variation

Fall Time Variation

Voltage High

–

660

125

850

ps

mV

Math averages Figure 8

Document #: 38-07593 Rev. *C

Page 12 of 18

CY28410

AC Electrical Specifications (continued)

Parameter

V_LOW

V_OX

V_OVS

Description

Condition

Math averages Figure 8

Min.

–150

250

Max.

–

550

Unit

mV

Voltage Low

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

V_HIGH

+

–

V

0.3

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

0.2

V

See Figure 8. Measure SE

SRC

T_DC

SRCT and SRCC Duty Cycle

100-MHz SRCT and SRCC Period

Measured at crossing point V_OX

45

55

%

T_PERIOD

T_PERIODSS

9.997001 10.00300 ns

100-MHz SRCT and SRCC Period,

9.997001 10.05327 ns

SSC

T_PERIODAbs

100-MHz SRCT and SRCC Absolute Measured at crossing point V_OX

Period

10.12800 9.872001 ns

9.872001 10.17827 ns

T_PERIODSSAbs100-MHz SRCT and SRCC Absolute Measured at crossing point V_OX

Period, SSC

T_SKEW

T_CCJ

L_ACC

SRC Skew

SRCT/C Cycle to Cycle Jitter

SRCT/C Long Term Accuracy

Measured at crossing point V_OX

–

250

125

300

ps

ppm

T_R/ T_F

SRCT and SRCC Rise and Fall Times Measured from V_OL= 0.175 to V_OH

=

175

–

1100

20

ps

%

0.525V

T_RFM

Rise/Fall Matching

Determined as a fraction of 2*(T_R– T_F)/(T_R

+ T_F)

∆T_R

∆T_F

V_HIGH

V_LOW

V_OX

Rise Time Variation

Fall Time Variation

Voltage High

Voltage Low

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

–

660

–150

250

125

850

–

ps

mV

Math averages Figure 8

550

V_OVS

V_HIGH

+

–

V

0.3

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

0.2

V

See Figure 8. Measure SE

PCI/PCIF

T_DC

PCI Duty Cycle

Spread Disabled PCIF/PCI Period

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODSS

29.99100 30.00900 ns

29.9910 30.15980 ns

29.49100 30.50900 ns

29.49100 30.65980 ns

Spread Enabled PCIF/PCI Period,

SSC

T_PERIODAbs

Spread Disabled PCIF/PCI Period

Measurement at 1.5V

T_PERIODSSAbsSpread Enabled PCIF/PCI Period,

SSC

T_HIGH

T_LOW

T_R/ T_F

T_SKEW

T_CCJ

PCIF and PCI high time

PCIF and PCI low time

PCIF and PCI rise and fall times

Any PCI clock to Any PCI clock Skew Measurement at 1.5V

Measurement at 2.4V

Measurement at 0.4V

Measured between 0.8V and 2.0V

11.5

0.5

–

2.0

500

ns

ps

PCIF and PCI Cycle to Cycle Jitter

Measurement at 1.5V

–

DOT

T_DC

DOT96T and DOT96C Duty Cycle

DOT96T and DOT96C Period

Measured at crossing point V_OX

45

55

%

T_PERIOD

10.41354 10.41979 ns

Document #: 38-07593 Rev. *C

Page 13 of 18

CY28410

AC Electrical Specifications (continued)

Parameter

Description

Condition

Min.

Max.

Unit

T_PERIODAbs

DOT96T and DOT96C Absolute

Measured at crossing point V_OX

10.16354 10.66979 ns

Period

T_CCJ

L_ACC

DOT96T/C Cycle to Cycle Jitter

DOT96T/C Long Term Accuracy

Measured at crossing point V_OX

–

250

100

ps

ppm

T_R/ T_F

DOT96T and DOT96C Rise and Fall Measured from V_OL= 0.175 to V_OH=

175

–

1100

20

ps

%

Times

0.525V

T_RFM

Rise/Fall Matching

Determined as a fraction of 2*(T_R– T_F)/(T_R

+ T_F)

∆T_R

∆T_F

V_HIGH

V_LOW

V_OX

Rise Time Variation

Fall Time Variation

Voltage High

Voltage Low

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

–

660

–150

250

125

850

–

ps

mV

Math averages Figure 8

550

V_OVS

V_HIGH

+

–

V

0.3

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

0.2

V

See Figure 8. Measure SE

USB

T_DC

Duty Cycle

Period

Absolute Period

USB high time

USB low time

Rise and Fall Times

Cycle to Cycle Jitter

USB Long Term Accuracy

Measurement at 1.5V

Measurement at 2.4V

Measurement at 0.4V

Measured between 0.8V and 2.0V

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODAbs

T_HIGH

T_LOW

T_R/ T_F

T_CCJ

20.83125 20.83542 ns

20.48125 21.18542 ns

8.094

7.694

0.475

–

10.036

9.836

1.4

ns

ps

350

L_ACC

–

100

ppm

REF

T_DC

REF Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODAbs

T_R/ T_F

REF Period

Measurement at 1.5V

Measured between 0.8V and 2.0V

Measurement at 1.5V

69.8203 69.8622 ns

68.82033 70.86224 ns

REF Absolute Period

REF Rise and Fall Times

REF Cycle to Cycle Jitter

0.35

–

2.0

1000

V/ns

ps

T_CCJ

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SS

–

10.0

0

1.8

–

ms

ns

Stopclock Set-up Time

Stopclock Hold Time

T_SH

Document #: 38-07593 Rev. *C

Page 14 of 18

CY28410

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the test load configurations for

the single-ended PCI, USB, and REF output signals.

Measurement

Point

60Ω

12Ω

5pF

PCI/

USB

Measurement

12Ω

Point

5pF

Measurement

Point

60Ω

12Ω

5pF

Measurement

12Ω

Point

REF

5pF

Measurement

12Ω

Point

5pF

Figure 7. Single-ended Load Configuration

For Differential CPU, SRC and DOT96 Output Signals

The following diagram shows the test load configuration for the

differential CPU and SRC outputs.

M e a s u re m e n t

P o in t

3 3 Ω

C P U T

S R C T

4 9 .9 Ω

2 p F

D O T 9 6 T

1 0 0 Ω D iffe re n tia l

M e a s u re m e n t

P o in t

3 3 Ω

C P U C

S R C C

2 p F

D O T 9 6 C

IR E F

4 9 .9 Ω

4 7 5 Ω

Figure 8. 0.7V Single-ended Load Configuration

3 .3 V s ig n a ls

T _{D C}

-

3 .3 V

2 .4 V

1 .5 V

0 .4 V

0 V

T _R

T _F

Figure 9. Single-ended Output Signals (for AC Parameters Measurement)

Document #: 38-07593 Rev. *C

Page 15 of 18

CY28410

Ordering Information

Part Number

Package Type

Product Flow

Standard

CY28410OC

CY28410OCT

CY28410ZC

CY28410ZCT

Lead-free (Planned)

CY28410OXC

CY28410OXCT

CY28410ZXC

CY28410ZXCT

56-pin SSOP

56-pin SSOP – Tape and Reel

56-pin TSSOP

Commercial, 0° to 70°C

56-pin TSSOP – Tape and Reel

56-pin SSOP

56-pin SSOP – Tape and Reel

56-pin TSSOP

Commercial, 0° to 70°C

56-pin TSSOP – Tape and Reel

Document #: 38-07593 Rev. *C

Page 16 of 18

CY28410

Package Drawing and Dimensions

56-lead Shrunk Small Outline Package O56

51-85062-*C

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56

0.249[0.009]

28

1

DIMENSIONS IN MM[INCHES] MIN.

MAX.

7.950[0.313]

8.255[0.325]

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.42gms

5.994[0.236]

6.198[0.244]

PART #

Z5624 STANDARD PKG.

ZZ5624 LEAD FREE PKG.

29

56

13.894[0.547]

14.097[0.555]

1.100[0.043]

MAX.

GAUGE PLANE

0.25[0.010]

0.20[0.008]

0.508[0.020]

0.762[0.030]

0.051[0.002]

0.152[0.006]

0.851[0.033]

0.950[0.037]

0.500[0.020]

BSC

0°-8°

0.100[0.003]

0.200[0.008]

0.170[0.006]

0.279[0.011]

SEATING

PLANE

51-85060-*C

Purchase of I²C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips

I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification

as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned

in this document are the trademarks of their respective holders.

Document #: 38-07593 Rev. *C

Page 17 of 18

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY28410

Document History Page

Document Title: CY28410 Clock Generator for Intel^Grantsdale Chipset

Document Number: 38-07593

Orig. of

REV.

**

*A

ECN NO. Issue Date Change

Description of Change

New Data Sheet

Corrected the frequency select table

130204

207740

12/24/03

See ECN

RGL

Corrected the V_{IH_FS}and V_{IL_FS}specs in the DC Electrical specs

Fixed the Single-ended Load Configuration diagram (Figure 8)

Corrected the ECN no. from 38-07595 to 130204

Corrected the Ordering Information entry for the PB free to match the

Devmaster

*B

*C

229399

270664

See ECN

RGL

Change the Long Term Accuracy spec in the 96MHz DOT clock from 300ppm

to 100ppm

Fixed the Single-ended Load Configuration

Fixed the AC table based on new char result

Removed all references to 166/333 and 400MHz CPU frequencies

Corrected a typo in the ordering information

Document #: 38-07593 Rev. *C

Page 18 of 18


型号：	CY28410OC
厂家：	CYPRESS
描述：	Clock Generator for Intel Grantsdale Chipset 时钟发生器为英特尔的Grantsdale芯片组晶体时钟发生器外围集成电路光电二极管
文件：	总18页 (文件大小：282K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY28410OC [CYPRESS]

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