CY284108ZXC_技术文档

CY284108

Clock Generator for Intel^®Blackford and Bayshore Chipsets

• Low-voltage frequency select input

Features

• I²C™ support with readback capabilities

• Compliant with Intel^CK410B

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• Supports Intel Pentium-4 and Xeon CPUs

• Selectable CPU frequencies

• 3.3V power supply

• Four differential CPU clock pairs

• Five 100 MHz Differential SRC clock pairs

• Two buffered Reference Clocks @ 14.31818 MHz

• One 48 MHz USB clock

• 56-pin SSOP and TSSOP packages

CPU

x 4

SRC

x5

PCI

x 7

REF

x 2

USB

x 1

• Seven 33 MHz PCI clocks

Block Diagram

Pin Configuration

VDD_REF

REF[0:1]

XIN

XTAL

OSC

XOUT

1

2

3

4

5

6

7

8

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PLL Ref Freq

VDD_PCI

VSS_PCI

PCI_0

FSC/TEST_SEL

REF0

VDD_CPU

REF1

CPUT[0:3], CPUC[0:3],

Divider

Network

CPU_STP#

PCI_STP#

PLL1

VDD_REF

X1

X2

VSS_REF

FSB/TEST_MODE

FS_A

VDD_CPU

CPUT0

CPUC0

VDD_CPU

CPUT1

PCI_1

PCI_2

PCI_3

VSS_PCI

VDD_PCI

PCIF_0

PCIF_1

PCIF_2

VDD_48

USB_48

VSS_48

VDD_SRC

SRCT0

SRCC0

SRCC1

SRCT1

VSS_SRC

SRCT2

SRCC2

SRCC3

SRCT3

VDD_SRC

SRCT4

SRCC4

VDD_SRC

SRCT[0:4], SRCC[0:4]

FS_[C:A]

VTT_PWRGD#

IREF

9

VDD_PCI

PCI[0:3]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VDD_PCIF

PCIF[0:2]

CPUC1

VSS_CPU

CPUT2

PD

VDD_48 MHz

USB_48

PLL2

CPUC2

VDD_CPU

CPUT3

CPUC3

VDDA

VSSA

IREF

NC

VTTPWRGD#**/PD

SDATA

SCLK

2

SDATA

SCLK

I C

Logic

........................ Document #: 38-07713 Rev. *B Page 1 of 16

400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669

www.silabs.com

CY284108

Pin Description

Name

X1

Pin Number

52

Type

I

Description

14.18 MHz crystal input

14.18 MHz crystal output

14.18 MHz reference clock

33 MHz clocks

X2

51

O, SE

O,SE

O, SE

O, DIF

REF[1:0]

PCI[3:0]

PCIF[2:0]

USB_48

CPU[T/C][3:0]

55, 54

6,5,4,3

11,10,9

13

33 MHz free running clock. Is not disabled via Software PCI_STOP.

Fixed 48 MHz USB clock output

37,36;40,39;

43,42;46,45

Differential CPU clock outputs

SRC[T/C][4:0]

FS_A

26,27;24,23;

21,22;19,18;

16,17

O, DIF

Differential serial reference clocks. SRC[T/C]4 is recommended for SATA.

48

I

3.3V-tolerant input for CPU frequency selection. Refer to DC Electrical

Specifications table for Vil_FS and Vih_FS specifications.

FS_B/TEST_MODE 49

3.3V-tolerant inputs for CPU frequency selection/selects REF/N or Hi-Z

when in test mode. Refer to DC Electrical Specifications table for Vil_FS and

Vih_FS specifications.

At VTTPWRGD# asserted low (see page 10 for diagram), this pin is sampled

to determine test mode functionality

0 = Hi-Z

1 = REF/N

FS_C/TEST_SEL

56

I

3.3V-tolerant inputs for CPU frequency selection/selects test mode if pulled

to 3.3V when VTT_PWRGD# is asserted low (seepage 10 for diagram).

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-

tions

IREF

33

31

I

A precision resistor is attached to this pin, which is connected to the internal

current reference

VTT_PWRGD#/PD

I, PD

DF3.3V LVTTL input is a level sensitive strobe used to latch the FS_A,

FS_B, FS_C/TEST_SELinputs.AfterVTT_PWRGD#(activelow)assertion,

this pin becomes a realtime input for asserting power down (active high).

See page 10 for diagram.

SCLK

29

I

SMBus-compatible SCLOCK

SMBus-compatible SDATA

3.3V power supply for outputs

Ground for outputs

SDATA

30

I/O

VDD_REF

VSS_REF

VDD_PCI

VSS_PCI

VDD_48

VSS_48

53

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

–

50

1,8

2,7

12

3.3V power supply for outputs

Ground for outputs

3.3V power supply for outputs

Differential CPU clock outputs

3.3V power supply for outputs

Ground for outputs

14

VDD_SRC

VSS_SRC

VDD_CPU

VSS_CPU

VDD_A

15,25,28

20

38,44,47

41

3.3V power supply for outputs

Ground for outputs

35

3.3V power supply for outputs

Ground for outputs

VSS_A

34

NC

32

No Connection

........................Document #: 38-07713 Rev. *B Page 2 of 16

CY284108

Table 1. CPU Frequency Select Tables

The registers associated with the Serial Data Interface

initialize to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Frequency Select Pins (FS_[C:A])

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A, FS_B, FS_C inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A, FS_B, and FS_C input values. For all logic

levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 2.

one-shot functionality in that once

a

valid low on

VTT_PWRGD# has been sampled, all further VTT_PWRGD#,

FS_A, FS_B, and FS_C transitions will be ignored, except in

test mode. FS_C is a three level input, when sampled at a

voltage greater than 2.0V by VTTPWRGD#, the device will

enter test mode as selected by the voltage level on the FS_B

input.

Serial Data Interface

The block write and block read protocol is outlined in Table 3

while Table 4 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

Table 2. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'

(6:0)

........................Document #: 38-07713 Rev. *B Page 3 of 16

CY284108

Table 3. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

Byte Count – 8 bits

20

(Skip this step if I²C_EN bit set)

28

36:29

37

Acknowledge from slave

Data byte 1 – 8 bits

27:21

28

Slave address – 7 bits

Read = 1

Acknowledge from slave

Data byte 2 – 8 bits

29

Acknowledge from slave

Byte Count from slave – 8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N –8 bits

....

46:39

47

Data byte 1 from slave – 8 bits

Acknowledge

....

Acknowledge from slave

Stop

55:48

56

Data byte 2 from slave – 8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave – 8 bits

NOT Acknowledge

....

Stop

Table 4. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Data byte – 8 bits

Acknowledge from slave

Stop

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

28

20

27:21

28

Slave address – 7 bits

Read

29

Acknowledge from slave

Data from slave – 8 bits

NOT Acknowledge

Stop

37:30

38

39

Control Registers

........................Document #: 38-07713 Rev. *B Page 4 of 16

CY284108

Byte 0: Control Register 0

Bit

7

@Pup

Name

Description

1

RESERVED

SRC[T/C]4

RESERVED

6

RESERVED

5

RESERVED

4

SRC[T/C]4 Output Enable

0 = Disable (Tri-state), 1 = Enable

3

2

1

0

1

SRC[T/C]3

SRC[T/C]2

SRC[T/C]1

SRC[T/C]0

SRC[T/C]3 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]2 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

1

REF1

REF1 Output Enable

0 = Disable, 1 = Enable

6

5

4

1

REF0

REF0 Output Enable

0 = Disable, 1 = Enable

CPU[T/C]3

CPU[T/C]2

CPU[T/C]3 Output Enable

0 = Disable (Tri-state), 1 = Enable

CPU[T/C]2 Output Enable

0 = Disable (Tri-state), 1 = Enable

3

2

1

RESERVED

CPU[T/C]1

RESERVED

CPU[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

1

0

1

0

CPU[T/C]0

CPU[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

CPU

SRC

PCIF

PCI

PLL1 Spread Spectrum Enable

0 = Spread off, 1 = Spread on

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

PCI3

PCI3 Output Enable

0 = Disable, 1 = Enable

6

5

4

3

2

1

PCI2

PCI1

PCI2 Output Enable

0 = Disable, 1 = Enable

PCI1 Output Enable

0 = Disable, 1 = Enable

PCI0

PCI0 Output Enable

0 = Disable, 1 = Enable

PCIF2

PCIF1

PCIF0

PCIF2 Output Enable

0 = Disable, 1 = Enable

PCIF1 Output Enable

0 = Disable, 1 = Enable

PCIF0 Output Enable

0 = Disable, 1 = Enable

........................Document #: 38-07713 Rev. *B Page 5 of 16

CY284108

Byte 2: Control Register 2 (continued)

Bit

@Pup

Name

Description

0

1

USB48

USB_48 Output Enable

0 = Disable, 1 = Enable

Byte 3: Control Register 3

Bit

@Pup

Name

7

0

PCIF2

Allow control of PCIF2 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

6

5

4

3

2

1

0

PCIF1

Allow control of PCIF1 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

PCIF0

Allow control of PCIF0 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with SW PCI_STP#

SRC[T/C]4

SRC[T/C]3

SRC[T/C]2

SRC[T/C]1

SRC[T/C]0

Allow control of SRC[T/C]4 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]3 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]2 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]1 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]0 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

0

CPU[T/C]3

CPU[T/C]3 PD drive mode

0 = Driven in power down, 1 = Tri-state

6

5

4

0

CPU[T/C]2

CPU[T/C]1

CPU[T/C]0

CPU[T/C]2 PD drive mode

0 = Driven in power down, 1 = Tri-state

CPU[T/C]1 PD drive mode

0 = Driven in power down, 1 = Tri-state

CPU[T/C]0 PD drive mode

0 = Driven in power down, 1 = Tri-state

3

2

1

0

RESERVED

Byte 5: Control Register 5

Bit

7

@Pup

Name

Description

0

RESERVED

6

SRC[T/C][4:0] PCI_STP# Stoppable SRC[T/C][4:0] drive mode upon PCI_STP# assertion

drive mode 0 = Driven in PCI_STOP#, 1 = Tri-state

5

0

SRC[T/C][4:0] PWRDWN SRC[T/C][4:0] PWRDWN drive mode

Drive mode

RESERVED

0 = Driven in power down, 1 = Tri-state

RESERVED, Set = 0

RESERVED

4

3

2

1

0

RESERVED

........................Document #: 38-07713 Rev. *B Page 6 of 16

CY284108

Byte 5: Control Register 5 (continued)

Bit

@Pup

Name

Description

0

RESERVED

Byte 6: Control Register 6

Bit

@Pup

Name

7

0

TEST_SEL

REF/N or Tri-state Select

0 = Tri-state, 1 = REF/N Clock

6

0

TEST_MODE

Test Clock Mode Entry Control

0 = Normal operation, 1 = REF/N or Tri-state mode

5

4

0

1

RESERVED

REF

RESERVED, Set = 0

REF Output Drive Strength

0 = Low, 1 = High

3

1

PCI_Stop Control

SW PCI_STP# Function

0 = SW PCI_STP# assert, 1 = SW PCI_STP# deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

2

1

0

HW

FS_C

FS_B

FS_A

FS_C Reflects the value of the FS_C pin sampled on power up

0 = FS_C was low during VTT_PWRGD# assertion

FS_B Reflects the value of the FS_B pin sampled on power up

0 = FS_B was low during VTT_PWRGD# assertion

FS_A Reflects the value of the FS_A pin sampled on power up

0 = FS_A was low during VTT_PWRGD# assertion

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

........................Document #: 38-07713 Rev. *B Page 7 of 16

CY284108

Table 5. Crystal Recommendations

Frequency

Drive

(max.)

Shunt Cap Motional

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

(Fund)

Cut

Loading Load Cap

(max.)

14.31818 MHz

AT

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

The CY284108 requires a parallel resonance crystal. Substi-

tuting a series resonance crystal will cause the CY284108 to

operate at the wrong frequency and violate the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

loading.

Clock Chip

Ci2

Ci1

3 to 6p

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

X2

X1

Cs2

Cs1

Trace

2.8 pF

Figure shows a typical crystal configuration using the two trim

capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It is a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

XTAL

Ce1

Ce2

Trim

33 pF

Figure 3. Crystal Loading Example

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Load Capacitance (each side)

Ce = 2 * CL – (Cs + Ci)

Total Capacitance (as seen by the crystal)

1

CLe

=

1

(

)

+

Ce2 + Cs2 + Ci2

Ce1 + Cs1 + Ci1

Figure 1. Crystal Capacitive Clarification

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Calculating Load Capacitors

Ce..................................................... External trim capacitors

Cs..............................................Stray capacitance (terraced)

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

PD (Power-down) Clarification

The VTT_PWRGD# /PD pin is a dual-function pin. During

initial power up, the pin functions as VTT_PWRGD#. Once

VTT_PWRGD# has been sampled low by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active HIGH input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD is also an asynchronous input for powering up the

system. When PD is asserted high, drive all clocks to a low

value and hold prior to turning off the VCOs and the crystal

oscillator.

calculated to provide equal capacitive loading on both sides.

Figure 2.

........................Document #: 38-07713 Rev. *B Page 8 of 16

CY284108

PD (Power-down) Assertion

power-on state, PD must be asserted high in less than 10 s

after asserting Vtt_PwrGd#.

When PD is sampled high by two consecutive rising edges of

CPUC, all single-ended outputs will be held low on their next

high to low transition and differential clocks must held high or

tri-stated (depending on the state of the control register drive

mode bit) on the next diff clock# high to low transition within 4

clock periods. When the SMBus PD drive mode bit corre-

sponding to the differential (CPU and SRC) clock output of

interest is programmed to ‘0’, the clock outputs are held with

“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state.

If the control register PD drive mode bit corresponding to the

output of interest is programmed to “1”, then both the “Diff

clock” and the “Diff clock#” are tri-state. Note that Figure 4

shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differ-

ential outputs. This diagram and description is applicable to

valid CPU frequencies 100, 133, 166, 200, 266, 333, and

400 MHz. In the event that PD mode is desired as the initial

PD Deassertion

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a three-state

condition resulting from power down will be driven high in less

than 300 s of PD deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs will be enabled within a few clock cycles of

each other. Figure 5 is an example showing the relationship of

clocks coming up.

PD

CPUT, 133 MHz

CPUC, 133 MHz

SRCT 100 MHz

SRCC 100 MHz

USB, 48 MHz

PCI, 33 MHz

REF

Figure 4. Power-down Assertion Timing Waveform

Tstable

<1.8 ms

PD

CPUT, 133 MHz

CPUC, 133 MHz

SRCT 100 MHz

SRCC 100 MHz

USB, 48 MHz

PCI, 33 MHz

REF

Tdrive_PWRDN#

<300 s, >200 mV

Figure 5. Power-down Deassertion Timing Waveform

........................Document #: 38-07713 Rev. *B Page 9 of 16

CY284108

FS_A, FS_B,FS_C

VTT_PWRGD#

PWRGD_VRM

0.2-0.3 ms

Delay

Wait for

VTT_PWRGD#

Device is not affected,

VTT_PWRGD# is ignored

Sample Sels

State 2

VDD Clock Gen

Clock State

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 6. VTT_PWRGD# Timing Diagram

S2

S1

VTT_PWRGD# = Low

Delay >

Sample

0.25 ms

Inputs straps

VDD_A = 2.0V

Wait for <1.8 ms

S0

S3

VDD_A = off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 7. Clock Generator Power-up/Run State Diagram

......................Document #: 38-07713 Rev. *B Page 10 of 16

CY284108

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Condition

Min.

–0.5

–65

0

Max.

4.6

Unit

V

V_{DD_A}

V_IN

Analog Supply Voltage

Input Voltage

4.6

V

Relative to V_SS

Non-functional

V_DD+ 0.5 VDC

T_S

Temperature, Storage

150

70

150

20

60

–

°C

T_A

Temperature, Operating Ambient Functional

T_J

Temperature, Junction

Functional

–

°C

Ø_JC

Dissipation, Junction to Case

Dissipation, Junction to Ambient

Mil-STD-883E Method 1012.1

JEDEC (JESD 51)

–

°C/W

V

Ø_JA

–

ESD_HBM

ESD Protection

MIL-STD-883, Method 3015

2000

(Human Body Model)

UL-94

MSL

Flammability Rating

At 1/8 in.

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

All VDDs

V_ILI2C

V_IHI2C

V_{IL_FS}

V_{IH_FS}

V_{IMFS_C}

V_{IH FS_C}

V_IL

Description

3.3V Operating Voltage

Input Low Voltage

Condition

Min.

Max.

Unit

V

3.3 ± 5%

3.135

3.465

SDATA, SCLK

–

1.0

V

Input High Voltage

2.2

–

V

FS_[A:B] Input Low Voltage

FS_[A:B] Input High Voltage

FS_C Mid Range

V_SS– 0.3

0.35

V

0.7

V_DD+ 0.5

V

0.7

2.0

V

FS_C High Range

2.0

V_DD+ 0.3

V

3.3V Input Low Voltage

3.3V Input High Voltage

Input Low Leakage Current

Input High Leakage Current

3.3V Output Low Voltage

3.3V Output High Voltage

High-impedance Output Current

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

V_SS– 0.3

0.8

V

V_IH

2.0

V_DD+ 0.3

V

I_IL

Except internal pull-up resistors, 0 < V_IN< V_DD

Except internal pull-down resistors, 0 < V_IN< V_DD

I_OL= 1 mA

–5

–

5

A

V

I_IH

–

V_OL

–

0.4

–

V_OH

I_OH= –1 mA

2.4

V

I_OZ

–10

10

A

pF

nH

V

C_IN

3

5

C_OUT

L_IN

3

6

–

7

V_XIH

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

500

70

V_XIL

Xin Low Voltage

0

–

V

I_DD3.3V

I_PD3.3V

I_PT3.3V

Dynamic Supply Current

Power-down Supply Current

At max. load and freq. per Figure 9

PD asserted, Outputs Driven

PD asserted, Outputs Tri-state

mA

12

...................... Document #: 38-07713 Rev. *B Page 11 of 16

CY284108

AC Electrical Specifications

Parameter

Crystal

T_DC

Description

Condition

Min.

Max.

Unit

XIN Duty Cycle

XIN Period

Thedevice willoperate reliably with input

dutycyclesupto30/70buttheREFclock

duty cycle will not be within specification

47.5

52.5

%

T_PERIOD

When XIN is driven from an external

clock source

69.841

71.0

ns

T_R/ T_F

T_CCJ

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Long-term Accuracy

Measured between 0.3V_DDand 0.7V_DD

As an average over 1-s duration

Over 150 ms

–

10.0

500

300

ns

ps

L_ACC

ppm

CPU at 0.7V

T_DC

CPUT and CPUC Duty Cycle

100-MHz CPUT and CPUC Period

133-MHz CPUT and CPUC Period

166-MHz CPUT and CPUC Period

200-MHz CPUT and CPUC Period

266-MHz CPUT and CPUC Period

333-MHz CPUT and CPUC Period

400-MHz CPUT and CPUC Period

CPU0 to CPU1

Measured at crossing point V_OX

45

55

%

T_PERIOD

T_SKEW

T_CCJ

9.997001 10.00300 ns

7.497751 7.502251 ns

5.998201 6.001801 ns

4.998500 5.001500 ns

3.748875 3.751125 ns

2.999100 3.000900 ns

2.499250 2.500750 ns

–

100

85

ps

CPUT/C Cycle to Cycle Jitter

Long Term Accuracy

L_ACC

Measured using frequency counter over

0.15seconds.

300

ppm

T_R/ T_F

T_RFM

CPUT and CPUC Rise and Fall Times MeasuredfromV_OL= 0.175 to V_OH= 0.525V

175

–

1100

20

ps

%

Rise/Fall Matching

Determined as a fraction of

2 * (T_R– T_F)/(T_R+ T_F)

T_R

Rise Time Variation

–

125

ps

mV

V

T_F

Fall Time Variation

125

V_HIGH

V_LOW

V_OX

Voltage High

Math averages Figure 9

660

–150

250

–

850

Voltage Low

–

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

550

V_OVS

V_UDS

V_RB

V_HIGH+ 0.3

–0.3

–

V

See Figure 9. Measure SE

0.2

V

SRC

T_DC

SRCT and SRCC Duty Cycle

100-MHz SRCT and SRCC Period

Any SRCT/C to SRCT/C Clock Skew

SRCT/C Cycle to Cycle Jitter

SRCT/C Long Term Accuracy

Measured at crossing point V_OX

45

55

%

T_PERIOD

T_SKEW

T_CCJ

L_ACC

T_R/ T_F

T_RFM

9.997001 10.00300 ns

–

250

125

300

1100

20

ps

–

ppm

ps

SRCT and SRCC Rise and Fall Times MeasuredfromV_OL= 0.175 to V_OH= 0.525V

175

–

Rise/Fall Matching

Determined as a fraction of

2 * (T_R– T_F)/(T_R+ T_F)

%

T_R

Rise TimeVariation

Fall Time Variation

Voltage High

–

125

850

ps

T_F

V_HIGH

Math averages Figure 9

660

mV

......................Document #: 38-07713 Rev. *B Page 12 of 16

CY284108

AC Electrical Specifications (continued)

Parameter

V_LOW

Description

Condition

Min.

–150

210

–

Max.

Unit

mV

V

Voltage Low

Math averages Figure 9

–

V_OX

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

550

V_OVS

V_HIGH+ 0.3

V_UDS

–0.3

–

V

V_RB

See Figure 9. Measure SE

0.2

V

PCI/PCIF

T_DC

PCI Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODSS

T_HIGH

T_LOW

Spread Disabled PCIF/PCI Period

29.99100 30.00900 ns

29.9910 30.15980 ns

Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

PCIF and PCI High Time

PCIF and PCI Low Time

PCI Edge Rates

Measurement at 2.4V

12.0

0.89

–

ns

Measurement at 0.4V

–

T_R/ T_F

T_SKEW

T_CCJ

Measured between 0.8V and 2.0V

4.0

585

500

V/ns

ps

Any PCI Clock to Any PCI clock Skew Measurement at 1.5V

PCIF and PCI Cycle to Cycle Jitter

Measurement at 1.5V

–

ps

USB48

T_DC

USB Duty Cycle

USB Period,

Measurement at 1.5V

45

55

%

T_PERIOD

Measurement at 1.5V, mean value over 20.8271

20.8396

ns

1 s

L_ACC

Long Accuracy

Measured at 1.5V using frequency

counter over 0.15s

–

100

ppm

T_HIGH

T_LOW

T_R/ T_F

T_CCJ

T_LTJ

USB High Time

USB Low Time

Measurement at 2.0V

8.094

7.694

1.0

–

11.000

4.0

ns

Measurement at 0.8V

USB Edge Rates

Cycle to Cycle Jitter

Long Term Jitter

Measured between 0.8V and 2.0V

Measurement taken @1.5V waveform

Measurement taken from cross point

V/ns

ps

350

–

650

ps

V

_OX@ 1 s

Measurement taken from cross point

_OX@ 10 s

Measurement taken from cross point

_OX@ 125 s

TLTJ

Long Term Jitter

–

1

ns

V

REF

T_DC

REF Duty Cycle

Measurement at 1.5V

45

69.827

0.55

–

55

69.855

4.0

ns

T_PERIOD

T_R/ T_F

T_CCJ

REF Period

Measurement at 1.5V

REF Edge Rates

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

REF Cycle to Cycle Jitter

REF Clock to Other REF Clock skew

1000

500

T_SKEW

Measurement at 1.5V

–

ps

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

–

1.8

ms

......................Document #: 38-07713 Rev. *B Page 13 of 16

CY284108

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

Figure 8 shows the test load configurations for the single-ended PCI, USB, and REF output signals.

Measurement

12

Point

60

5 pF

Measurement

Point

12

PCI/

USB

5 pF

Measurement

Point

5 pF

12

60

Measurement

Point

5 pF

Measurement

Point

5 pF

12

REF

60

Figure 8. Single-ended Load Configuration

For Differential CPU, SRC and DOT96 Output Signals

Figure 9 shows the test load configuration for the differential CPU and SRC outputs.

M e a s u re m e n t

3 3 

C P U T

S R C T

D O T 9 6 T

P o in t

2 p F

4 9 .9 

1 0 0  D iffe re n tia l

M e a su re m e n t

P o in t

C P U C

S R C C

D O T 9 6 C

IR E F

3 3 

4 9 .9 

4 7 5 

Figure 9. 0.7V Single-ended Load Configuration

3 .3 V s ig n a ls

T _{D C}

-

3 .3 V

2 .4 V

1 .5 V

0 .4 V

0 V

T _R

T _F

Figure 10. Single-ended Output Signals (for AC Parameters Measurement)

......................Document #: 38-07713 Rev. *B Page 14 of 16

CY284108

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

CY284108OXC

CY284108OXCT

CY284108ZXC

CY284108ZXCT

56-pin SSOP

Commercial, 0° to 85°C

56-pin SSOP – Tape and Reel

56-pin TSSOP

56-pin TSSOP – Tape and Reel

Package Diagrams

56-Lead Shrunk Small Outline Package O56

.020

28

1

0.395

0.420

0.292

0.299

DIMENSIONS IN INCHES MIN.

MAX.

29

56

0.720

0.730

SEATING PLANE

0.005

0.010

0.088

0.092

0.095

0.110

.010

GAUGE PLANE

0.110

0.024

0.040

0.025

BSC

0.008

0.016

0°-8°

0.008

0.0135

......................Document #: 38-07713 Rev. *B Page 15 of 16

CY284108

Package Diagrams (continued)

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z5624

NOTE :

1. JEDEC STD REF MO-153

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE

MIN.

3. DIMENSIONS IN MM. [INCHES]

MAX.

3. PACKAGE WEIGHT 0.42gms

0.249[0.009]

28

1

7.950[0.313]

8.255[0.325]

5.994[0.236]

6.198[0.244]

PART #

Z5624 STANDARD PKG.

ZZ5624 LEAD FREE PKG.

29

56

13.894[0.547]

14.097[0.555]

1.100[0.043]

MAX.

GAUGE PLANE

0.25[0.010]

0.20[0.008]

0.508[0.020]

0.762[0.030]

0.051[0.002]

0.152[0.006]

0.851[0.033]

0.950[0.037]

0.500[0.020]

BSC

0°-8°

0.100[0.003]

0.200[0.008]

0.170[0.006]

0.279[0.011]

SEATING

PLANE

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-

icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the

use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or

parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-

sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-

cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

......................Document #: 38-07713 Rev. *B Page 16 of 16


型号：	CY284108ZXC
厂家：	SILICON
描述：	Clock Generator, 400MHz, CMOS, PDSO56, 6 X 12 MM, LEAD FREE, TSSOP-56 时钟光电二极管外围集成电路晶体
文件：	总16页 (文件大小：148K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY284108ZXC [SILICON]

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