CXD1944R_技术文档

PRELIMINARY

CXD1944R

IEEE1394 3-port 200Mbps Cable Transceiver/Arbiter

Description

64 pin LQFP (plastic)

The CXD1944R is a PHY chip which supports

100/200Mbps speeds and performs cable interface and

bus arbitration. It conforms to the high performance seri-

al bus IEEE1394-1995 standard. The structure is 0.4µm

CMOS and it operates on a single 3.3V power supply.

Features

• Conforms to IEEE1394-1995

• Single 3.3V power supply

• Supports 100/200Mbps speeds

• Automatic power down for unused ports

• Power down mode to conserve energy

• Supports short reset operation

• Supports ping for optimization of a Gap_count

Operating Conditions

• Supply voltage

VDD

3.0 to 4.5

V

• Operating temperature Ta

–20 to +75

°C

Package

64-pin plastic LQFP (VQFP)

Absolute Maximum Ratings

• Supply voltage

• Input voltage

• Output voltage

VDD

–0.5 to +4.6

V

Applications

VI VSS –0.5 to VDD +0.5 V

VO VSS –0.5 to VDD +0.5 V

When used with a LINK chip (e.g. CXD1940R), allows

configuration of a high-speed digital serial interface.

• Operating temperature Ta

–20 to +70

°C

Structure

• Storage temperature

• Allowable power dissipation

PD

Tstg

–55 to +150

0.4µm CMOS monolithic IC

1000

mW

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication

or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony

cannot assume responsibility for any problems arising out of the use of these circuits.

–1–

PE96431–ST

CXD1944R

Block Diagram

CMC/LKON

PC0

TPA1+

TPA1–

PC1

PC2

TIO

Cable Port 1

TEST0

TEST1

TPB1+

TPB1–

Arbitration

and Control

State Machine

Logic

LDSEL

CPS

LPS

TPA2+

TPA2–

XISO

SYSCLK

LREQ

CTL0

CTL1

D0

Cable Port 2

Cable Port 3

Link

Interface

I/O

TPB2+

TPB2–

TPA3+

TPA3–

D1

TPB3+

TPB3–

D2

D3

TB1

TB2

TB3

R1

Received Data

Decoder and

Retimer

Voltage and

Current

Generator

R0

XI

XO

FLT

Crystal

Transmit Data

Encoder

Oscillator PLL

System and

Transmit Clock

Generator

XRESET

–2–

CXD1944R

Pin Configuration

1

2

XRESET

LPS

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

TB3

TB2

3

LREQ

VDD-IO

LDSEL

DVDD

PWD

DVSS

SYSCLK

DVSS

CTL0

CTL1

D0

TB1

4

TPA1+

TPA1–

TPB1+

TPB1–

AVSS

5

6

7

8

9

TPA2+

TPA2–

TPB2+

TPB2–

TPA3+

TPA3–

TPB3+

TPB3–

10

11

12

13

14

15

16

D1

D2

D3

–3–

CXD1944R

Pin Description

Pin No.

1

Symbol

I/O

I

Description

XRESET

Reset input. Asserts at LOW. A power-on reset signal can be generated by

adding a 0.1µF capacitor.

2

3

LPS

LREQ

VDD-IO

LDSEL

DVDD

PWD

DVSS

SYSCLK

DVDD

CTL0

CTL1

D0

I

LINK power supply status. LINK power supply is connected.

LINK request input.

4

Supply

I

IO power supply.

5

LINK delay select.

6

Supply

I

Digital circuit power supply.

7

Power down input.

8

Supply

OUT

Supply

I/O

Digital circuit ground.

9

System clock output; 49.152MHz clock to LINK.

Digital circuit power supply.

10

11

12

13

14

15

16

17

18

I/O of bidrectional control signals for LINK.

I/O of bidirectional data signals for LINK.

Connect to ground via 0.1µF capacitor when a 5V LINK is used.

I/O

D1

I/O

D2

I/O

D3

I/O

CAP

I

TIO

I/O

Connect to VSS or VDD. If then connected to VDD, short reset mode is

selected.

19

XSLOW

I

When XSLOW = LOW, a device acts as a 100M PHY. Normally connected

to VDD.

20

21

22

23

24

25

26

27

DVDD

TEST1

TEST0

CPS

Supply

I

Digital power supply.

Test mode control. Normally connected to ground.

Cable power status input. Normally connected to cable power.

Analog circuit power supply.

I

I(A)

AVDD

Supply

I/O

AVDD

Analog circuit power supply.

AVSS

Analog circuit power ground.

CMC/LKON

Configuration Manager Capable input, LINK ON clock (6MHz) output.

When LPS = LOW and a LinkOn packet is received, the 6MHz clock

signal continues to be output. Connect to VDD or VSS with a 10KΩ resister.

The configuration management function is indicated when connected to

VDD.

28

29

30

31

32

33

34

PC0

PC1

I

Power Class input (LSB).

Power Class input.

I

PC2

I

Power Class input (MSB).

Cable Not Active output. This output is debounced.

Analog circuit power ground.

Port3, Cable Pair B–.

CNA

O

AVSS

TPB3–

TPB3+

Supply

I/O(A)

Port3, Cable Pair B+.

–4–

CXD1944R

Pin No.

35

Symbol

TPA3–

TPA3+

TPB2–

TPB2+

TPA2–

TPA2+

AVSS

I/O

Description

I/O(A)

Supply

I/O(A)

O(A)

Port3, Cable Pair A–.

Port3, Cable Pair A+.

Port2, Cable Pair B–.

Port2, Cable Pair B+.

Port2, Cable Pair A–.

Port2, Cable Pair A+.

Analog circuit power ground.

Port1, Cable Pair B–.

Port1, Cable Pair B+.

Port1, Cable Pair A–.

Port1, Cable Pair A+.

36

37

38

39

40

41

42

TPB1–

TPB1+

TPA1–

TPA1+

TB1

43

44

45

46

Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power

down. Corresponds to one port.

47

48

TB2

TB3

O(A)

Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power

down. Corresponds to one port.

Tp bias output. Output 1.85V (typ.), and Hi-Z during chip reset and power

down. Corresponds to one port.

49

50

51

52

53

54

55

56

AVSS

Supply

O(A)

Analog circuit power ground.

Analog circuit power supply.

PLL circuit power ground.

PLL loop filter.

AVDD

PLLVSS

FLT

PLLVDD

XI

Supply

I(A)

PLL circuit power supply.

Crystal oscillator (24.576MHz±100ppm). The optimum values for the 100kΩ

resistor and 20pF capacitor.

57

XO

O(A)

Crystal oscillator (24.576MHz±100ppm). The optimum values for the 100kΩ

resistor and 20pF capacitor.

58

59

DVDD

R0

Supply

I(A)

Digital circuit power supply.

Reference resistance pin. Connect R1 and R0 with 6.8kΩ±5% resistor. R0

may be connected to ground.

60

R1

O(A)

Reference resistance pin. Connect R1 and R0 with 6.8kΩ±5% resistor. R0

may be connected to ground.

61

62

63

64

AVSS

XISO

AVSS

Supply

I

Analog circuit power ground.

XISO = LOW indicates isolation barrier which enables digital differentiator.

Analog circuit power ground.

Supply

Analog circuit power ground.

–5–

CXD1944R

Recommended Operating Conditions

Item

Symbol

VDD

Conditions

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

V

Supply voltage

High level input

Low level input

Differential input

Common input

VIH

XRESET, LPS, LREQ, CTL0

Cable input, 100Mbps

0.8VDD

V

VIL

0.2VDD

260

V

VID-100

VID-200

VID-ARB

VCM-100

142

132

mV

V

Cable input, 200Mbps

260

Cable input, Arbitration

171

260

TpB Cable input, 100Mbps or

speed signaling off

1.165

2.515

Common input

VCM-200

TpB Cable input, 200Mbps,

speed signaling on

0.935

2.515

V

Differential input jitter

Differential input skew

Differential input jitter

Differential input skew

JTT100

SKW100

JTT200

SKW200

IOH/IOL

Cable input, 100Mbps

±1.08

±0.80

±0.50

±0.55

ns

Between TpA and TpB, 100Mbps

Cable input, 200Mbps

ns

Between TpA and TpB, 200Mbps

ns

(1)

Output current

SYSCLK, CTL0, CTL1, D0, D1,

D2, D3, CMC/LKON

±12

mA

IO

TB1, TB2, TB3

–1.3

9.68

mA

Electrical Characteristics

Driver

Item

Symbol

Conditions

55Ω load

Driver on, speed signaling off –0.40

Min. Typ. Max.

Unit

Differential output voltage

VOD

ICM

172

265

0.22

–2.53

20

mV

mA

mV

(2)

Common mode current

(2)

Speed signal common mode current

ICM-SP 200Mbps speed signaling on –4.84

(2)

Common mode voltage when driver is off

VOFF

Driver off, speed signaling off

NOTES:

1. For output current, all source current is positive (+) and sink current is negative (–).

2. Common mode current is the average value of the currents output from TPB+ and TPB–. The same applies to TPA+ and TPA–.

–6–

CXD1944R

Receiver

Item

Symbol

Conditions

Driver off

Min.

–20

15

Typ.

Max.

20

Unit

µA

Common mode input current

Differential input impedance

IIC

ZID

Driver off

kΩ

24

30

pF

Differential input threshold

VTH

–30

168

–89

mV

Arbitration differential input threshold VTH+

“1” input

“Z” input

“0” input

VTHZ

VTH–

89

–168

131

Speed signal detection threshold

Cable bias detection threshold

VTH-SP

TB-TPA common mode

potential

49

VTH-CB

TPB common mode

input

0.6

1.0

V

–7–

CXD1944R

Device

Item

Symbol

IDD

Condition

Min.

Typ.

Max. Unit

Supply current

VDD = 3.6V

100

50

mA

V

VDD = 3.6V when cable is not connected

VDD = 3.6V, Power down mode

When a 5V LINK is used

IDD-PD

VDD-IO

10

I/O supply voltage

4.5

3.0

5.5

3.6

When a 3V LINK is used

V

High level output

Low level output

VOH

VOL

SYSCLK, CTL0, CTL1, D0, D1, D2, D3,

CMC/LKON, IOH = 12mA, VDD = min.

VDD–0.4

V

SYSCLK, CTL0, CTL1, D0, D1, D2, D3,

CMC/LKON, IOL = 12mA, VDD = max.

0.4

V

High level input threshold VTH+

Low level input threshold VTH–

XRESET, LPS, LREQ, PWD, CTL0, CTL1,

D0, D1, D2, D3

0.6VDD

XRESET, LPS, LREQ, PWD, CTL0, CTL1,

D0, D1, D2, D3

0.4VDD

±10

V

Input leak current

IIL

XRESET, LPS, LREQ, PWD, CTL0, CTL1,

D0, D1, D2, D3, VI = 0V or VDD

µA

Output leak current

when output is off

IOZ

SYSCLK, CTL0, CTL1, D0, D1, D2, D3,

CMC/LKON

±40

Power up reset time

CPS input threshold

CPS input current

TB output voltage

R1 pin output voltage

TPWR

2

ms

V

VTH-CPS 200kΩ resistor

5.5

7.5

30

ICPS

VO

CPS pin at 1.85V

20

µA

V

1.665

0.635

2.015

0.761

VR1

IR1 = 100µA

V

–8–

CXD1944R

I/O Pin Capacitance

Item

Symbol

CIN

Conditions

Min.

Typ.

Max.

11

Unit

pF

Input pin capacitance

Output pin capacitance

XRESET, LPS, LREQ, PC0, PC1, PC2, CPS

COUT SYSCLK

11

pF

Input/Output capacitance CI/O

CTL0, CTL1, D0, D1, D2, D3, CMC/LKON

11

pF

AC Characteristics

Item

Output jitter

Symbol

JTT

SKW

Tr

Conditions

TPA, TPB

Min.

Typ.

Max.

±0.25

±0.15

2.2

Unit

ns

Output skew

Output rise time

Output fall time

Setup time

Between TPA and TPB

ns

TPA, TPB, 10 to 90%, RL = 55Ω, CL = 10pF

TPA, TPB, 90 to 10%, RL = 55Ω, CL = 10pF

ns

Tf

2.2

ns

Tsu

LREQ, CTL0, CTL1, D0, D1, D2, D3 relative

to SYSCLK, LDSEL = HIGH

5

0

2

7

ns

LREQ, CTL0, CTL1, D0, D1, D2, D3

relative to SYSCLK, LDSEL = LOW

ns

Hold time

Thd

LREQ, CTL0, CTL1, D0, D1, D2, D3

relative to SYSCLK, LDSEL = HIGH

LREQ, CTL0, CTL1, D0, D1, D2, D3

relative to SYSCLK, LDSEL = LOW

Output delay time

Td

CTL0, CTL1, D0, D1, D2, D3 from SYSCLK

2.5

1.5

11

ns

(1)

Output disable time

Thz

0.0

NOTE:

1. When control of CTL0, CTL1 and D0 to 3 passes from PHY to LINK. Refer to the section on Transmit.

–9–

CXD1944R

Switching Waveforms

SysCLK

tsu

thd

LReq,

Ctl,

Data

LReq, Ctl, Data setup time and hold time

SysCLK

td

Ctl, Data

SysCLK

tHZ

Hi-Z

Ctl, Data

Ctl, Data Output Delay

Internal Register

MSB

0

LSB

Address

0000

0001

0010

0011

0100

0101

1

2

3

4

5

6

7

Physical-ID

R

CPS

RHB

IBR

GC

SPD = 01

0

NP = 00011

Con1

Con2

Con3

0

ASTAT1

ASTAT2

ASTAT3

BSTAT1

BSTAT2

BSTAT3

Ch1

Ch2

Ch3

0

P1Fast

P2Fast

P3Fast

0

0110

0111

1000

1001

1010

1011

LoopInt CPStatInt

CPStat

IDidIt Illegal LReq

Reserved

Chip Rev

Reserved

0

Slow Pin Slow Bit ArbRstReq

Ping Timer [15 : 8]

Ping Timer [7 : 0]

–10–

CXD1944R

Name

Physical-ID

R

Size

Type

R

Description

The address number of this node. Determined during Self-ID.

Indicates that this node is the root.

6

1

R

CPS

R

Cable power status.

RHB

R/W

Root Holding Bit. Attempts to become the root during next bus reset if set to “1”.

IBR

Initiate Bus Reset. Generates bus reset when possible after being set to “1”.

Cleared after bus reset.

GC

6

2

4

2

R/W

R

Gap Count. Used to optimize gap time according to bus scale.

Indicates this node’s highest speed; 200Mbps when “01”, 100Mbps when “00”.

Indicates the number of ports on this node.

SPD

NP

R

ASTAT(n)

R

Indicates port n TPA status.

11 = Z, 01 = 1, 10 = 0, 00 = invalid

BSTAT(n)

2

R

Indicates port n TPB status.

11 = Z, 01 = 1, 10 = 0, 00 = invalid

Ch(n)

1

R

When the value is “1”, indicates that port n is the Child. “0” indicates Parent.

When the value is “1”, indicates that the active cable is connected to port n.

When the value is “1”, indicates that port n supports 200Mbps.

Con(n)

P(n) Fast

LoopInt

R

R/W

This is set to “1” when Tree-ID is not completed in time, which means that the

bus may be forming a loop.

CPStatInt

CPStat

IDidIt

1

R/W

R

Indicates a drop in cable power line voltage.

Same as CPS.

R

Indicates that this node generates the last bus reset. More than one node

may set this value.

IllegalReq

ChipRev

1

4

R

Indicates an illegal LReq is detected.

Indicates the chip revision number.

Slow Pin

Slow Bit

1

R

Indicates XSLOW pin is set to LOW.

1

R/W

R

When set to “1”, the node acts as a 100Mbps PHY. Default is “0”.

Initiate the arbitrated bus reset. Cleared after bus reset.

ArbRstReq

Ping Timer

1

16

50MHz Ping Timer count. A count starts when a configuration packet is trans-

mitted and stops when the first packet is received. The value may not be cleared

until the next configuration packet is sent.

–11–

CXD1944R

External Components and Pin Connection

220pF

2.4kΩ

20pF

6.6kΩ

20pF

100kΩ

/ISO

VDD

XRESET

LPS

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

TPB3

TPB2

0.1µF

Tp Bias

LINK VDD

10kΩ

LREQ

VDD-IO

LDSEL

DVDD

PWD

DVSS

SYSCLK

DVSS

CTL0

CTL1

D0

3

TPB1

4

TPB1+

TPA1–

TPB1+

TPB1–

AVSS

LDSEL

5

Tp Cables

VDD

6

Power

Down

7

8

9

TPA2+

TPA2–

TPB2+

TPB2–

TPA3+

TPA3–

TPB3+

TPB3–

10

11

12

13

14

15

16

LINK Controller

Interface

Tp Cables

D1

D2

D3

0.1µF

Power Class

Programming

200kΩ

VDO

VDD

10kΩ

Cable Power

/SLOW

CNA Out

Link On Configuration

–12–

CXD1944R

Twisted Pair Cable Connection

CPS

Power pair

200kΩ

TPAn+

TPAn–

Cable pair A

Cable pair B

55Ω

Cable Port (n)

TPBn+

TPBn–

TPBSn

55Ω

0.33µF

250pF

5kΩ

request operation to read or write an internal PHY regis-

ter or to ask the PHY to initiate a transmit action. The

PHY initiates a receive action whenever a packet is

received from the serial bus.

Description of Operation

The CXD1994R is used with LINK controllers such as

the CXD1940R to configure a high speed serial bus. It

has three ports which support speeds of 100M/200Mbps.

There are four basic operations which may occur in

the interface: request, status, transmit, and receive. All

bit request are initiated by the PHY. The LINK uses the

The serial bus is always 2 bits wide, independent of

speed.

The encoding of these pins is as follows:

CTL [0 : 1] When PHY is Driving

CTL [0: 1]

Name

Idle

Meaning

00

01

10

11

No activity.

Status

The PHY is sending status information to the LINK.

An incoming packet is being transferred from the PHY to the LINK.

The LINK is granted the bus to send a packet.

Receive

Transmit

CTL [0 : 1] When the LINK is Driving (upon a grant from PHY)

CTL [0: 1]

Name

Idle

Meaning

Transmission complete, release bus.

00

01

Hold

The LINK is holding the bus while preparing data or indicating it wishes to

reacquire the bus without arbitration to send another packet.

10

11

Transmit

The LINK is sending a packet to the PHY.

Unused.

Reserved

–13–

CXD1944R

LINK Request

transfer can be either 7 bits, 9 bits or 17 bits, depending

on whether it is a bus request, a read access, or a write

access, repectively. A stop bit of 0 is required after each

request transfer before another transfer may begin.

To request the bus or access a PHY register, the LINK

sends a short stream to the PHY on the LREQ pin. The

information sent includes the type of request to which the

packet is to be sent, or a read or write command. The

Bus Request Format

Bit(s)

0

Name

Start Bit

Description

Indicates start of transfer. Always 1.

1 to 3

Request Type

Indicates which type of bus request is being performed. See the table below

for the encoding of this field.

4 to 5

6

Request Speed

The speed at which the PHY will be sending the packet for this request. This

field has the same encoding as the speed code from the first symbol of the

receive packet. See the following table for the encoding of this field.

Stop Bit

Indicates end of transfer. Always 0.

If the transfer is a read request, it is 9 bits long and

has the following format:

Read Request Format

Bit(s)

0

Name

Start Bit

Description

Indicates start of transfer. Always 1.

1 to 3

Request Type

Indicates that this is a register read. See the following table for the encoding of

this field.

4 to 7

8

Address

Stop Bit

The internal PHY register address to be read.

Indicates end of transfer. Always 0.

If the transfer is a write request, it is 17 bits long and

has the following format:

Write Request Format

Bit(s)

0

Name

Start Bit

Description

Indicates start of transfer. Always 1.

1 to 3

Request Type

Indicates that this is a register read. See the following table for the encoding

of this field.

4 to 7

Address

The internal PHY register address to be written.

The data to be written to the specified address.

Indicates end of transfer. Always 0.

8 to 15 Data

16 Stop Bit

–14–

CXD1944R

The request type field is encoded as follows:

Request Type Field

LREQ [1 : 3]

000

Name

Meaning

ImmReq

Take control of the bus immediately upon detecting idle; do not arbitrate. Used

for acknowledge transfers.

001

010

IsoReq

PriReq

Arbitrate for the bus; no gaps. Used for isochronous transfers.

Arbitrate after a subaction gap; ignore fair protocol. Used for cycle start

packet.

011

FairReq

RdReq

Arbitrate after a subaction gap, following fair prototcol. Used for fair transfers.

Return specified register contents through status transfer.

Write to specified register.

100

101

WrReg

110 to 111

Reserved

Ignored.

The request speed field is encoded as follows:

Request Speed Field

LREQ [4 : 5]

Data Rate

100Mbps

200Mbps

400Mbps

>400Mbps

00

01

10

11

NOTE:

The CXD1944R does not support 400Mbps and over.

–15–

CXD1944R

LREQ Timing

LR (n – 1)

LR1

LR (n – 2)

LR0

LR2

LR3

FairReq and PrioReq:

cause a temporary, localized collision of the data-on line

states somewhere between two PHYs intending to

acknowledge. All other PHYs on the bus would see the

data-on state. This collision would appear as a “zz” line

state, and would not be interpreted as a bus reset. The

mistaken node would drops its request as soon as it has

checked the CRC and spurious “zz” line states would go

away. The only side effect of such a collision would be

the loss of the intended acknowledge packet, which

would be handled by the higher-layer protocol.

To request the bus for fair or priority access, the LINK

sends the request at least one clock after the interface

becomes idle. The LINK interprets the receive state on

the CTL pins as a lost request. If the LINK sees the

receive state anytime during or after it sends the request

transfer, it assumes the request is lost and reissues the

request on the next idle. The PHY will ignore a fair or pri-

ority request if it asserts the receive state anytime during

the request transfer. Note that the minimum length of a

packet is two clock cycles in the case of 400Mbps

acknowledge packet. The minimum request packet is 8

clock cycles. It is important that the LINK and PHY agree

to interpret a lost request the same way.

IsoReq:

To send an isochronous packet, the LINK is recom-

mended to issue an IsoReq request during the reception

or transmission (if root) of a cycle start packet or another

isochronous packet. This is required to keep an isochro-

nous gap short. Any IsoReq will be cleared when a pack-

et is transmitted or a certain time (80ns) is passed in idle

after the bus seized. (This timeout is not a part of the

IEEE1394-1995 standard.) When the LINK issues an

IsoReq before CRC check of a cycle start packet and the

CRC is found wrong after the IsoReq, the LINK may

release the bus without sending a packet when the bus is

granted.

The cycle master node uses a priority request

(PriReq) to send the cycle start message. To request the

bus to send isochronous data, the LINK can issue the

request at any time after receiving the cycle start. The

PHY will clear an isochronous request only when the bus

has been won.

ImmReq:

To send an acknowledge, the LINK must issue an

ImmReq request during the reception of the packet

addressed to it. This is required because the delay from

end of packet to acknowledge request adds directly to

the minimum delay every PHY must wait after every

packet to allow an acknowledge to occur. After the pack-

et ends, the PHY immediately takes control of the bus

and grants the bus to the LINK. If the header CRC of the

packet turns out to be bad, the LINK releases the bus

immediately. The LINK cannot use this grant to send

another type of packet. To ensure this, the LINK must

wait 160ns after the end of the received packet to allow

the PHY to grant it the bus for the acknowledge, then

release the bus and proceed with another request.

Though highly unlikely, it is conceivable that two dif-

ferent nodes can perceive (one correctly, one mistaken-

ly) that an incoming packet is intended for them and both

issue an acknowledge request before checking the CRC.

Both nodes’ PHYs would grab control of the bus immedi-

ately after the packet is complete. This condition will

Read/Write Request:

For write requests, the PHY takes the value in the data

field of the transfer and loads it into the addressed regis-

ter as soon as the transfer is complete. For read

requests, the PHY returns the contents of the addressed

register at the next opportunity through a status transfer.

The LINK is allowed to perform a read or write operation

at any time. If the status transfer is interrupted by an

incoming packet, the PHY continues to attempt the trans-

fer of the requested register until it is successful.

Once the LINK issues a request for access to the bus

(immediate, iso, fair, or priority) it cannot issue another

request until the PHY indicates “lost” (incoming packet)

or “won” (transmit). The PHY ignores new requests while

a previous request is pending.

–16–

CXD1944R

Status Transfer

tion of the status transfer.The PHY may prematurely end

a status transfer by asserting something other than sta-

tus on the CTL pins. This should be done in the event

that a packet arrives before the status transfer com-

pletes. There must be at least one cycle in between con-

secutive status transfers.

When the PHY has status information to transfer to

the LINK, it will initiate a status transfer.The PHY will wait

until the interface is idle to perform the transfer. The PHY

initiates the transfer by asserting status (01b) on the CTL

pins, along with the first two bits of status information on

D [0 : 1]. The PHY maintains CTL = status for the dura-

Status Transfer Timing

PHY

CTL [0:1]

00

01

00

PHY

D [0:1]

s[0:1]

s[2:3]

s[14:15]

–17–

CXD1944R

Transmit:

When the LINK requests access to the serial bus

during a single cycle. The only requirement when send-

ing multiple packets during a single bus ownership is that

all must be transmitted at the same speed, since the

speed of the packet transmission is set before the first

packet.

through the LREQ pin, the PHY arbitrates for access to

the serial bus. If the PHY wins the arbitration, it grants the

bus to the LINK by asserting transmit on the CTL pin for

one SCLK cycle, followed by idle for one cycle. After

sampling the transmit state from the PHY, the LINK takes

over control of the interface by asserting either hold or

transmit on the CTL pins. The LINK asserts hold to keep

ownership of the bus while preparing data. The PHY

asserts the data-on state on the serial bus during this

time. When it is ready to begin transmitting a packet, the

LINK asserts transmit on the CTL pins along with the first

bits of the packet. After sending the last bits of the pack-

et, the link asserts either idle or hold on the on the CTL

pins for one cycle, and then idle for one additional cycle

before tristating those pins.

As noted above, when the LINK has finished sending

the last packet for the current bus ownership, it releases

the bus by asserting idle on the CTL pins for two SCLK

cycles. The PHY begins asserting idle on the CTL pins

one clock after sampling idle from the link. Note that

whenever the D and CTL lines change “ownership”

between the PHY and the LINK, there is an extra clock

period allowed so that both sides of the interface can

operate on registered versions of the interface signals,

rather than having to respond to a CTL state on the next

cycle.

Note that it is not required that the LINK enter the hold

state before sending the first packet if implementation

permits the LINK to be ready to transmit as soon as bus

ownership is granted. The timing for a single packet

transmit operation is shown below. In the diagram, D0

through Dn are the data symbols of the packet; zz repre-

sents high impedance state.

The hold state here indicates to the PHY that the LINK

needs to send another packet without releasing the bus.

The PHY responds to this hold state by waiting the

required minimum time and then asserting transmit as

before. This function would be used after sending an

acknowledge if the LINK intends to send a unified

response, or to send consecutive isochronous packets

Transmit Timing

Single Packet

PHY

zz

00

zz

00

zz

11

00

zz

00

CTL [0:1]

PHY

D [0:1]

00

LINK

CTL [0:1]

01

00

zz

01

00

10

00

zz

10

00

zz

10

zz

LINK

D [0:1]

D0

Dn

D2

D1

Continued Packet

PHY

zz

00

11

00

zz

00

zz

CTL [0:1]

PHY

D [0:1]

zz

LINK

CTL [0:1]

00

10

zz

01

00

10

zz

01

00

01

00

zz

10

LINK

D [0:1]

D1

Dn–1

Dn

D0

NOTES:

zz = Hi-Z

D0 to Dn = Packet data

This figure is for 100Mbps. For 200Mbps, D [0:3] is used.

–18–

CXD1944R

is a PHY-LINK protocol and is not included in the calcula-

tion of the CRC or other data protection mechanisms.

It is possible that a PHY can see date-on appear and

then disappear on the serial bus without seeing a packet.

This is the case when a packet of a higher speed than the

PHY can receive is being transmitted. In this case, the

PHY will end the packet by asserting idle when the data-

on state goes away.

Receive:

Whenever the PHY sees the “data-on” state on the

serial bus, it initiates a receive operation by asserting

receive on the CTL pins and “1” on each of the D pins.

The PHY indicates the start of a packet by placing the

speed code (encoding shown below) on the D pins, fol-

lowed by the contents of the packet, holding the CTL pins

in receive until the last symbol of the packet has been

transferred. The PHY indicates the end of the packet by

asserting idle on the CTL pins. Note that the speed code

If the PHY is capable of a higher data rate than the

LINK, the LINK detects the speed code as such and

ignores the packet until it sees the idle state again.

Receive Timing

PHY

CTL [0:1]

00

10

F

10

F

10

00

0

00

0

PHY

D [0:3]

(hex)

0

SPD

D0

D1

Dn

NOTES:

SPD = speed code

D0 to Dn = data symbols of the packet; for 100Mbps, packet data is output to D [0 : 1] only.

The speed code for the receive operation is defined

as follows:

Receive Speed Code

D[0 : 3]

00xx

Data Rate

100Mbps

200Mbps

0100

NOTE:

The “xx” means transmitted as 00, ignored on receive.

–19–

CXD1944R

Power Class Programming

Power use or power supply from the cable requires

certain settings. PC [2 : 0] is used for this setting.

The power classes are defined as follows:

PC [2 : 0]

Definition

000

001

010

011

100

101

The node does not consume cable power. Also, power does not repeat.

The node operates on its own power, and a minimum of 15W is supplied to the cable.

The node operates on its own power, and a minimum of 30W is supplied to the cable.

The node operates on its own power and a minimum of 45W is supplied to the cable.

The node may use cable power. Maximum required power is 1W.

The node may use cable power. Maximum required power is 1W. A further 2W are required to

operate LINK and upper layer.

110

111

The node may use cable power. Maximum required power is 1W. A further 5W are required to

operate LINK and upper layer.

The node may use cable power. Maximum required power is 1W. A further 9W are required to

operate LINK and upper layer.

Additional Features

Short Bus Reset:

Slow Mode:

The CXD1944R supports 200Mbps. In some cable

environments, however, 200Mbps may be difficult to

The short bus reset or arbitrated bus reset were pro-

posed in the 1394 Trade Association by Apple Computer.

The standardization, however, has not been done yet.

The CXD1944R supports a short bus reset mode whose

reset pulse width is 1.4µs instead of the normal bus reset

pulse width of 166µs. This mode can be selected by con-

necting the TIO pin to VDD.When the node needs to send

a reset pulse, it will first arbitrate the bus according to the

fair protocol as a FairReq. If it gets the bus grant, it will

send a short bus reset pulse instead of a packet. This is

called “arbitrated bus reset”, which ensures all nodes can

detect the short bus reset pulse. Since it follows Fair pro-

tocol, it won’t disturb the isochronous cycle. This arbitrat-

ed bus reset can only work after the bus is initialized.

Before the bus initialization, the node will send a short

bus reset pulse immediately. In both cases, if a short bus

reset fails, the node will send a normal long bus reset, so

that the short bus reset mode can be used with an older

PHY which does not support a short bus reset mode.

If the IBR bit of the internal PHY register is set to 1, the

device will send a long reset pulse. To request a short

arbitrated bus reset, write 1 to the ArbRsrReq bit in the

reset mode.

operate; thus we have added the Slow Mode operation.

By connecting XSLOW pin to ground, or writing a “1” to

the Slow Bit of the internal PHY register, the device will

act as a 100Mbps PHY. D[2:3] is still active in the slow

mode.

Ping and Ping Timer:

Ping is used to measure a node-node packet delay. If

the node received an R=0 and T=0 configuration packet,

it will send a Self-ID packet immediately as an acknowl-

edge. Since a LINK is not involved in this Self-ID trans-

mission, and it is very quick, a sender can know the exact

packet delay between the node and the remote node.

LINK can read a Ping timer count after a Self-ID acknowl-

edge. The Ping timer will be cleared and starts a count

only when a configuration packet is sent from the node.

The counter runs at 50MHz clock cycle. This feature is

thought useful to optimize a gap count of the bus.

–20–

CXD1944R

Package Outline

Unit: mm

64 pin LQFP (Plastic)

12.0 ±0.2

10.0 ±0.1

+0.05

0.127

–0.02

*

0.1

48

33

49

32

64

17

(0.22)

1

16

0.18 ⁺–⁰0.^.0⁰3⁸

1.5 ⁺–0⁰.^.1²

0.5 ±0.08

0.1 ±0.1

0°-10°

NOTE: Dimension “*” does not include mold protrusion.

Package Structure

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY/PHENOL RESIN

SOLDER PLATING

42 ALLOY

SONY CODE

EIAJ CODE

LQFP-64P-L01

*QFP064-P-1010-A

—

JEDEC CODE

PACKAGE WEIGHT

0.3g

–21–


型号：	CXD1944R
厂家：	SONY CORPORATION
描述：	IEEE1394 3-port 200Mbps Cable Transceiver/Arbiter 200Mbps的IEEE1394 3端口电缆收发器/仲裁器
文件：	总21页 (文件大小：185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD1944R [SONY]

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