SL74HC373 [SLS]
Octal 3-State Noninverting Transparent Latch; 八路三态同相透明锁存器
| 型号： | SL74HC373 |
| 厂家： | 
SYSTEM LOGIC SEMICONDUCTOR |
| 描述： | Octal 3-State Noninverting Transparent Latch |
| 文件： | 总5页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL74HC373
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The SL74HC373 is identical in pinout to the LS/ALS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches,
but when Output Enable is high, all device outputs are forced to the
high-impedance state. Thus, data may be latched even when the
outputs are not enabled.
ORDERING INFORMATION
SL74HC373N Plastic
SL74HC373D SOIC
TA = -55° to 125° C for all packages
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Q
PIN 20=VCC
PIN 10 = GND
Output
Enable
Latch
D
Enable
L
L
L
H
H
H
L
H
L
H
L
No Change
Z
X
X
X
X = Don’t Care
Z = High Impedance
System Logic
Semiconductor
SLS
SL74HC373
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
VCC
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
-0.5 to +7.0
V
IN
-1.5 to VCC +1.5
V
V
VOUT
IIN
-0.5 to VCC +0.5
±20
±35
±75
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V , VOUT
IN
VCC
V
TA
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range
IN
GND£(V or VOUT)£VCC.
IN
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
System Logic
SLS
Semiconductor
SL74HC373
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
25 °C
to
£85
°C
£125
°C
Unit
V
-55°C
V
IH
Minimum High-Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
êIOUTê£ 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
IL
Maximum Low -Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
êIOUTê £ 20 mA
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
VOH
Minimum High-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
IN
IH
V =V or V
IL
IN
IH
êIOUTê £ 6.0 mA
êIOUTê £ 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level
Output Voltage
V = V or V
IH
êIOUTê £ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IL
V = V or V
IH
IN
IL
êIOUTê £ 6.0 mA
êIOUTê £ 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
V =VCC or GND
6.0
±0.1
±1.0
±1.0
mA
mA
IN
IOZ
Maximum Three-State Output in High-Impedance
6.0
±0.5
±5.0
±10
Leakage Current
State
V = V or V
IH
IN
IL
VOUT=VCC or GND
ICC
Maximum Quiescent
Supply Current
(per Package)
V =VCC or GND
IOUT=0mA
6.0
4.0
40
160
mA
IN
System Logic
Semiconductor
SLS
SL74HC373
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
ns
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
125
25
155
31
190
38
32
21
26
tPLH, tPHL Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
ns
ns
ns
tPLZ, tPHZ Maximum Propagation Delay ,Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tPZL, tPZH Maximum Propagation Delay , Output Enable to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
36
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tSU
Parameter
V
25 °C to
-55°C
£85°C
£125°C
Unit
Minimum Setup Time, Input D
to Latch Enable
2.0
4.5
6.0
25
5.0
5.0
30
6.0
6.0
40
8.0
7.0
ns
ns
ns
ns
(Figure 4)
th
Minimum Hold Time,Latch
Enable to Input D
(Figure 4)
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
tw
Minimum Pulse Width, Latch
Enable (Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
Semiconductor
SLS
SL74HC373
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
EXPANDED LOGIC DIAGRAM
System Logic
Semiconductor
SLS
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