SL74HC374N [SLS]

Octal 3-State Noninverting D Flip-Flop; 八路三态非反相D触发器
SL74HC374N
型号: SL74HC374N
厂家: SYSTEM LOGIC SEMICONDUCTOR    SYSTEM LOGIC SEMICONDUCTOR
描述:

Octal 3-State Noninverting D Flip-Flop
八路三态非反相D触发器

触发器
文件: 总5页 (文件大小:56K)
中文:  中文翻译
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SL74HC374  
Octal 3-State Noninverting D Flip-Flop  
High-Performance Silicon-Gate CMOS  
The SL74HC374 is identical in pinout to the LS/ALS374. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LS/ALSTTL outputs.  
Data meeting the setup and hold time is clocked to the outputs with  
the rising edge of the Clock. The Output Enable input does not affect  
the states of the flip-flops, but when Output Enable is high, the  
outputs are forced to the high-impedance state; thus, data may be  
stored even when the outputs are not enabled.  
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 mA  
ORDERING INFORMATION  
SL74HC374N Plastic  
SL74HC374D SOIC  
TA = -55° to 125° C for all packages  
High Noise Immunity Characteristic of CMOS Devices  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
FUNCTION TABLE  
PIN 20=VCC  
PIN 10 = GND  
Inputs  
Clock  
Output  
Q
Output  
Enable  
D
L
L
L
H
L
H
L
L,H,  
X
no  
change  
H
X
X
Z
X = don’t care  
Z = high impedance  
System Logic  
Semiconductor  
SLS  
SL74HC374  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
VCC  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage (Referenced to GND)  
DC Output Voltage (Referenced to GND)  
DC Input Current, per Pin  
-0.5 to +7.0  
V
IN  
-1.5 to VCC +1.5  
V
V
VOUT  
IIN  
-0.5 to VCC +0.5  
±20  
±35  
±75  
mA  
mA  
mA  
mW  
IOUT  
ICC  
DC Output Current, per Pin  
DC Supply Current, VCC and GND Pins  
PD  
Power Dissipation in Still Air, Plastic DIP+  
SOIC Package+  
750  
500  
Tstg  
TL  
Storage Temperature  
-65 to +150  
260  
°C  
°C  
Lead Temperature, 1 mm from Case for 10 Seconds  
(Plastic DIP or SOIC Package)  
*Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation should be restricted to the Recommended Operating Conditions.  
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C  
SOIC Package: : - 7 mW/°C from 65° to 125°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
VCC  
Parameter  
Min  
2.0  
0
Max  
6.0  
Unit  
DC Supply Voltage (Referenced to GND)  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
V
V
V , VOUT  
IN  
VCC  
TA  
-55  
+125  
°C  
ns  
tr, tf  
Input Rise and Fall Time (Figure 1)  
VCC =2.0 V  
VCC =4.5 V  
VCC =6.0 V  
0
0
0
1000  
500  
400  
This device contains protection circuitry to guard against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range  
IN  
GND£(V or VOUT)£VCC.  
IN  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).  
CC  
Unused outputs must be left open.  
System Logic  
SLS  
Semiconductor  
SL74HC374  
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)  
VCC  
V
Guaranteed Limit  
Symbol  
Parameter  
Test Conditions  
25 °C  
to  
£85  
°C  
£125  
°C  
Unit  
V
-55°C  
V
IH  
Minimum High-Level  
Input Voltage  
VOUT=0.1 V or VCC-0.1 V  
êIOUTê£ 20 mA  
2.0  
4.5  
6.0  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
V
IL  
Maximum Low -Level  
Input Voltage  
VOUT=0.1 V or VCC-0.1 V  
êIOUTê £ 20 mA  
2.0  
4.5  
6.0  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
V
VOH  
Minimum High-Level  
Output Voltage  
V =V or V  
IL  
êIOUTê £ 20 mA  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
V
IN  
IH  
V =V or V  
IL  
êIOUTê £ 6.0 mA  
êIOUTê £ 7.8 mA  
4.5  
6.0  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
IN  
IH  
VOL  
Maximum Low-Level  
Output Voltage  
V = V or V  
IH  
êIOUTê £ 20 mA  
2.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
IN  
IL  
V = V or V  
IH  
êIOUTê £ 6.0 mA  
êIOUTê £7.8 mA  
4.5  
6.0  
0.26  
0.26  
0.33  
0.33  
0.4  
0.4  
IN  
IL  
IIN  
Maximum Input  
Leakage Current  
V =VCC or GND  
6.0  
6.0  
±0.1  
±0.5  
±1.0  
±5.0  
±1.0  
±10  
mA  
mA  
IN  
IOZ  
Maximum Three State Output in High-Impedance  
Leakage Current  
State  
V =V or V  
IL  
IN  
IH  
VOUT= VCC or GND  
ICC  
Maximum Quiescent  
Supply Current  
(per Package)  
V =VCC or GND  
IOUT=0mA  
6.0  
4.0  
40  
160  
mA  
IN  
System Logic  
Semiconductor  
SLS  
SL74HC374  
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)  
VCC  
Guaranteed Limit  
Symbol  
fmax  
Parameter  
V
25 °C to £85°C  
-55°C  
£125°C  
Unit  
Maximum Clock Frequency (50% Duty Cycle)  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
6.0  
30  
35  
5.0  
24  
28  
4.0  
20  
24  
MHz  
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures  
1 and 4)  
2.0  
4.5  
6.0  
125  
25  
21  
155  
31  
26  
190  
38  
32  
ns  
ns  
ns  
ns  
tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Q  
(Figures 2 and 5)  
2.0  
4.5  
6.0  
150  
30  
26  
190  
38  
33  
225  
45  
38  
tPZH, tPZL Maximum Propagation Delay, Output Enable to Q  
(Figures 2 and 5)  
2.0  
4.5  
6.0  
150  
30  
26  
190  
38  
33  
225  
45  
38  
tTLH, tTHL Maximum Output Transition Time, Any Output  
(Figures 1 and 4)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
CIN  
Maximum Input Capacitance  
-
-
10  
15  
10  
15  
10  
15  
pF  
pF  
COUT  
Maximum Three-State Output Capacitance  
(Output in High-Impedance State)  
Power Dissipation Capacitance (Per Enabled  
Output)  
Typical @25°C,VCC=5.0 V  
CPD  
Used to determine the no-load dynamic power  
consumption: PD=CPDVCC2f+ICCVCC  
34  
pF  
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)  
VCC  
Guaranteed Limit  
Symbol  
tSU  
Parameter  
V
25 °C to  
-55°C  
£85°C  
£125°C  
Unit  
Minimum Setup Time, Data to  
Clock (Figure 3)  
2.0  
4.5  
6.0  
50  
10  
9
65  
13  
11  
75  
15  
13  
ns  
ns  
ns  
ns  
th  
Minimum Hold Time, Clock to  
Data (Figure 3)  
2.0  
4.5  
6.0  
5
5
5
5
5
5
5
5
5
tw  
Minimum Pulse Width, Clock  
(Figure 1)  
2.0  
4.5  
6.0  
60  
12  
10  
75  
15  
13  
90  
18  
15  
tr, tf  
Maximum Input Rise and Fall  
Times (Figure 1)  
2.0  
4.5  
6.0  
1000  
500  
400  
1000  
500  
400  
1000  
500  
400  
System Logic  
Semiconductor  
SLS  
SL74HC374  
Figure 1. Switching Waveforms  
Figure 2. Switching Waveforms  
Figure 3. Switching Waveforms  
Figure 4. Test Circuit  
Figure 5. Test Circuit  
EXPANDED LOGIC DIAGRAM  
System Logic  
Semiconductor  
SLS  

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