SL74HC4015 [SLS]
Dual 4-Bit Shift Register; 双4位移位寄存器
| 型号： | SL74HC4015 |
| 厂家： | 
SYSTEM LOGIC SEMICONDUCTOR |
| 描述： | Dual 4-Bit Shift Register |
| 文件： | 总6页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL74HC4015
Dual 4-Bit Shift Register
High-Performance Silicon-Gate CMOS
The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two identical independent 4-stage serial-
input/parallel-output registers. Each register has independent Clock
and Reset inputs as well as a single serial Data input. “Q” outputs are
available from each of the four stages on both registers. All register
stages are D-type, master-slave flip-flops. The logic level present at the
Data input is transferred into the first register stage and shifted over
one stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
ORDERING INFORMATION
SL74HC4015N Plastic
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
SL74HC4015D SOIC
TA = -55° to 125° C for all packages
High Noise Immunity Characteristic of CMOS Devices
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Data
L
Outputs
Clock
X
Reset
Q0
Qn
Qn-1
Qn-1
Qn*
L
L
L
L
H
L
H
H
PIN 16 = VCC
PIN 8 = GND
X
Q0*
X
L
* = No Change
X = don’ t care
System Logic
SLS
SL74HC4015
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
V
V
V
IN
VOUT
IIN
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V , VOUT
IN
VCC
V
TA
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range
IN
GND£(V or VOUT)£VCC.
IN
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
System Logic
SLS
SL74HC4015
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
25 °C
to
£85
°C
£125
°C
Unit
V
-55°C
V
IH
Minimum High-Level
Input Voltage
VOUT= 0.1 V or VCC-0.1 V
êIOUTê£ 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
IL
Maximum Low -Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
êIOUTê £ 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
IN
IH
V = V or V
IL
IN
IH
êIOUTê £ 4.0 mA
êIOUTê £ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
V = V or V
IL
IN
IH
êIOUTê £ 4.0 mA
êIOUTê £ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
V =VCC or GND
6.0
±0.1
±1.0
±1.0
mA
mA
IN
ICC
Maximum Quiescent
Supply Current
(per Package)
V =VCC or GND
6.0
8.0
80
160
IN
IOUT=0mA
System Logic
Semiconductor
SLS
SL74HC4015
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
fmax
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figure 2)
2.0
4.5
6.0
6
30
35
4.8
24
28
4
20
24
MHz
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures
2 and 5)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
ns
ns
pF
tPHL
Maximum Propagation Delay, Reset to Q (Figures
1 and 5)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Latch)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
140
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
25 °C to
-55°C
£85°C
£125°C
Unit
ns
Minimum Setup Time, D to Clock
(Figure 4)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
th
trec
tw
Minimum Hold Time, Clock to D
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
ns
ns
Minimum Recovery Time, Reset to
Clock (Figure 1)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
Minimum Pulse Width, Reset (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tw
Minimum Pulse Width, Clock (Figure
4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
System Logic
SLS
SL74HC4015
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
System Logic
Semiconductor
SLS
SL74HC4015
EXPANDED LOGIC DIAGRAM
System Logic
SLS
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