SL74HC393D [SLS]
Dual 4-Stage Binary Ripple Counter; 双4级二进制纹波计数器
| 型号： | SL74HC393D |
| 厂家： | 
SYSTEM LOGIC SEMICONDUCTOR |
| 描述： | Dual 4-Stage Binary Ripple Counter |
| 文件： | 总7页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL74HC393
Dual 4-Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS
The SL74HC393 is identical in pinout to the LS/ALS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two independent 4-bit binary ripple
counters with parallel outputs from each counter stage. A¸ 256 counter
can be obtained by cascading the two binary counters.
Internal flip-flops are triggered by high-to-low transitions of the
clock input. Reset for the counters is asynchronous and active-high.
State changes of the Q outputs do not occur simultaneously becaue of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the SL74HC393.
ORDERING INFORMATION
SL74HC393N Plastic
SL74HC393D SOIC
TA = -55° to 125° C for all packages
·
·
·
·
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
PIN ASSIGNMENT
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Outputs
Clock
Reset
X
H
L
H
L
L
L
L
L
PIN 14 =VCC
PIN 7 = GND
No Change
No Change
No Change
Advance to Next
State
X = don’ t care
System Logic
Semiconductor
SLS
SL74HC393
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
VCC
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
-0.5 to +7.0
V
IN
-1.5 to VCC +1.5
V
V
VOUT
IIN
-0.5 to VCC +0.5
±20
±25
±50
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
V , VOUT
IN
VCC
V
TA
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range
IN
GND£(V or VOUT)£VCC.
IN
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must be left open.
System Logic
SLS
SL74HC393
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
25 °C
to
£85
°C
£125
°C
Unit
V
-55°C
V
IH
Minimum High-Level
Input Voltage
VOUT=0.1 V or VCC-0.1 V
êIOUTê£ 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
IL
Maximum Low -Level VOUT=0.1 V or VCC-0.1 V
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Input Voltage
êIOUTê £ 20 mA
VOH
Minimum High-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
IN
IH
V =V or V
IL
IN
IH
êIOUTê £ 4.0 mA
êIOUTê £ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-Level
Output Voltage
V =V or V
IL
êIOUTê £ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
V =V or V
IL
IN
IH
êIOUTê £ 4.0 mA
êIOUTê £ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
V =VCC or GND
6.0
±0.1
±1.0
±1.0
mA
mA
IN
ICC
Maximum Quiescent
Supply Current
(per Package)
V =VCC or GND
6.0
8.0
80
160
IN
IOUT=0mA
System Logic
SLS
SL74HC393
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
25 °C to
-55°C
£85°C
£125°C Unit
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 3)
2.0
4.5
6.0
5.4
27
32
4.4
22
26
3.6
18
21
MHz
ns
tPLH, tPHL Maximum Propagation Delay, Clock to Q1
(Figures 1 and 3)
2.0
4.5
6.0
120
24
20
150
30
26
180
36
31
tPLH, tPHL Maximum Propagation Delay, Clock to Q2
(Figures 1 and 3)
2.0
4.5
6.0
190
38
32
240
48
41
285
57
48
ns
tPLH, tPHL Maximum Propagation Delay, Clock to Q3
(Figures 1 and 3)
2.0
4.5
6.0
240
48
41
300
60
51
360
72
61
ns
tPLH, tPHL Maximum Propagation Delay, Clock to Q4
(Figures 1 and 3)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
ns
tPHL
Maximum Propagation Delay, Reset to any Q
(Figures 2 and 3)
2.0
4.5
6.0
165
33
28
205
41
35
250
50
43
ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
CIN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Counter)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
40
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
trec
Parameter
V
25 °C to-55°C
£85°C
£125°C
Unit
ns
Minimum Recovery Time, Reset
Inactive to Clock (Figure 2)
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
tw
Minimum Pulse Width, Clock (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
ns
ns
tw
Minimum Pulse Width, Set
(Figure 2)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
1000
500
1000
500
1000
500
System Logic
SLS
SL74HC393
6.0
400
400
400
System Logic
SLS
SL74HC393
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 4.Test Circuit
EXPANDED LOGIC DIAGRAM
System Logic
SLS
SL74HC393
TIMING DIAGRAM
COUNT SEQUENCE
Outputs
Count
0
Q4
L
Q3
L
Q2
L
Q1
L
1
L
L
L
H
L
2
L
L
H
H
L
3
L
L
H
L
4
L
H
H
H
H
L
5
L
L
H
L
6
L
H
H
L
7
L
H
L
8
H
H
H
H
H
H
H
H
9
L
L
H
L
10
11
12
13
14
15
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
System Logic
SLS
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