STK22C48_08 [SIMTEK]
2Kx8 AutoStore nvSRAM; 2Kx8自动存储的nvSRAM
| 型号： | STK22C48_08 |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | 2Kx8 AutoStore nvSRAM |
| 文件： | 总16页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK22C48
2Kx8 AutoStore nvSRAM
DESCRIPTION
FEATURES
• 25, 45 ns Read Access & R/W Cycle Times
The Simtek STK22C48 is a 16Kb fast static RAM with
a nonvolatile Quantum Trap storage element included
with each memory cell.
• Unlimited Read/Write Endurance
• Automatic Non-Volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware Control
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
The SRAM provides the fast access & cycle times,
ease of use, and unlimited read & write endurance of
a normal SRAM.
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the STORE
operation). On power-up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5.0V +10% Operation
• Commercial, Industrial, and Military
Temperatures
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest-performance, most reliable non-volatile
memory available.
• 28-Pin 300 mil SOIC or 330 mil SOIC (RoHS-
Compliant)
BLOCK DIAGRAM
V
V
CAP
CC
POWER
CONTROL
Quantum Trap
32 x 512
A
A
A
A
A
STORE
RECALL
5
6
7
8
9
STORE/
RECALL
CONTROL
HSB
STATIC RAM
ARRAY
32 x 512
DQ
DQ
DQ
0
1
2
COLUMN I/O
COLUMN DEC
DQ
DQ
3
4
DQ
DQ
DQ
5
6
7
A
10
A A A A A
0 1 2 3 4
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
Rev 2.0
Document Control #ML0004
Feb, 2008
1
STK22C48
PIN CONFIGURATIONS
1
V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
W
HSB
A
A
NC
G
CAP
NC
CCX
2
3
A
A
A
A
A
7
6
5
4
4
8
5
9
6
(TOP)
7
3
2
8
A
A
E
10
9
A
1
0
10
11
12
13
14
A
DQ
DQ
DQ
DQ
DQ
7
6
5
DQ
DQ
DQ
V
0
1
2
4
3
SS
28-pin 300 mil SOIC
28-pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 11 address inputs select one of 2,048 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
10
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, ±10%
Ground
CC
SS
Rev 2.0
Document Control #ML0004
Feb, 2008
2
STK22C48
a
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on Input Relative to Ground . . . . . . . . . . . . . –0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . .–0.6V to (V + 0.5V)
CC
Voltage on DQ0-7 or HSB . . . . . . . . . . . . . . . .–0.5V to (V + 0.5V)
CC
Temperature under Bias . . . . . . . . . . . . . . . . . . . . .–55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .–65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . 15mA
Package Thermal Characteristics - See Website at http://www.simtek.com
e
DC CHARACTERISTICS
(V = 5.0V ± 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
85
65
90
65
mA
mA
t
t
= 25ns
= 45ns
CC
1
CC
AVAV
AVAV
c
I
I
Average V Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
2
3
b
Average V Current at t
CC
= 200ns
W ≥ (V – 0.2V)
CC
AVAV
CC
10
10
5V, 25°C, Typical
All Others Cycling, CMOS Levels
c
I
I
I
I
I
Average V
Cycle
Current during AutoStore
CAP
All Inputs Don’t Care
CC
4
2
2
mA
d
Average V Current
CC
(Standby, Cycling TTL Input Levels)
25
18
26
19
mA
mA
t
t
= 25ns, E ≥ V
= 45ns, E ≥ V
SB
SB
AVAV
AVAV
IH
IH
1
d
V
Standby Current
E ≥ (V – 0.2V)
CC
CC
2
1.5
±1
±5
1.5
±1
±5
mA
μA
μA
(Standby, Stable CMOS Input Levels)
All Others V ≤ 0.2V or ≥ (V – 0.2V)
IN CC
Input Leakage Current
V = max
CC
ILK
V
= V to V
CC
IN
SS
Off-State Output Leakage Current
V = max
CC
OLK
V
= V to V , E or G ≥ V
IH
IN
SS
CC
V
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Logic “0” Voltage on HSB Output
Operating Temperature
Storage Capacitance
2.2
V
+ .5
2.2
V + .5
CC
V
V
All Inputs
All Inputs
IH
CC
V
– .5
0.8
V – .5
SS
0.8
IL
SS
2.4
2.4
V
I
I
I
=–4mA except HSB
= 8mA except HSB
= 3mA
OH
OL
BL
OUT
OUT
OUT
0.4
0.4
70
0.4
0.4
85
V
V
0
–40
61
°C
μF
A
V
61
220
220
5 Volt rated, 68 μF+20%/-10% Nom.
CAP
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).
2
4
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
Note e: VCC reference levels throughout this datasheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground.
5.0V
AC TEST CONDITIONS
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
480 Ohms
Input and Output Timing Reference Levels. . . . . . . . . . . . . . . .1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
OUTPUT
30 pF
255 Ohms
f
CAPACITANCE
(T = 25°C, f = 1.0MHz)
INCLUDING
SCOPE AND
FIXTURE
A
SYMBOL
PARAMETER
MAX
UNITS
pF
pF
CONDITIONS
C
Input Capacitance
Output Capacitance
8
7
ΔV = 0 to 3V
IN
C
ΔV = 0 to 3V
OUT
Figure 1: AC Output Loading
Note f: These parameters are guaranteed but not tested.
Rev 2.0
Document Control #ML0004
Feb, 2008
3
STK22C48
SRAM READ CYCLES #1 & #2
e
(V = 5.0V ± 10%)
CC
SYMBOLS
NO.
STK22C48-25
STK22C48-45
PARAMETER
Chip Enable Access Time
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
g
t
Read Cycle Time
25
45
AVAV , ELEH
h
3
Address Access Time
25
10
45
20
AVQV
4
Output Enable to Data Valid
GLQV
OE
OH
LZ
h
5
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
5
5
5
5
AXQX
6
ELQX
i
7
10
10
25
15
15
45
EHQZ
HZ
8
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
10
11
ELICCH
f
Chip Disable to Power Standby
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
g, h
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
g
SRAM READ CYCLE #2: E and G Controlled
ADDRESS
2
29
tE LE H
tEHAX
1
11
tEL Q V
tEHI CC L
6
E
tELQ X
27
7
tEHQ Z
3
tAV QV
G
9
4
tG L QV
tGH Q Z
8
tG L Q X
DQ (DATA OUT)
DATA VAL ID
10
tELI CC H
AC TIVE
STAND BY
ICC
Rev 2.0
Document Control #ML0004
Feb, 2008
4
STK22C48
e
SRAM WRITE CYCLES #1 & #2
(V = 5.0V ± 10%)
CC
SYMBOLS
STK22C48-25 STK22C48-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
tWC
tWP
tCW
tDW
tDH
tAW
tAS
MIN
25
20
20
10
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
tAVAV
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
20
0
30
0
tWR
tWZ
tOW
0
0
i, j
tWLQZ
10
15
tWHQX
5
5
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
k, l
SRAM WRITE CYCLE #1: W Controlled
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
W
tWLWH
15
tDVWH
16
tWHDX
DATA IN
DATA VALID
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
k, l
SRAM WRITE CYCLE #2: E Controlled
12
tAVAV
ADDRESS
14
tELEH
18
tAVEL
19
tEHAX
E
17
tAVEH
13
tWLEH
W
15
tDVEH
16
tEHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 2.0
Document Control #ML0004
Feb, 2008
5
STK22C48
HARDWARE MODE SELECTION
E
W
HSB
A
- A (hex)
MODE
I/O
Output High Z
Output Data
Input Data
POWER
Standby
NOTES
12
0
H
L
X
H
L
H
H
H
L
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Active
Active
n
L
X
X
Nonvolatile STORE
Output High Z
lCC
2
m
Note m: HSB STORE operation occurs only if an SRAM write has been done since the last nonvolatile cycle. After the STORE (if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
Note n: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
e
HARDWARE STORE CYCLE
(V = 5.0V ± 10%)
CC
SYMBOLS
NO.
STK22C48
PARAMETER
UNITS NOTES
Standard
tSTORE
tDELAY
Alternate
MIN
1
MAX
22
23
24
25
26
tHLHZ
STORE Cycle Duration
10
ms
μs
ns
ns
ns
i, o
i, p
tHLQZ
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
tRECOVER
tHLHX
tHHQX
700
300
o, q
15
tHLBL
Hardware STORE Low to Store Busy
Note o: E and G low for output behavior.
Note p: E and G low and W high for output behavior.
Note q: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
tHLHX
HSB (IN)
24
tRECOVER
22
tSTORE
26
tHLBL
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
tDELAY
DQ (DATA OUT)
DATA VALID
Rev 2.0
Document Control #ML0004
Feb, 2008
6
STK22C48
(V = 5.0V ± 10%)
e
AutoStore™/POWER-UP RECALL
CC
SYMBOLS
NO.
STK22C48
PARAMETER
UNITS NOTES
Standard
tRESTORE
tSTORE
Alternate
MIN
MAX
27
28
29
30
31
32
Power-up RECALL Duration
STORE Cycle Duration
550
10
μs
ms
ns
μs
V
r
p, s
l
tHLHZ
tVSBL
Low Voltage Trigger (VSWITCH) to HSB Low
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
300
tDELAY
tBLQZ
1
o
VSWITCH
VRESET
4.0
4.5
3.6
Low Voltage Reset Level
V
Note r: tRESTORE starts from the time VCC rises above VSWITCH
.
Note s: HSB is asserted low for 1μs when VCAP drops through VSWITCH. If an SRAM write has not taken place since the last nonvolatile cycle, HSB will be
released and no STORE will take place.
AutoStore™/POWER-UP RECALL
VCC
31
VSWITCH
32
VRESET
TM
AutoStore
POWER-UP RECALL
29
tVSBL
28
tSTORE
27
tRESTORE
HSB
30
tDELAY
W
DQ (DATA OUT)
POWER-UP
RECALL
BROWN OUT
NO STORE
BROWN OUT
AutoStore
BROWN OUT
AutoStore
(NO SRAM WRITES)
NO RECALL
NO RECALL
RECALL WHEN
(V DID NOT GO
(V DID NOT GO
V
RETURNS
CC
CC
CC
BELOW V
)
BELOW V
)
ABOVE V
SWITCH
RESET
RESET
Rev 2.0
Document Control #ML0004
Feb, 2008
7
STK22C48
nvSRAM OPERATION
The STK22C48 has two separate modes of opera-
tion: SRAM mode and nonvolatile mode. In SRAM
mode, the memory operates as a standard fast static
RAM. In nonvolatile mode, data is transferred from
SRAM to Nonvolatile Elements (the STORE opera-
tion) or from Nonvolatile Elements to SRAM (the
RECALL operation). In this mode SRAM functions are
disabled.
POWER-UP RECALL
During power up, or after any low-power condition
(VCAP < VRESET), an internal RECALL request will be
latched. When VCAP once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK22C48 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
NOISE CONSIDERATIONS
The STK22C48 is a high-speed memory and so
must have a high-frequency bypass capacitor of
approximately 0.1μF connected between VCAP and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
VCC or between E and system VCC.
AutoStore MODE
The STK22C48 can be powered in one of three
modes.
During normal AutoStore operation, the STK22C48
will draw current from VCC to charge a capacitor con-
nected to the VCAP pin. This stored charge will be
used by the chip to perform a single STORE opera-
tion. After power up, when the voltage on the VCAP
pin drops below VSWITCH, the part will automatically
disconnect the VCAP pin from VCC and initiate a
STORE operation.
SRAM READ
The STK22C48 performs a READ cycle whenever E
and G are low and W and HSB are high. The
address specified on pins A0-10 determines which of
the 2,048 data bytes will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond to
address changes within the tAVQV access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought high, or W or HSB is brought low.
Figure 2 shows the proper connection of capacitors
for automatic store operation. A charge storage
capacitor having a capacity of between 68μF and
220μF (± 20%) rated at 6V should be provided.
In system power mode, both VCC and VCAP are con-
nected to the + 5V power supply without the 68μF
capacitor. In this mode the AutoStore function of the
SRAM WRITE
10kΩ∗
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
1
32
31
30
+
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
16
17
Figure 2: AutoStore Mode
*If HSB is not used, it should be left unconnected.
Rev 2.0
Document Control #ML0004
Feb, 2008
8
STK22C48
condition while the STORE (initiated by any means)
STK22C48 will operate on the stored system charge
as power goes down. The user must, however, guar-
antee that VCC does not drop below 3.6V during the
10ms STORE cycle.
is in progress. Pull up this pin with an external 10K
ohm resistor to V
if HSB is used as a driver.
CAP
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK22C48 will
AutoStore INHIBIT MODE
If an automatic STORE on power loss is not required,
then VCC can be tied to ground and + 5V applied to
VCAP (Figure 3). This is the AutoStore Inhibit mode,
in which the AutoStore function is disabled. If the
STK22C48 is operated in this configuration, refer-
ences to VCC should be changed to VCAP throughout
this data sheet. In this mode, STORE operations may
be triggered with the HSB pin. To enable or disable
AutoStore using an IO port pin, see “PREVENTING
STORES” on page 9.
continue SRAM operations for tDELAY. During tDELAY
,
multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low it will
be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple
STK22C48s while using a single larger capacitor. To
operate in this mode the HSB pin should be con-
nected together to the HSB pins from the other
STK22C48s. An external pull-up resistor to + 5V is
required since HSB acts as an open drain pull down.
The VCAP pins from the other STK22C48 parts can
be tied together and share a single capacitor. The
capacitor size must be scaled by the number of
devices connected to it. When any one of the
STK22C48s detects a power loss and asserts HSB,
the common HSB pin will cause all parts to request a
STORE cycle (a STORE will take place in those
STK22C48s that have been written since the last
nonvolatile cycle).
1
32
31
30
17
16
Figure 3: AutoStore Inhibit Mode
During any STORE operation, regardless of how it
was initiated, the STK22C48 will continue to drive
the HSB pin low, releasing it only when the STORE is
complete. Upon completion of the STORE operation
the STK22C48 will remain disabled until the HSB pin
returns high.
In order to prevent unneeded STORE operations,
automatic STOREs as well as those initiated by
externally driving HSB low will be ignored unless at
least one WRITE operation has taken place since the
most recent STORE or RECALL cycle.
If the power supply drops faster than 20 μs/volt
before VCC reaches VSWITCH, then a 2.2 ohm resistor
should be inserted between VCC and the system sup-
ply to avoid momentary excess of current between
Vcc and Vcap.
If HSB is not used, it should be left unconnected.
PREVENTING STORES
The STORE function can be disabled on the fly by
holding HSB high with a driver capable of sourcing
30mA at a VOH of at least 2.2V, as it will have to
overpower the internal pull-down device that drives
HSB low for 20μs at the onset of a STORE. When the
STK22C48 is connected for AutoStore operation
(system VCC connected to VCC and a 68μF capacitor
on VCAP) and VCC crosses VSWITCH on the way down,
the STK22C48 will attempt to pull HSB low; if HSB
doesn’t actually get below VIL, the part will stop try-
ing to pull HSB low and abort the STORE attempt.
HSB OPERATION
The STK22C48 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin is used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK22C48 will
conditionally initiate a STORE operation after tDELAY
;
an actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The HSB pin has a very resistive pul-
lup and is internally driven low to indicate a busy
Rev 2.0
Document Control #ML0004
Feb, 2008
9
STK22C48
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 5 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK22C48 depends on the following items: 1)
CMOS vs. TTL input levels; 2) the duty cycle of chip
enable; 3) the overall cycle rate for accesses; 4) the
ratio of READs to WRITEs; 5) the operating tempera-
HARDWARE PROTECT
The STK22C48 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs dur-
ing low-voltage conditions. When VCAP < VSWITCH, all
externally initiated STORE operations and SRAM
WRITEs are inhibited.
AutoStore can be completely disabled by tying VCCX
to ground and applying + 5V to VCAP. This is the
AutoStore
Inhibit mode; in this mode STOREs are only
initiated by explicit request using the HSB pin.
LOW AVERAGE ACTIVE POWER
ture; 6) the V level; and 7) I/O loading.
cc
The STK22C48 draws significantly less current
when it is cycled at times longer than 50ns. Figure 4
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
150 200
0
0
50
100
Cycle Time (ns)
Figure 4: Icc (max) Reads
50
100
Cycle Time (ns)
Figure 5: Icc (max) Writes
150
200
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STK22C48
desired state as a safeguard against events that
might flip the bit inadvertently (program bugs,
incoming inspection routines, etc.).
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the
product’s main system values, experience gained
working with hundreds of applications has resulted
in the following suggestions as best practices:
• The V
value specified in this datasheet
cap
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max V
inrush currents may reduce the reliability of the
internal pass transistor. Customers that want to
value because the higher
cap
• The non-volatile cells in an nvSRAM are pro-
grammed on the test floor during final test and
quality assurance. Incoming inspection routines
at customer or contract manufacturer’s sites will
sometimes reprogram these values. Final NV
patterns are typically repeating patterns of AA,
55, 00, FF, A5, or 5A. End product’s firmware
should not assume an NV array is in a set pro-
grammed state. Routines that check memory
content values to determine first time system
configuration, cold or warm boot status, etc.
should always program a unique NV pattern
(e.g., complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final sys-
tem manufacturing test to ensure these system
routines work consistently.
use a larger V
value to make sure there is
cap
extra store charge should discuss their V
selection with Simtek.
size
cap
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state. While the
nvSRAM is shipped in a preset state, best prac-
tice is to again rewrite the nvSRAM into the
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STK22C48
ORDERING INFORMATION
STK22C48 - N F 45 I TR
Packing Option
Blank = Tube
TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (-40 to 85°C)
Access Time
25 = 25ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 330 mil SIOC
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STK22C48
Ordering Information
Item Number
Item Name
Access Times
Temperature
STK22C48-NF25
STK22C48-NF45
STK22C48-SF25
STK22C48-SF45
STK22C48-NF25TR
STK22C48-NF45TR
STK22C48-SF25TR
STK22C48-SF45TR
STK22C48-NF25I
STK22C48-NF45I
STK22C48-SF25I
STK22C48-SF45I
STK22C48-NF25ITR
STK22C48-NF45ITR
STK22C48-SF25ITR
STK22C48-SF45ITR
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-300
5V 2Kx 8 AutoStore nvSRAM SOP28-330
5V 2Kx 8 AutoStore nvSRAM SOP28-330
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
25 ns access time
45 ns access time
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
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STK22C48
Package Diagrams
28-Lead, 300 mil SOIC Gull Wing
0.292 7.42
0.300 7.59
(
)
0.400 10.16
( )
0.410 10.41
Pin 1
Index
.050 (1.27)
BSC
0.701 17.81
0.711 18.06
(
)
0.097 2.46
( )
0.104 2.64
0.090 2.29
0.094 2.39
)
(
0.005 0.12
0.012 0.29
(
)
0.014 0.35
0.019 0.48
)
(
MIN
MAX
DIM = INCHES
0°
8°
0.009 0.23
( )
0.013 0.32
MIN
(MAX)
DIM = mm
0.024 0.61
(
)
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STK22C48
28-Lead, 330 mil SOIC Gull Wing
0.713
0.733
18.11
(
)
18.62
0.112
0.004
(2.845)
(0.102)
0.020
0.014
0.508
0.356
0.050 (1.270)
(
)
0.103
2.616
2.362
(
)
0.093
0.336
0.326
8.534
8.280
0.477
12.116
11.506
(
)
(
)
0.453
Pin 1
10°
0°
0.014
0.008
0.356
0.203
(
)
0.044
1.117
(
)
0.028
0.711
MIN
MAX
DIM = INCHES
MIN
MAX
)
(
DIM = mm
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STK22C48
Document Revision History
Revision
0.0
Date
December 2002
September 2003
March 2006
Summary
Removed 20 nsec device.
0.1
Added lead-free lead finish
0.2
Obsolete: 35ns speed grade, Plastic DIP packages and Leaded Lead Finish
Add Fast Power-Down Slew Rate Information
0.3
February 2007
Add Tape Reel Ordering Options
Add Product Ordering Code Listing
Add Package Drawings
Reformat Entire Document
2.0
January 2008
In the block diagram and elsewhere in this data sheet, removed the “x” from Vccx.
Page 4: in SRAM Read Cycles #1 & #2 table, revised description for tELQX and tEHQZ and
changed Symbol #2 to tELEH for Read Cycle Time.
Page 4: updated SRAM Read Cycle #2 timing diagram and changed title to add G
controlled.
Page 9: under HSB Operation, revised first paragraph to read “The HSB pin has a very
resistive pullup...”
Page 11: added best practices section.
Page 13: added access times to Ordering Information table.
SIMTEK STK22C48 Datasheet, January 2008
Copyright 2008, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MER-
CHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a
license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Rev 2.0
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16
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