STK22C48_11 [CYPRESS]
16-Kbit (2 K × 8) AutoStore? nvSRAM; 16 - Kbit的（ 2 k × 8 ）自动存储™的nvSRAM
| 型号： | STK22C48_11 |
| 厂家： | 
CYPRESS |
| 描述： | 16-Kbit (2 K × 8) AutoStore? nvSRAM |
| 文件： | 总17页 (文件大小：1448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK22C48
16-Kbit (2 K × 8) AutoStore™ nvSRAM
16-Kbit (2
K × 8) AutoStore nvSRAM
Features
Functional Description
■ 25 ns and 45 ns access times
The Cypress STK22C48 is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
■ Hands off automatic STORE on power-down with external
68 µF capacitor
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. A hardware STORE is initiated with
the HSB pin.
■ STORE to QuantumTrap™ nonvolatile elements is initiated by
software, hardware, or AutoStore™ on power-down
■ RECALL to SRAM initiated by software or power-up
■ Unlimited read, write, and RECALL cycles
■ 1,000,000 STORE cycles to QuantumTrap
■ 100 year data retention to QuantumTrap
■ Single 5 V +10% operation
■ Commercial and industrial temperatures
■ 28-pin 300 mil and (330 mil) Small outline integrated circuit
(SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
V
V
CC
CAP
Quantum Trap
32 X 512
POWER
A5
STORE
CONTROL
A6
RECALL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
32 X 512
A7
A8
HSB
A9
DQ0
COLUMN I/O
DQ1
DQ2
DQ3
COLUMN DEC
DQ4
DQ5
DQ6
DQ7
A0
A4
A10
A1
A3
A2
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-51000 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 7, 2011
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STK22C48
Contents
Pin Configurations ........................................................... 3
Device Operation ..............................................................4
SRAM Read ....................................................................... 4
SRAM Write....................................................................... 4
AutoStore Operation ........................................................ 4
AutoStore Inhibit mode ....................................................4
Hardware STORE (HSB) Operation .................................5
Hardware RECALL (Power Up) ........................................5
Data Protection .................................................................5
Noise Considerations....................................................... 5
Hardware Protect.............................................................. 5
Low Average Active Power.............................................. 5
Preventing Store............................................................... 6
Best Practices................................................................... 6
Maximum Ratings .............................................................7
Operating Range ...............................................................7
DC Electrical Characteristics ..........................................7
Data Retention and Endurance .......................................7
Capacitance ...................................................................... 8
Thermal Resistance ..........................................................8
AC Test Conditions ..........................................................8
AC Switching Characteristics .........................................9
SRAM Read Cycle ......................................................9
Switching Waveforms ...................................................... 9
SRAM Write Cycle .....................................................10
AutoStore or Power Up RECALL ..................................11
Switching Waveform ......................................................11
Hardware STORE Cycle .................................................12
Switching Waveform ......................................................12
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Package Diagrams ..........................................................14
Document Conventions .................................................15
Acronyms .................................................................15
Units of Measure .......................................................15
Document History Page................................................. 16
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC Solutions .........................................................17
Document Number: 001-51000 Rev. *D
Page 2 of 17
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STK22C48
Pin Configurations
Figure 1. Pin Diagram - 28-pin SOIC
1
28
VCC
WE
VCAP
2
3
NC
A7
A6
27
26
HSB
A8
4
5
25
24
A5
A4
A3
A9
6
7
NC
23
28-SOIC
22
OE
A10
Top View
A2
8
21
(Not To Scale)
A1
A0
9
20
19
18
17
16
CE
10
11
12
13
DQ7
DQ6
DQ5
DQ4
DQ0
DQ1
DQ2
VSS
14
15
Q3
Table 1. Pin Definitions
Pin Name Alt
A0–A10
IO Type
Input
Input or output Bidirectional data IO lines. Used as input or output lines depending on operation.
Description
Address inputs. Used to elect one of the 2,048 bytes of the nvSRAM.
DQ0–DQ7
Input
Write enable input, active LOW. When the chip is enabled and WE is LOW, data on the IO
pins is written to the specific address location.
WE
W
Input
Input
Chip enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
E
Output enable, active LOW. The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
G
VSS
VCC
Ground
Ground for the device. The device is connected to ground of the system.
Power supply Power supply inputs to the device.
Input or output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull-up resistor keeps this pin high if not connected (connection optional).
HSB
VCAP
NC
Power supply AutoStore capacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
No connect No connect. This pin is not connected to the die.
Document Number: 001-51000 Rev. *D
Page 3 of 17
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STK22C48
Figure 2. AutoStore Mode
Device Operation
The STK22C48 nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables the storage and
recall of all cells in parallel. During the STORE and RECALL
operations, SRAM Read and Write operations are inhibited. The
STK22C48 supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL
operations from the nonvolatile cells and up to one million
STORE operations.
9&$3
9FF
:(
+6%
SRAM Read
The STK22C48 performs a Read cycle whenever CE and OE are
LOW while WE and HSB are HIGH. The address specified on
pins A0–10 determines the 2,048 data bytes accessed. When the
Read is initiated by an address transition, the outputs are valid
after a delay of tAA (Read cycle 1). If the Read is initiated by CE
or OE, the outputs are valid at tACE or at tDOE, whichever is later
(Read cycle 2). The data outputs repeatedly respond to address
changes within the tAA access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
9VV
In system power mode, both VCC and VCAP are connected to the
+5 V power supply without the 68 μF capacitor. In this mode, the
AutoStore function of the STK22C48 operates on the stored
system charge as power goes down. The user must, however,
guarantee that VCC does not drop below 3.6 V during the 10 ms
STORE cycle.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the Write cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ0–7 are written into the memory if it has valid tSD, before
the end of a WE controlled Write or before the end of an CE
controlled Write. Keep OE HIGH during the entire Write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
To prevent unneeded STORE operations, automatic STOREs
and those initiated by externally driving HSB LOW are ignored,
unless at least one WRITE operation takes place since the most
recent STORE or RECALL cycle. An optional pull-up resistor is
shown connected to HSB. This is used to signal the system that
the AutoStore cycle is in progress.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then VCC
is tied to ground and +5 V is applied to VCAP (Figure 3 on page
5). This is the AutoStore Inhibit mode, where the AutoStore
function is disabled. If the STK22C48 is operated in this config-
uration, references to VCC are changed to VCAP throughout this
data sheet. In this mode, STORE operations are triggered with
the HSB pin. It is not permissible to change between these three
options “on the fly”.
AutoStore Operation
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. A charge storage capacitor
between 68 µF and 220 µF (+20%) rated at 6 V should be
Document Number: 001-51000 Rev. *D
Page 4 of 17
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STK22C48
Figure 3. AutoStore Inhibit Mode
Data Protection
The STK22C48 protects data from corruption during low voltage
conditions by inhibiting all externally initiated STORE and Write
operations. The low voltage condition is detected when VCC is
less than VSWITCH. If the STK22C48 is in a Write mode (both CE
and WE are low) at power-up after a RECALL or after a STORE,
the Write is inhibited until a negative transition on CE or WE is
detected. This protects against inadvertent writes during
power-up or brown out conditions.
9
&$3
9FF
:(
+6%
Noise Considerations
The STK22C48 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF connected
between VCC and VSS, using leads and traces that are as short
as possible. As with all high speed CMOS ICs, careful routing of
power, ground, and signals reduce circuit noise.
Hardware Protect
9VV
The STK22C48 offers hardware protection against inadvertent
STORE operation and SRAM Writes during low voltage
conditions. When VCAP<VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5 V to
Hardware STORE (HSB) Operation
VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs
The STK22C48 provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the STK22C48 conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a Write to the
SRAM takes place since the last STORE or RECALL cycle. The
HSB pin also acts as an open drain driver that is internally driven
LOW to indicate a busy condition, while the STORE (initiated by
any means) is in progress. Pull-up this pin with an external
10 K ohm resistor to VCAP if HSB is used as a driver.
are only initiated by explicit request using either the software
sequence or the HSB pin.
Low Average Active Power
CMOS technology provides the STK22C48 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 on page 6 shows the relationship between
ICC and Read or Write cycle time. Worst case current
consumption is shown for both CMOS and TTL input levels
(commercial temperature range, VCC = 5.5 V, 100% duty cycle
on chip enable). Only standby current is drawn when the chip is
disabled. The overall average current drawn by the STK22C48
depends on the following items:
SRAM Read and Write operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the STK22C48 continues SRAM operations for tDELAY. During
tDELAY, multiple SRAM Read operations take place. If a Write is
in progress when HSB is pulled LOW, it allows a time, tDELAY to
complete. However, any SRAM Write cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
■ The duty cycle of chip enable
■ The overall cycle rate for accesses
■ The ratio of Reads to Writes
■ CMOS versus TTL input levels
■ The operating temperature
■ The VCC level
During any STORE operation, regardless of how it is initiated,
the STK22C48 continues to drive the HSB pin LOW, releasing it
only when the STORE is complete. After completing the STORE
operation, the STK22C48 remains disabled until the HSB pin
returns HIGH.
If HSB is not used, it is left unconnected.
■ I/O loading
Hardware RECALL (Power Up)
During power-up or after any low power condition (VCC
<
VRESET), an internal RECALL request is latched. When VCC
once again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
Document Number: 001-51000 Rev. *D
Page 5 of 17
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STK22C48
Figure 4. Current Versus Cycle Time (Read)
device drives HSB LOW for 20 ns at the onset of a STORE.
When the STK22C48 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on VCAP
)
and VCC crosses VSWITCH on the way down, the STK22C48
attempts to pull HSB LOW. If HSB does not actually get below
VIL, the part stops trying to pull HSB LOW and abort the STORE
attempt.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease of use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The
end product’s firmware should not assume that an NV array is
in a set programmed state. Routines that check memory
content values to determine first time system configuration,
cold or warm boot status, and so on must always program a
unique NV pattern (for example, complex 4-byte pattern of 46
E6 49 53 hex or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Figure 5. Current Versus Cycle Time (Write)
■ Power-up boot firmware routines should rewrite the nvSRAM
into the desired state. While the nvSRAM is shipped in a preset
state, best practice is to again rewrite the nvSRAM into the
desired state as a safeguard against events that might flip the
bit inadvertently (program bugs, incoming inspection routines,
and so on).
■ The VCAP value specified in this data sheet includes a minimum
and a maximum value size. The best practice is to meet this
requirement and not exceedthe maximumVCAP value because
the higher inrush currents may reduce the reliability of the
internal pass transistor. Customers who want to use a larger
VCAP value to make sure there is extra store charge should
discuss their VCAP size selection with Cypress.
Preventing Store
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a VOH of at least 2.2 V,
because it must overpower the internal pull-down device. This
Table 2. Hardware Mode Selection
CE
H
L
WE
X
HSB
H
A10–A0
Mode
Not selected
I/O
Power
Standby
Active[1]
Active
X
X
X
X
Output high Z
Output data
Input data
H
H
Read SRAM
L
L
H
Write SRAM
[2]
X
X
L
Nonvolatile STORE
Output high Z
ICC2
Notes
1. I/O state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.
IL
2. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode,
inhibiting all operations until HSB rises.
Document Number: 001-51000 Rev. *D
Page 6 of 17
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STK22C48
Voltage on DQ0-7 or HSB .....................–0.5 V to Vcc + 0.5 V
Power dissipation ........................................................ 1.0 W
DC output current (1 output at a time, 1 s duration) .... 15 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Temperature under bias............................ –55 °C to +125 °C
Supply voltage on VCC relative to VSS............–0.5 V to 7.0 V
Voltage on input relative to VSS ...........–0.6 V to VCC + 0.5 V
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70 °C
VCC
4.5 V to 5.5 V
4.5 V to 5.5 V
–40 °C to +85 °C
DC Electrical Characteristics
Over the operating range (VCC = 4.5 V to 5.5 V) [3]
Parameter
Description
Test Conditions
Min
Max
Unit
ICC1
Average VCC current
tRC = 25 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
Commercial
Industrial
–
85
65
mA
mA
–
90
65
mA
mA
IOUT = 0 mA.
ICC2
ICC3
Average VCC current during
STORE
All inputs Do Not Care, VCC = Max
Average current for duration tSTORE
–
–
3
mA
mA
Average VCC current at
WE > (VCC – 0.2 V). All other inputs cycling.
10
t
RC = 200 ns, 5 V, 25 °C typical Dependent on output loading and cycle rate. Values obtained
without output loads.
Average VCAP current during All inputs Do Not Care, VCC = Max
ICC4
–
–
–
–
2
mA
AutoStore cycle
Average current for duration tSTORE
[4]
ISB1
Average Vcc current
(Standby, cycling TTL input
levels)
tRC = 25 ns, CE > VIH
tRC = 45 ns, CE > VIH
Commercial
Industrial
25
18
mA
mA
26
19
mA
mA
[4]
ISB2
VCC standby current
CE > (VCC – 0.2 V). All others VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
1.5
mA
IILK
Input leakage current
VCC = Max, VSS < VIN < VCC
–1
–5
+1
+5
μA
μA
IOLK
Off state output leakage
current
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL
VIH
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
2.2
VCC + 0.5
V
V
VIL
VSS – 0.5
0.8
–
VOH
VOL
VBL
VCAP
IOUT = –4 mA except HSB
IOUT = 8 mA except HSB
2.4
–
V
0.4
0.4
220
V
Logic ‘0’ voltage on HSB output IOUT = 3 mA
Storage capacitor Between VCAP pin and Vss, 6 V rated. 68 µF –10%, +20%
nom.
–
V
61
µF
Data Retention and Endurance
Parameter
Description
Min
Unit
Years
K
DATAR
NVC
Data retention
Nonvolatile STORE operations
100
1,000
Notes
3.
V
reference levels throughout this data sheet refer to V if that is where the power supply connection is made, or V
if V is connected to ground.
CC
CC
CAP CC
4. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.
IH
Document Number: 001-51000 Rev. *D
Page 7 of 17
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STK22C48
Capacitance
In the following table, the capacitance parameters are listed.[5]
Parameter
CIN
COUT
Description
Input capacitance
Output capacitance
Test Conditions
Max
8
Unit
pF
TA = 25 °C, f = 1 MHz,
CC = 0 to 3.0 V
V
7
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[5]
28-SOIC
(300 mil)
28-SOIC
(330 mil)
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
TBD
TBD
°C/W
ΘJC
Thermal resistance
(junction to case)
TBD
TBD
°C/W
Figure 6. AC Test Loads
R1 963 Ω
R1 963 Ω
For Tri-state Specs
5.0 V
5.0 V
Output
Output
R2
R2
512
30 pF
5 pF
512 Ω
Ω
AC Test Conditions
Input pulse levels....................................................0 V to 3 V
Input rise and fall times (10% to 90%)......................... < 5 ns
Input and output timing reference levels ....................... 1.5 V
Note
5. These parameters are guaranteed by design and are not tested.
Document Number: 001-51000 Rev. *D
Page 8 of 17
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STK22C48
AC Switching Characteristics
SRAM Read Cycle
Parameter
25 ns
45 ns
Description
Chip enable access time
Unit
Cypress
Alt
Min
Max
Min
Max
Parameter
tACE
tELQV
tAVAV, ELEH
tAVQV
–
25
–
25
–
–
45
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[6]
tRC
t
Read cycle time
[7]
tAA
tDOE
Address access time
25
10
–
45
20
–
tGLQV
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
–
–
[7]
tOHA
tAXQX
5
5
[8]
[8]
[8]
[8]
tLZCE
tHZCE
tLZOE
tHZOE
tELQX
5
–
5
–
tEHQZ
–
10
–
–
15
–
tGLQX
0
0
tGHQZ
–
10
–
–
15
–
[9]
tPU
tELICCH
tEHICCL
0
0
[9]
tPD
–
25
–
45
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7]
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Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6]
W5&
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W$&(
W3'
W+=&(
W/=&(
2(
W+=2(
W'2(
W/=2(
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,&&
Notes
6. WE and HSB must be High during SRAM Read cycles.
7. Device is continuously selected with CE and OE both Low.
8. Measured ±200 mV from steady state output voltage.
9. These parameters are guaranteed by design and are not tested.
Document Number: 001-51000 Rev. *D
Page 9 of 17
[+] Feedback
STK22C48
SRAM Write Cycle
Parameter
25 ns
45 ns
Description
Write cycle time
Unit
Cypress
Alt
Min
Max
Min
Max
Parameter
tWC
tAVAV
tWLWH, WLEH
tELWH, ELEH
tDVWH, DVEH
tWHDX, EHDX
tAVWH, AVEH
tAVWL, AVEL
tWHAX, EHAX
tWLQZ
tWHQX
25
20
20
10
0
–
–
45
30
30
15
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPWE
tSCE
tSD
t
Write pulse width
t
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
–
–
t
–
–
tHD
t
–
–
tAW
t
20
0
–
30
0
–
tSA
t
–
–
tHA
t
0
–
0
–
[10, 11]
[10]
tHZWE
tLZWE
–
10
–
–
14
–
5
5
Switching Waveforms
Figure 9. SRAM Write Cycle 1: WE Controlled [12, 13]
tWC
ADDRESS
CE
tHA
tSCE
tAW
tSA
tPWE
WE
tHD
tSD
DATA VALID
DATA IN
tHZWE
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
Figure 10. SRAM Write Cycle 2: CE Controlled [12, 13]
tWC
ADDRESS
tHA
tSCE
tSA
CE
WE
tAW
tPWE
tSD
tHD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Notes
10. Measured ±200 mV from steady state output voltage.
11. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
12. HSB must be high during SRAM Write cycles.
13.
CE or WE must be greater than V during address transitions.
IH
Document Number: 001-51000 Rev. *D
Page 10 of 17
[+] Feedback
STK22C48
AutoStore or Power Up RECALL
STK22C48
Max
Parameter
Alt
Description
Unit
Min
–
[14]
tHRECALL
tRESTORE
tHLHZ
tHLQZ , BLQZ
Power Up RECALL duration
STORE cycle duration
550
10
μs
ms
μs
V
[15, 16]
tSTORE
tDELAY
–
[17]
t
Time allowed to complete SRAM cycle
Low voltage trigger level
1
–
VSWITCH
4.0
–
4.5
3.6
300
VRESET
Low voltage reset level
V
[18]
tVSBL
Low voltage trigger (VSWITCH) to HSB Low
–
ns
Switching Waveform
Figure 11. AutoStore/Power Up RECALL
WE
Notes
14. t
starts from the time V rises above V
.
SWITCH
HRECALL
CC
15. CE and OE low and WE high for output behavior.
16. HSB is asserted low for 1us when V
takes place.
drops through V
. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store
SWITCH
CAP
17. CE and OE low for output behavior.
18. HSB must be high during SRAM Write cycles.
Document Number: 001-51000 Rev. *D
Page 11 of 17
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STK22C48
Hardware STORE Cycle
STK22C48
Min Max
Parameter
Alt
Description
Unit
[19, 20]
tDHSB
tPHSB
tHLBL
tRECOVER, HHQX
t
Hardware STORE HIGH to inhibit off
Hardware STORE pulse width
–
15
–
700
–
ns
ns
ns
tHLHX
Hardware STORE LOW to STORE busy
300
Switching Waveform
Figure 12. Hardware STORE Cycle
Notes
19. CE and OE low and WE high for output behavior.
20. t is only applicable after t is complete.
DHSB
STORE
Document Number: 001-51000 Rev. *D
Page 12 of 17
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STK22C48
Ordering Code Definitions
STK22C48 - N F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Temperature Range:
Blank - Commercial (0 °C to 70 °C)
I - Industrial (-40 °C to 85 °C)
Speed:
25 - 25 ns
45 - 45 ns
Lead Finish
F = 100% Sn (Matte Tin)
Package:
N = Plastic 28-pin 300 mil SOIC
S = Plastic 28-pin 330 mil SOIC
Ordering Information
These parts are not recommended for new designs. They are in production to support ongoing production programs only.
Speed (ns)
Ordering Code
STK22C48-NF25ITR
STK22C48-NF25I
STK22C48-SF25ITR
STK22C48-SF25I
Package Diagram
51-85026
Package Type
28-pin SOIC (300 mil)
28-pin SOIC (300 mil)
28-pin SOIC (330 mil)
28-pin SOIC (330 mil)
28-pin SOIC (300 mil)
28-pin SOIC (300 mil)
Operating Range
Industrial
25
51-85026
51-85058
51-85058
45
STK22C48-NF45TR
STK22C48-NF45
51-85026
Commercial
51-85026
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts
Document Number: 001-51000 Rev. *D
Page 13 of 17
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STK22C48
Package Diagrams
Figure 13. 28-Pin (300 mil) SOIC (51-85026)
51-85026 *F
Figure 14. 28-Pin (330 mil) SOIC (51-85058)
51-85058 *B
Document Number: 001-51000 Rev. *D
Page 14 of 17
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STK22C48
Document Conventions
Acronyms
Acronym
Description
CMOS
EIA
Complementary metal oxide semiconductor
Electronic Industries Alliance
I/O
Input/output
nvSRAM
RoHS
SOIC
nonvolatile static random access memory
Restriction of hazardous substances
Small outline integrated circuit
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
Hertz
Hz
kbit
KΩ
μA
mA
μF
1024 bits
kilo ohms
micro Amperes
milli Amperes
micro Farads
mega Hertz
micro seconds
milli seconds
nano seconds
pico Farads
Volts
MHz
μs
ms
ns
pF
V
Ω
ohms
W
Watts
Document Number: 001-51000 Rev. *D
Page 15 of 17
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STK22C48
Document History Page
Document Title: STK22C48 16-Kbit (2 K × 8) AutoStore™ nvSRAM
Document Number: 001-51000
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
2625139
2826441
GVCH/PYRS
GVCH
01/30/2009 New data sheet
*A
12/11/2009 Added following text in the Ordering Information section: “These parts are
not recommended for new designs. In production to support ongoing
production programs only.”
Added watermark in PDF stating “Not recommended for new designs. In
production to support ongoing production programs only.”
Added Contents on page 2.
*B
*C
3037216
3054310
GVCH
09/23/2010 Added Pin Configurations and Pin Definitions table.
Updated Package Diagrams.
Added Acronyms and units Units of Measure table.
Minor edits.
GVCH/KEER
10/11/2010 Removed inactive parts - STK22C48-NF25, STK22C48-NF25TR,
STK22C48-SF25, STK22C48-SF25TR, STK22C48-SF45,
STK22C48-SF45TR, STK22C48-NF45I, STK22C48-NF45ITR from Order-
ing information table.
Updated Package diagrams.
*D
3189527
GVCH
03/07/2011 Added watermark in PDF stating “Not recommended for new designs. In
production to support ongoing production programs only.”
Document Number: 001-51000 Rev. *D
Page 16 of 17
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STK22C48
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51000 Rev. *D
Revised March 7, 2011
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
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