SI5319B-C-GMR [SILICON]
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SILICON 
Si5319
PRELIMINARY DATA SHEET
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
Features
The Si5319 is a jitter-attenuating precision M/N clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input ranging
from 2 kHz to 710 MHz and generates one clock output
ranging from 2 kHz to 945 MHz and select frequencies to
1.4 GHz. The Si5319 can also use its crystal oscillator as a
clock source for frequency synthesis. The device provides
virtually any frequency translation combination across this
operating range. The Si5319 input clock frequency and clock
multiplication ratio are programmable through an I2C or SPI
interface. The Si5319 is based on Silicon Laboratories' 3rd-
generation DSPLL® technology, which provides any-rate
frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for external
VCXO and loop filter components. The DSPLL loop
bandwidth is digitally programmable, providing jitter
performance optimization at the application level. Operating
from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for
providing clock multiplication and jitter attenuation in high
performance timing applications.
ꢀ Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
ꢀ Ultra-low jitter clock outputs with jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
ꢀ Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
ꢀ Meets OC-192 GR-253-CORE jitter specifications
ꢀ Clock or crystal input with manual clock selection
ꢀ Clock output selectable signal format
(LVPECL, LVDS, CML, CMOS)
ꢀ Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
ꢀ Supports various frequency translations for
Synchronous Ethernet
ꢀ LOL, LOS alarm outputs
2
ꢀ I C or SPI programmable
ꢀ On-chip voltage regulator for 1.8 V ±5%, 2.5 or
Applications
3.3 V ±10% operation
ꢀ
SONET/SDH OC-48/STM-16 and OC-192/STM-64
line cards
ꢀ Small size: 6 x 6 mm 36-lead QFN
ꢀ Pb-free, ROHS compliant
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
Synchronous Ethernet
Test and measurement
Discrete PLL replacement
Broadcast video
Xtal or Refclock
XO
÷ NC1_LS
CKOUT
÷ N32
®
DSPLL
N1_HS
÷ N31
CKIN
÷ N2
VDD (1.8, 2.5, or 3.3 V)
GND
Loss of Signal
Loss of Lock
Control
Signal Detect
I2C/SPI Port
Xtal/Clock Select
Device Interrupt
Rate Select
Preliminary Rev. 0.3 1/08
Copyright © 2008 by Silicon Laboratories
Si5319
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5319
Table 1. Performance Specifications1
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
Test Condition
Min
–40
2.97
2.25
1.71
—
Typ
25
3.3
2.5
1.8
217
Max
85
3.63
2.75
1.89
243
Unit
ºC
V
V
V
T
A
V
DD
Supply Current
I
f
= 622.08 MHz
mA
DD
OUT
CKOUT enabled
LVPECL format output
= 19.44 MHz
f
—
194
220
mA
OUT
CKOUT enabled
CMOS format output
Tristate/Sleep Mode
—
0.002
165
—
TBD
710
mA
MHz
Input Clock Frequency
(CKIN)
CK
Input frequency and clock multi-
plication ratio determined by
programming device PLL divid-
ers. Consult Silicon Laboratories
configuration software DSPLL-
sim to determine PLL divider
settings for a given input fre-
quency/clock multiplication ratio
combination.
F
Output Clock Frequency
(CKOUT)
CK
0.002
970
1213
—
945
1134
1400
MHz
OF
3-Level Input Pins
Input Mid Current
Input Clock (CKIN)
Differential Voltage
Swing
I
See Note 2.
–2
—
—
2
µA
IMM
CKN
0.25
1.9
VPP
DPP
Common Mode Voltage CKN
1.8 V ±5%
2.5 V ±10%
3.3 V ±10%
0.9
1.0
1.1
—
40
2
—
—
—
—
—
—
1.4
1.7
1.95
11
60
—
V
V
V
ns
%
ns
VCM
Rise/Fall Time
CKN
20–80%
Whichever is smaller
TRF
Duty Cycle
CKN
DC
(Minimum Pulse Width)
Output Clock (CKOUT)
Common Mode
Differential Output Swing
Single Ended Output
Swing
V
V
V
LVPECL
100 Ω load
line-to-line
V
– 1.42
1.1
0.5
—
—
—
V – 1.25
DD
V
V
OCM
DD
1.9
0.93
OD
SE
Rise/Fall Time
Output Duty Cycle
CKO
20–80%
100 Ω load
—
—
230
—
350
±40
ps
ps
TRF
CKO
DC
Differential Uncertainty
line-to-line
measured at 50% point
Notes:
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
2
Preliminary Rev. 0.3
Si5319
Table 1. Performance Specifications1 (Continued)
(VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
PLL Performance
Jitter Generation
Symbol
Test Condition
Min
Typ
Max
Unit
J
f
= f = 622.08 MHz,
—
0.3
TBD
ps rms
GEN
IN
OUT
LVPECL output format
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
—
—
—
—
0.3
0.4
0.05
TBD
TBD
TBD
0.1
ps rms
ps rms
dB
Jitter Transfer
J
PK
External Reference Jitter J
Transfer
TBD
dB
PKEXTN
Phase Noise
CKO
f
= f = 622.08 MHz
OUT
—
TBD
TBD
dBc/Hz
PN
IN
100 Hz offset
1 kHz offset
10 kHz offset
100 kHz offset
1 MHz offset
—
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
Subharmonic Noise
Spurious Noise
SP
SP
Phase Noise @ 100 kHz Offset
Max spur @ n x F3
SUBH
SPUR
dBc
(n > 1, n x F3 < 100 MHz)
Package
Thermal Resistance
Junction to Ambient
Notes:
Theta JA
Still Air
—
38
—
ºC/W
1. For a more comprehensive listing of device specifications, consult the Silicon Laboratories Any-Rate Precision Clock
Family Reference Manual.
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
Manual. In most designs an external resistor voltage divider is recommended.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
V
–0.5 to 3.6
V
DD
DIG
JCT
STG
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
V
ºC
ºC
kV
V
DD
Operating Junction Temperature
T
–55 to 150
–55 to 150
2
Storage Temperature Range
T
ESD HBM Tolerance (100 pF, 1.5 kΩ), Except CKIN Pins
ESD HBM Tolerance (100 pF, 1.5 kΩ), CKIN Pins
ESD MM Tolerance, Except CKIN Pins
ESD MM Tolernace, CKIN Pins
700
200
V
150
V
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.3
3
Si5319
155.52 MHz in, 622.08 MHz out
0
-20
-40
-60
-80
-100
-120
-140
-160
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
Jitter Band
Jitter, RMS
1,279 fs
Brick Wall, 100 Hz to 100 MHz
SONET_OC48, 12 kHz to 20 MHz
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 MHz to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall, 800 Hz to 80 MHz
315 fs
335 fs
194 fs
318 fs
343 fs
4
Preliminary Rev. 0.3
Si5319
C4
C1
1 µF
System
Power
Supply
0.1 µF
Ferrite
Bead
C2
C3
0.1 µF
0.1 µF
VDD = 3.3 V
0.1 µF
130 Ω
82 Ω
130 Ω
82 Ω
CKOUT+
CKOUT–
+
–
CKIN+
100 Ω
CKIN–
0.1 µF
INT_CB
LOL
Interrupt/CKIN Invalid Indicator
PLL Loss of Lock Indicator
Serial Port Address
Si5319
XA
Option 1:
Crystal
XB
A[2:0]
SDA
SCL
Crystal/RefClk Rate
RATE[1:0]
I2C Interface
Serial Data
Serial Clock
0.1 µF
Option 2:
Refclk+
Refclk–
XA
0.1 µF
XB
CS
Xtal/Clock Select
Control Mode (L)
Reset
CMODE
RST
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
2
Figure 2. Si5319 Typical Application Circuit (I C Control Mode)
C4
C1
1 µF
System
Power
Supply
0.1 µF
Ferrite
Bead
C2
C3
0.1 µF
0.1 µF
VDD = 3.3 V
0.1 µF
130 Ω
82 Ω
130 Ω
82 Ω
CKOUT+
CKOUT–
+
–
CKIN+
100 Ω
CKIN–
0.1 µF
INT_CB
LOL
Interrupt/CLKIN Invalid Indicator
PLL Loss of Lock Indicator
Si5319
XA
Option 1:
Crystal
XB
SS
SDO
SDI
Slave Select
Crystal/RefClk Rate
RATE[1:0]
Serial Data Out
SPI Interface
0.1 µF
Option 2:
Serial Data In
Serial Clock
XA
Refclk+
0.1 µF
SCLK
CS
XB
Refclk–
Control Mode (H)
Reset
CMODE
RST
Xtal/Clock Select
*Note: Assumes differential LVPECL termination (3.3 V) on clock inputs.
Figure 3. Si5319 Typical Application Circuit (SPI Control Mode)
Preliminary Rev. 0.3
5
Si5319
1.1. External Reference
1. Functional Description
A low-cost 114.285 MHz 3rd overtone crystal or an
external reference oscillator is used as part of a fixed-
frequency oscillator within the DSPLL. This external
reference is required for the device to perform jitter
attenuation. Silicon Laboratories recommends using a
high quality crystal. Specific recommendations may be
found in the Family Reference Manual. An external
oscillator as well as other crystal frequencies can also
be used as a reference for the device.
The Si5319 is a jitter-attenuating precision clock
multiplier for applications requiring sub 1 ps jitter
performance. The Si5319 accepts one clock input
ranging from 2 kHz to 710 MHz and generates one
clock output ranging from 2 kHz to 945 MHz and select
frequencies to 1.4 GHz. The Si5319 can also use its
crystal oscillator as a clock source for frequency
synthesis. The device provides virtually any frequency
translation combination across this operating range.
The Si5319 input clock frequency and clock
In digital hold, the DSPLL remains locked to this
external reference. Any changes in the frequency of this
reference when the DSPLL is in digital hold will be
tracked by the output of the device. Note that crystals
can have temperature sensitivities.
2
multiplication ratio are programmable through an I C or
SPI interface. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5319. Additional design support
is available from Silicon Laboratories through your
distributor.
This
utility
can
be
downloaded
from
http://www.silabs.com/timing.
The Si5319 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
®
rate frequency synthesis and jitter attenuation in a
highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
Si5319 PLL loop bandwidth is digitally programmable
and supports a range from 60 Hz to 8.4 kHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
Silicon Laboratories has developed
a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
The Si5319 monitors the input clock for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on the input clock. The device monitors the lock
status of the PLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in
relation to the phase of the feedback clock.
The Si5319 provides a digital hold capability that allows
the device to continue generation of a stable output
clock when the selected input reference is lost. During
digital hold, the DSPLL freezes its VCO settings and
uses its XO as its frequency reference.
The Si5319 has one differential clock output. The
electrical format of the clock output is programmable to
support LVPECL, LVDS, CML, or CMOS loads. For
system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
6
Preliminary Rev. 0.3
Si5319
2. Pin Descriptions: Si5319
36 35 34 33 32 31 30 29 28
RST
NC
1
2
3
4
5
6
7
8
9
27 SDI
26
A2_SS
25 A1
INT_CB
NC
24
23
A0
GND
Pad
VDD
XA
SDA_SDO
22 SCL
XB
21
20
19
CS
GND
NC
GND
GND
10 11 12 13 14 15 16 17 18
Pin numbers are preliminary and subject to change.
Pin # Pin Name I/O Signal Level
Description
External Reset.
1
I
LVCMOS
RST
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device regis-
ters to their default value. Clock outputs are disabled during reset. The
part must be programmed after a reset or power-on to get a clock out-
put. See Family Reference Manual for details.
This pin has a weak pull-up.
No Connect.
2, 4, 9,
12–14,
30,
NC
—
O
—
This pin must be left unconnected for normal operation.
33–35
Interrupt/CKIN Invalid Indicator.
3
INT_CB
LVCMOS
This pin functions as a device interrupt output or an alarm output for
CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin
functions as a maskable interrupt output with active polarity controlled
by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS alarm indicator
for CKIN. Set CK_BAD_PIN = 1 and INT_PIN = 0.
0 = CKIN present.
1 = LOS on CKIN.
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
Preliminary Rev. 0.3
7
Si5319
Pin # Pin Name I/O Signal Level
Description
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-
tors should be associated with the following V pins:
5, 10,
32
V
V
Supply
DD
DD
DD
5
10
32
0.1 µF
0.1 µF
0.1 µF
A 1.0 µF should also be placed as close to the device as is practical.
External Crystal or Reference Clock.
7
6
XB
XA
I
Analog
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to the Family Reference Manual for
interfacing to an external reference. The external reference must be
from a high-quality clock source (TCXO, OCXO). Frequency of crystal
or external clock is set by the RATE pins.
Ground.
8, 31
GND
I
Supply
3-Level
GND
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
External Crystal or Reference Clock Rate.
11
15
RATE0
RATE1
Three level inputs that select the type and rate of external crystal or
reference clock to be applied to the XA/XB port. Refer to the Family
Reference Manual for settings. These pins have both a weak pull-up
and a weak pull-down; they default to M. The "HH" setting is not sup-
ported.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Input.
16
17
CKIN+
CKIN–
I
Multi
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
PLL Loss of Lock Indicator.
18
LOL
O
LVCMOS
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the
LOL_POL bit. The PLL lock status will always be reflected in the
LOL_INT read only register bit.
Xtal/Input Clock Select.
21
22
CS
I
I
LVCMOS
LVCMOS
This pin selects the active DSPLL input clock, which can be a clock
input or a crystal input. See the FREE_EN register for free run settings.
0 = Select clock input (CKIN).
1 = Select crystal input.
This pin should not be left open.
Serial Clock/Serial Clock.
SCL
2
This pin functions as the serial clock input for both SPI and I C modes.
This pin has a weak pull-down.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
8
Preliminary Rev. 0.3
Si5319
Pin # Pin Name I/O Signal Level
Description
Serial Data.
23
SDA_SDO I/O
LVCMOS
LVCMOS
LVCMOS
2
In I C control mode (CMODE = 0), this pin functions as the bidirec-
tional serial data port.
In SPI control mode (CMODE = 1), this pin functions as the serial data
output.
Serial Port Address.
25
24
A1
A0
I
I
2
In I C control mode (CMODE = 0), these pins function as hardware
2
controlled address bits. The I C address is 1101 [A2] [A1] [A0].
In SPI control mode (CMODE = 1), these pins are ignored.
These pins have a weak pull-down.
Serial Port Address/Slave Select.
26
27
A2_SS
2
In I C control mode (CMODE = 0), this pin functions as a hardware
controlled address bit [A2].
In SPI control mode (CMODE = 1), this pin functions as the slave
select input.
This pin has a weak pull-down.
Serial Data In.
SDI
I
LVCMOS
Multi
2
In I C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the serial data
input.
This pin has a weak pull-down.
Output Clock.
29
28
CKOUT–
CKOUT+
O
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by SFOUT1_REG regis-
ter bits. Output is differential for LVPECL, LVDS, and CML compatible
modes. For CMOS format, both output pins drive identical single-
ended clock outputs.
Control Mode.
36
CMODE
I
LVCMOS
Supply
2
Selects I C or SPI control mode for the Si5319.
2
0 = I C Control Mode
1 = SPI Control Mode
Ground Pad.
GND
PAD
GND
GND
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).
Preliminary Rev. 0.3
9
Si5319
3. Ordering Guide
Ordering Part
Output Clock
Frequency Range
ROHS6,
Pb-Free
Package
Temperature Range
Number
Si5319A-C-GM
2 kHz–945 MHz
970–1134 MHz
1.213–1.417 GHz
36-Lead 6 x 6 mm QFN
Yes
–40 to 85 °C
Si5319B-C-GM
Si5319C-C-GM
2 kHz–808 MHz
2 kHz–346 MHz
36-Lead 6 x 6 mm QFN
36-Lead 6 x 6 mm QFN
Yes
Yes
–40 to 85 °C
–40 to 85 °C
10
Preliminary Rev. 0.3
Si5319
4. Package Outline: 36-Pin QFN
Figure 4 illustrates the package details for the Si5319. Table 3 lists the values for the dimensions shown in the
illustration.
Figure 4. 36-Pin Quad Flat No-lead (QFN)
Table 3. Package Dimensions
Symbol
Millimeters
Nom
Symbol
Millimeters
Min
0.80
0.00
0.18
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.70
12º
A
A1
b
0.85
L
0.02
θ
0.25
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.08
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Preliminary Rev. 0.3
11
Si5319
5. Recommended PCB Layout
Figure 5. PCB Land Pattern Diagram
12
Preliminary Rev. 0.3
Si5319
Table 4. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Preliminary Rev. 0.3
13
Si5319
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
ꢀ Changed 1.8 V operating range to ±5%.
ꢀ Updated Table 1 on page 2.
ꢀ Updated Table 2 on page 3.
ꢀ Added table under Figure 1 on page 4.
ꢀ Updated "1. Functional Description" on page 6.
ꢀ Clarified "2. Pin Descriptions: Si5319" on page 7.
Revision 0.2 to Revision 0.3
ꢀ Updated "2. Pin Descriptions: Si5319" on page 7.
ꢁ Corrected Pins 11 and 15 description in table.
14
Preliminary Rev. 0.3
Si5319
NOTES:
Preliminary Rev. 0.3
15
Si5319
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
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Preliminary Rev. 0.3
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