SI5319C-C-GM_技术文档

Si5319

ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Features



Generates any frequency from 2 kHz to 945 MHz and

select frequencies to 1.4 GHz from an input frequency of

2 kHz to 710 MHz

Ultra-low jitter clock output with jitter generation as low as

0.3 ps rms (50 kHz–80 MHz)

Integrated loop filter with selectable loop bandwidth

(60 Hz to 8.4 kHz)

Meets OC-192 GR-253-CORE jitter specifications

Clock or crystal input with manual clock selection

Selectable clock output signal format



Support for ITU G.709 and custom OTN FEC ratios (e.g.

255/238, 255/237, 255/236)

Supports various frequency translations for Synchronous

Ethernet

LOL, LOS alarm outputs

I²C or SPI programmable

On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10% or

3.3 V ±10% operation

Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS compliant



(LVPECL, LVDS, CML, CMOS)

Applications



10G/40G/100G OTN line cards

SONET/SDH OC-48/STM-16 and OC-192/STM-64

line cards

GbE/10GbE, 1/2/4/8/10GFC line cards

ITU G.709 and custom FEC line cards

Synchronous Ethernet



Wireless basestations

Data converter clocking

DSLAM/MSANs

Test and measurement

Broadcast video



Discrete PLL replacement

Optical modules

Description

The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The

Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz

and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for free-running clock

generation. The device provides virtually any frequency translation combination across this operating range. The Si5319 input

clock frequency and clock multiplication ratio are programmable through an I²C or SPI interface. The Si5319 is based on Silicon

Laboratories' third-generation DSPLL^®technology, which provides any-frequency synthesis and jitter attenuation in a highly

integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is

digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or

3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.

Rev. 1.0 12/10

Si5319

2

Rev. 1.0

Si5319

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5. Pin Descriptions: Si5319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

7. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

9. Si5319 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Rev. 1.0

3

Si5319

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Ambient Temperature

T

-40

25

85

°C

V

A

Supply Voltage during

Normal Operation

V

3.3 V Nominal

2.97

3.3

3.63

DD

2.5 V Nominal

1.8 V Nominal

2.25

1.71

2.5

1.8

2.75

1.89

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.

Figure 1. Differential Voltage Characteristics

Figure 2. Rise/Fall Time Characteristics

4

Rev. 1.0

Si5319

Table 2. DC Characteristics

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

1

Supply Current

I

LVPECL Format

622.08 MHz Out

—

217

243

mA

DD

CMOS Format

19.44 MHz Out

—

194

165

220

—

mA

Disable Mode

2

CKIN Input Pin

Input Common Mode

Voltage (Input Thresh-

old Voltage)

V

1.8 V ± 5%

2.5 V ± 10%

3.3 V ± 10%

Single-ended

0.9

1

—

40

—

1.4

1.7

1.95

60

V

ICM

1.1

20

0.2

V

Input Resistance

CKN

kΩ

RIN

Single-Ended Input

Voltage Swing

(See Absolute Specs)

V

f

< 212.5 MHz

—

V

ISE

CKIN

PP

See Figure 1.

> 212.5 MHz

0.25

0.2

—

CKIN

See Figure 1.

< 212.5 MHz

CKIN

Differential Input

Voltage Swing

(See Absolute Specs)

V

ID

See Figure 1.

> 212.5 MHz

0.25

CKIN

See Figure 1.

3

Output Clock (CKOUT)

Common Mode

CKO

LVPECL 100  load

V

–1.42

—

V –1.25

DD

V

VCM

DD

line-to-line

Differential Output

Swing

CKO

LVPECL 100  load

1.1

0.5

350

1.9

0.93

500

V

VD

PP

line-to-line

Single Ended Output

Swing

LVPECL 100  load

—

V

VSE

line-to-line

Differential Output

Voltage

CKO

CML 100  load line-to-

425

mV

PP

VD

line

Notes:

1. Current draw is independent of supply voltage.

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal V ≥ 2.5 V.

DD

4. This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Rev. 1.0

5

Si5319

Table 2. DC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

– 0.36

DD

Max

Unit

Common Mode Output

Voltage

CKO

CML 100  load line-to-

—

V

—

V

VCM

line

Differential Output

Voltage

CKO

LVDS

100  load line-to-line

500

350

700

425

1.2

900

500

1.275

—

mV

VD

PP

Low Swing LVDS

100  load line-to-line

Common Mode Output

Voltage

LVDS 100 load line-

1.125

V

VCM

to-line

Differential Output

Resistance

CKO

CML, LVPECL, LVDS

—

200



RD

Output Voltage Low

CKO

CMOS

—

0.4

—

V

VOLLH

Output Voltage High

V

= 1.71 V

0.8 x V

—

VOHLH

DD

CMOS

ICMOS[1:0] =11

= 1.8 V

Output Drive Current

(CMOS driving into

CKO

7.5

5.5

3.5

1.75

32

—

mA

IO

V

DD

CKO

for output low

VOL

ICMOS[1:0] =10

= 1.8 V

—

or CKO

for output

VOH

V

DD

high. CKOUT+ and

CKOUT– shorted

externally)

ICMOS[1:0] =01

= 1.8 V

—

V

DD

ICMOS[1:0] =00

= 1.8 V

—

V

DD

ICMOS[1:0] =11

= 3.3 V

—

V

DD

ICMOS[1:0] =10

= 3.3 V

—

24

V

DD

ICMOS[1:0] =01

= 3.3 V

—

16

V

DD

ICMOS[1:0] =00

= 3.3 V

—

8

V

DD

Notes:

1. Current draw is independent of supply voltage.

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal V ≥ 2.5 V.

DD

4. This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

6

Rev. 1.0

Si5319

Table 2. DC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

2-Level LVCMOS Input Pins

Input Voltage Low

Input Voltage High

V

= 1.71 V

= 2.25 V

= 2.97 V

= 1.89 V

= 2.25 V

= 3.63 V

—

0.5

0.7

0.8

—

V

IL

DD

—

V

1.4

1.8

2.5

IH

—

4

3-Level Input Pins

Input Voltage Low

V

—

0.15 x V

0.55 x V

V

ILL

DD

Input Voltage Mid

Input Voltage High

V

0.45 x

IMM

DD

V

DD

V

0.85 x

—

V

IHH

V

DD

Input Low Current

Input Mid Current

Input High Current

I

See Note 4

–20

–2

—

+2

20

μA

ILL

I

IMM

I

—

IHH

LVCMOS Output Pins

Output Voltage Low

V

IO = 2 mA

—

0.4

V

OL

V

= 1.71 V

DD

Output Voltage Low

IO = 2 mA

= 2.97 V

V

DD

Notes:

1. Current draw is independent of supply voltage.

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal V ≥ 2.5 V.

DD

4. This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Rev. 1.0

7

Si5319

Table 2. DC Characteristics (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Voltage High

V

IO = –2 mA

V

–0.4

—

V

OH

DD

V

= 1.71 V

DD

Output Voltage High

IO = –2 mA

= 2.97 V

–0.4

—

V

DD

V

DD

Disabled Leakage

Current

I

RSTb = 0

–100

100

μA

OZ

Notes:

1. Current draw is independent of supply voltage.

2. No under- or overshoot is allowed.

3. LVPECL outputs require nominal V ≥ 2.5 V.

DD

4. This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.

Table 3. Microprocessor Control

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

2

I C Bus Lines (SDA, SCL)

Input Voltage Low

VIL

—

0.7 x V

–10

—

0.25 x V

V

I2C

DD

Input Voltage High

Input Current

VIH

V

DD

I2C

DD

II

VIN = 0.1 x V

10

μA

I2C

DD

to 0.9 x V

DD

Hysteresis of Schmitt

trigger inputs

VHYS

V

= 1.8V

DD

0.1 x V

—

V

I2C

DD

V

= 2.5 or 3.3 V

0.05 x V

—

DD

Output Voltage Low

VOL

V

= 1.8 V

0.2 x V

DD

I2C

DD

IO = 3 mA

= 2.5 or 3.3 V

IO = 3 mA

—

0.4

V

SPI Specifications

Duty Cycle, SCLK

Cycle Time, SCLK

Rise Time, SCLK

Fall Time, SCLK

t

SCLK = 10 MHz

40

100

—

60

—

25

%

ns

DC

t

c

t

20–80%

r

t

—

f

8

Rev. 1.0

Si5319

Table 3. Microprocessor Control (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Low Time, SCLK

t

20–20%

30

—

ns

lsc

High Time, SCLK

t

80–80%

30

—

ns

hsc

Delay Time, SCLK Fall

to SDO Active

t

25

d1

d2

d3

Delay Time, SCLK Fall

to SDO Transition

t

—

25

20

25

20

25

—

25

—

ns

Delay Time, SS Rise

to SDO Tri-state

t

Setup Time, SS to

SCLK Fall

t

su1

Hold Time, SS to

SCLK Rise

t

h1

Setup Time, SDI to

SCLK Rise

su2

Hold Time, SDI to

SCLK Rise

t

h2

Delay Time between

Slave Selects

t

cs

Table 4. AC Specifications

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Single-Ended Reference Clock Input Pin XA (XB with cap to GND)

Input Resistance

XA

RATE[1:0] = LM or MH, ac

coupled

—

12

—

k

RIN

Input Voltage Swing

XA

RATE[1:0] = LM or MH, ac

coupled

0.5

1.2

V

PP

VPP

Differential Reference Clock Input Pins (XA/XB)

Input Voltage Swing

XA/XB

RATE[1:0] = LM or MH

0.5

—

1.2

V ,

each.

VPP

PP

CKIN Input Pins

Input Frequency

CKN

0.002

710

MHz

F

Rev. 1.0

9

Si5319

Table 4. AC Specifications (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Input Duty Cycle

(Minimum Pulse

Width)

CKN

Whichever is smaller

(i.e., the 40% / 60%

limitation applies only

to high-frequency

clocks)

40

—

60

%

DC

2

—

ns

Input Capacitance

Input Rise/Fall Time

CKN

—

3

pF

ns

CIN

CKN

20–80%

11

TRF

See Figure 2

CKOUT Output Pins

(See ordering section for speed grade vs frequency limits)

Output Frequency

(Output not config-

ured for CMOS or

Disabled)

CKO

N1  6

N1 = 5

N1 = 4

0.002

970

—

945

1134

1.4

MHz

GHz

MHz

F

1.213

—

Maximum Output

Frequency in CMOS

Format

212.5

F

Output Rise/Fall

(20–80 %) @

622.08 MHz output

CKO

Output not configured for

CMOS or Disabled

See Figure 2

—

230

—

350

8

ps

ns

ps

TRF

Output Rise/Fall

(20–80%) @

212.5 MHz output

CMOS Output

TRF

V

= 1.71

DD

C

= 5 pF

LOAD

Output Rise/Fall

(20–80%) @

212.5 MHz output

CMOS Output

= 2.97

—

2

V

DD

C

= 5 pF

LOAD

Output Duty Cycle

Uncertainty @

622.08 MHz

CKO

100  Load

Line-to-Line

Measured at 50% Point

(Not for CMOS)

—

+/-40

DC

LVCMOS Input Pins

Minimum Reset Pulse

Width

t

1

—

10

3

μs

ms

pF

RSTMN

Reset to Microproces-

sor Access Ready

t

—

READY

Input Capacitance

C

in

10

Rev. 1.0

Si5319

Table 4. AC Specifications (Continued)

(V_DD= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

LVCMOS Output Pins

Rise/Fall Times

t

C

= 20pf

—

25

—

ns

RF

LOAD

See Figure 2

LOSn Trigger Window

LOS

From last CKINn to 

Internal detection of LOSn

N3 ≠ 1

4.5 x N3

—

T

CKIN

TRIG

Time to Clear LOL

after LOS Cleared

t

LOS to LOL

Fold = Fnew

Stable Xa/XB reference

—

10

ms

CLRLOL

Device Skew

Input to Output Phase

Change Due to Tem-

perature Variation

t

Max phase changes from

–40 to +85 °C

300

500

ps

TEMP

PLL Performance

(fin=fout = 622.08 MHz; BW=120 Hz; LVPECL)

Lock Time

t

Start of ICAL to of LOL

—

35

1200

—

ms

ps

LOCKMP

Output Clock Phase

Change

t

After clock switch

200

P_STEP

f3  128 kHz

Closed Loop Jitter

Peaking

J

—

0.05

—

0.1

—

dB

PK

Jitter Tolerance

J

Jitter Frequency Loop

5000/BW

ns pk-pk

TOL

Bandwidth

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

—

–106

–121

–132

–88

–87

–100

–104

–119

–76

dBc/Hz

dBc

Phase Noise

fout = 622.08 MHz

CKO

PN

Subharmonic Noise

Spurious Noise

SP

Phase Noise @ 100 kHz

Offset

SUBH

SPUR

Max spur @ n x F3

—

–93

–70

dBc

(n  1, n x F3 < 100 MHz)

Rev. 1.0

11

Si5319

Table 5. Jitter Generation

*

Parameter

Symbol

Min

Typ

Max

GR-253-

Specification

Unit

Test Condition

Measurement

Filter

DSPLL

2

BW

Jitter Gen

OC-192

J

0.02–80 MHz

120 Hz

—

4.2

0.27

3.7

6.2

0.42

6.4

30

N/A

10

ps

PP

GEN

ps

rms

4–80 MHz

ps

PP

0.14

4.4

0.31

6.9

N/A

10

ps

rms

0.05–80 MHz

0.12–20 MHz

ps

PP

0.26

3.5

0.41

5.4

1.0

ps

rms

PP

Jitter Gen

OC-48

J

40.2

4.02

ps

GEN

0.27

0.41

rms

*Note: Test conditions:

1. fIN = fOUT = 622.08 MHz

2. Clock input: LVPECL

3. Clock output: LVPECL

4. PLL bandwidth: 120 Hz

5. 114.285 MHz 3rd OT crystal used as XA/XB input

6. V_DD= 2.5 V

7. T_A= 85 °C

Table 6. Thermal Characteristics

(V_DD= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A= –40 to 85 °C)

Parameter

Symbol

Test Condition

Value

Unit

Thermal Resistance Junction to Ambient



Still Air

32

C°/W

JA

JC

Thermal Resistance Junction to Case



Still Air

14

C°/W

12

Rev. 1.0

Si5319

Table 7. Absolute Maximum Limits

Parameter

Symbol

Test Condition

Min

Typ

Max

3.8

Unit

DC Supply Voltage

V

–0.5

—

V

DD

LVCMOS Input Voltage

V

–0.3

0

V

+0.3

DD

V

DIG

CKINn Voltage Level Limits

XA/XB Voltage Level Limits

CKN

—

V

DD

VIN

XA

0

1.2

V

VIN

Operating Junction Tempera-

ture

T

–55

150

ºC

JCT

Storage Temperature Range

T

–55

2

—

150

—

ºC

kV

STG

ESD HBM Tolerance

(100 pF, 1.5 k); All pins except

CKIN+/CKIN–

ESD MM Tolerance; All pins

except CKIN+/CKIN–

150

750

100

—

V

ESD HBM Tolerance

(100 pF, 1.5 k); CKIN+/CKIN–

ESD MM Tolerance;

CKIN+/CKIN–

Latch-up Tolerance

JESD78 Compliant

Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods of time may affect device reliability.

Rev. 1.0

13

Si5319

2. Typical Phase Noise Plots

The following typical phase noise plot was taken using a Rohde and Schwarz SML03 RF Generator as the clock

input source to the Si5326. The Agilent model E5052B was used for the phase noise measurement. For this

measurement, the Si5319 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled

differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is

below the loop BW is caused by the jitter at the input clock. The loop BW was 120 Hz.

2.1. Example: SONET OC-192

Figure 3. Typical Phase Noise Plot

T

Jitter Band

Jitter, RMS

SONET_OC48, 12 kHz to 20 MHz

250 fs

SONET_OC192_A, 20 kHz to 80 MHz

SONET_OC192_B, 4 to 80 MHz

SONET_OC192_C, 50 kHz to 80 MHz

Brick Wall, 800 Hz to 80 MHz

274 fs

166 fs

267 fs

274 fs

14

Rev. 1.0

Si5319

2

Figure 4. Si5319 Typical Application Circuit (I C Control Mode)

Figure 5. Si5319 Typical Application Circuit (SPI Control Mode)

Rev. 1.0

15

Si5319

3. Functional Description

The Si5319 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.

The Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from

2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock

source for frequency synthesis. The device provides virtually any frequency translation combination across this

2

operating range. The Si5319 input clock frequency and clock multiplication ratio are programmable through an I C

or SPI interface. Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine

the optimum PLL divider settings for a given input frequency/clock multiplication ratio combination that minimizes

phase noise and power consumption. This utility can be downloaded from http://www.silabs.com/timing.

®

The Si5319 is based on Silicon Laboratories' third generation DSPLL technology, which provides any-frequency

synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and

loop filter components. The Si5319 PLL loop bandwidth is digitally programmable and supports a range from 60 Hz

to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input

clock frequency/clock multiplication ratio.

The Si5319 monitors the input clock for loss-of-signal and provides a LOS alarm when it detects missing pulses on

the input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously

monitoring the phase of the input clock in relation to the phase of the feedback clock.

The Si5319 provides a VCO freeze capability that allows the device to continue generation of a stable output clock

when the selected input reference is lost. During VCO freeze, the DSPLL latches its VCO settings and uses its XO

as its frequency reference.

The Si5319 has one differential clock output. The electrical format of the clock output is programmable to support

LVPECL, LVDS, CML, or CMOS loads. For system-level debugging, a bypass mode is available which drives the

output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8,

2.5, or 3.3 V supply.

3.1. External Reference

A low-cost 114.285 MHz 3rd overtone crystal or an external reference oscillator is used as part of a fixed-frequency

oscillator within the DSPLL. This external reference is required for the device to operate. Silicon Laboratories

recommends using a high quality crystal. Specific recommendations may be found in the Family Reference

Manual. An external oscillator as well as other crystal frequencies can also be used as a reference for the device.

In VCO Freeze, the DSPLL remains locked to this external reference. Any changes in the frequency of this

reference when the DSPLL is in VCO freeze will be tracked by the output of the device. Note that crystals can have

temperature sensitivities.

3.2. Further Documentation

Consult the Silicon Laboratories Any-Frequency Precision Clock Family Reference Manual (FRM) for detailed

information about the Si5319. Additional design support is available from Silicon Laboratories through your

distributor.

Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration,

including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from

http://www.silabs.com/timing.

16

Rev. 1.0

Si5319

4. Register Map

All register bits that are not defined in this map should always be written with the specified Reset Values. The

writing to these bits of values other than the specified Reset Values may result in undefined device behavior. Do

not write to registers not listed in the register map, such as Register 64.

Register

D7

D6

D5

D4

D3

D2

D1

D0

0

FREE_RUN

CKOUT_

ALWAYS_

ON

BYPASS_

REG

2

3

BWSEL_REG[3:0]

VCO_

SQ_ICAL

FREEZE

5

ICMOS[1:0]

6

SFOUT1_REG[2:0]

8

HLOG[1:0]

10

11

19

20

22

23

24

25

31

32

33

40

41

42

43

44

45

46

47

48

DSBL_ REG

PD_CK

VALTIME[1:0]

LOCK[T2:0]

LOL_PIN

INT_PIN

INT_POL

LOL_POL

LOS_MSK LOSX_MSK

LOL_MSK

N1_HS[2:0]

N2_HS[2:0]

NC1_LS[19:16]

NC1_LS[15:8]

NC1_LS[7:0]

N2_LS[19:16]

N2_LS[15:8]

N2_LS[7:0]

N31[18:16]

N31[15:8]

N31[7:0]

N32[18:16]

N32[15:8]

N32[7:0]

Rev. 1.0

17

Si5319

Register

D7

D6

D5

D4

D3

D2

D1

D0

128

CK_ACT-

V_REG

129

130

131

132

134

135

136

138

LOS_INT

LOSX_INT

LOL_INT

LOS_FLG

LOL_FLG

LOSX_FLG

PARTNUM_RO[11:4]

PARTNUM_RO[3:0]

ICAL

REVID_RO[3:0]

GRADE_RO[1:0]

RST_REG

LOS_EN

[1:1]

139

185

LOS_EN

[0:0]

NVM_REVID[7:0]

18

Rev. 1.0

Si5319

Register 0.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

FREE_

RUN

CKOUT_

ALWAYS_

ON

BYPASS_

REG

Type

R

R/W

R

R/W

R

Reset value = 0001 0100

Bit

7

Name

Function

Reserved

Reserved.

6

FREE_RUN Free Run.

Internal to the device, route XA/XB to CKIN2. This allows the device to lock to its XA-XB

reference (either internal or external).

0: Disable

1: Enable

5

CKOUT_

CKOUT Always On.

ALWAYS_ON This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on

and ICAL is not complete or successful. See Table 9 on page 39.

0: Squelch output until part is calibrated (ICAL).

1: Device generates output clock, including during calibration. Note: The frequency may

be significantly off until the part is calibrated.

4:2

1

Reserved

Reserved.

BYPASS_

REG

Bypass Register.

This bit enables or disables the PLL bypass mode. Use only when the device is in VCO_-

FREEZE or before the first ICAL. Bypass mode is not supported for CMOS output clocks.

0: Normal operation

1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.

0

Reserved

Reserved.

Rev. 1.0

19

Si5319

Register 2.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

BWSEL_REG [3:0]

R/W

Reserved

R

Reset value = 0100 0010

Bit

Name

BWSEL_REG BWSEL_REG.

Function

7:4

[3:0]

Selects nominal f3dB bandwidth for PLL. See the DSPLLsim for settings. After

BWSEL_REG is written with a new value, an ICAL is required for the change to take

effect.

3:0

Reserved

Reserved.

Register 3.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

R

VCO_

FREEZE

SQ_ICAL

Reserved

R

Type

R/W

Reset value = 0000 0101

Bit

7:6

5

Name

Function

Reserved

Reserved.

VCO_

VCO_FREEZE.

FREEZE

Forces the part into VCO Freeze. This bit overrides all other manual and automatic clock

selection controls.

0: Normal operation.

1: Force VCO Freeze mode. Overrides all other settings and ignores the quality of all of

the input clocks.

4

SQ_ICAL

Reserved

SQ_ICAL.

This bit determines if the output clocks will remain enabled or be squelched (disabled)

during an internal calibration. See Table 9 on page 39.

0: Output clocks enabled during ICAL.

1: Output clocks disabled during ICAL.

3:0

Reserved.

20

Rev. 1.0

Si5319

Register 5.

Bit

D7

ICMOS [1:0]

R/W

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reserved

R

Reset value = 1110 1101

Bit

Name

Function

7:6

ICMOS [1:0] ICMOS [1:0].

When the output buffer is set to CMOS mode, these bits determine the output buffer drive

strength. The first number below refers to 3.3 V operation; the second to 1.8 V operation.

These values assume CKOUT+ is tied to CKOUT-.

00: 8 mA/2 mA.

01: 16 mA/4 mA

10: 24 mA/6 mA

11: 32 mA/ 8mA

5:0

Reserved

Reserved.

Register 6.

Bit

D7

D6

D5

D4

Reserved

R

D3

D2

D1

SFOUT_REG [2:0]

R/W

D0

Name

Type

Reserved

R

Reset value = 0010 1101

Bit

7:3

2:0

Name

Function

Reserved

Reserved.

SFOUT_

SFOUT_REG [2:0].

REG [2:0]

Controls output signal format and disable for CKOUT output buffer. Bypass mode is not

supported for CMOS output clocks.

000: Reserved

001: Disable

010: CMOS

011: Low swing LVDS

100: Reserved

101: LVPECL

110: CML

111: LVDS

Rev. 1.0

21

Si5319

Register 8.

Bit

D7

D6

D5

HLOG[1:0]

R/W

D4

D3

D2

D1

D0

Name

Type

Reserved

R

Reserved

R

Reset value = 0000 0000

Bit

7:6

5:4

Name

Function

Reserved

Reserved.

HLOG [1:0].

00: Normal operation.

01: Holds CKOUT output at static logic 0. Entrance and exit from this state will occur

without glitches or runt pulses.

10: Holds CKOUT output at static logic 1. Entrance and exit from this state will occur

without glitches or runt pulses.

11: Reserved.

3:0

Reserved

Reserved.

Register 10.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

DSBL_

REG

Reserved

R

Type

R

R/W

Reset value = 0000 0000

Bit

7:3

2

Name

Function

Reserved

Reserved.

DSBL_REG DSBL_REG.

This bit controls the powerdown of the CKOUT output buffer. If disable mode is selected,

the NC_LS output divider is also powered down.

0: CKOUT enabled.

1: CKOUT disabled.

1:0

Reserved

Reserved.

22

Rev. 1.0

Si5319

Register 11.

Bit

D7

D6

D5

D4

Reserved

R

D3

D2

D1

D0

PD_CK

R/W

Name

Type

Reset value = 0100 0000

Bit

7:1

0

Name

Reserved

PD_CK

Function

Reserved.

PD_CK.

This bit controls the powerdown of the CKIN input buffer.

0: CKIN enabled.

1: CKIN disabled.

Register 19.

Bit

D7

D6

Reserved

R

D5

D4

VALTIME [1:0]

R/W

D3

D2

D1

D0

Name

Type

LOCKT [2:0]

R/W

Reset value = 0010 1100

Bit

Name

Function

7:5

FOS_EN

Reserved.

4:3 VALTIME [1:0] VALTIME [1:0].

Sets amount of time for input clock to be valid before the associated alarm is removed.

00: 2 ms

01: 100 ms

10: 200 ms

11: 13 seconds

2:0

LOCKT [2:0] LOCKT [2:0].

Sets retrigger interval for one shot monitoring phase detector output. One shot is trig-

gered by a phase slip in the DSPLL. Refer to the Family Reference Manual for more

details.

000: 106 ms

001: 53 ms

010: 26.5 ms

011: 13.3 ms

100: 6.6 ms

101: 3.3 ms

110: 1.66 ms

111: .83 ms

Rev. 1.0

23

Si5319

Register 20.

Bit

D7

D6

D5

D4

D3

D2

D1

LOL_PIN

R/W

D0

INT_PIN

R/W

Name

Reserved

R

Type

Reset value = 0011 1110

Bit

7:2

1

Name

Function

Reserved

LOL_PIN

Reserved.

LOL_PIN.

The LOL_INT status bit can be reflected on the LOL output pin.

0: LOL output pin tristated

1: LOL_INT status reflected to output pin

0

INT_PIN

INT_PIN.

Reflects the interrupt status on the INT_CB output pin.

0: Interrupt status not displayed on INT_CB output pin. If CK1_BAD_PIN = 0, INT_CB

output pin is tristated.

1: Interrupt status reflected to output pin. Instead, the INT_CB pin indicates when CKIN is

bad.

Register 22.

Bit

D7

D6

D5

D4

D3

D2

D1

LOL_POL

R/W

D0

INT_POL

R/W

Name

Type

Reserved

R

Reset value = 1101 1111

Bit

7:2

2

Name

Function

Reserved

Reserved.

CK_BAD_

POL

CK_BAD_POL.

Sets the active polarity for the INT_CB and C2B signals when reflected on output pins.

0: Active low

1: Active high

1

0

LOL_POL

INT_POL

LOL_POL.

Sets the active polarity for the LOL status when reflected on an output pin.

0: Active low

1: Active high

INT_POL.

Sets the active polarity for the interrupt status when reflected on the INT_CB output pin.

0: Active low

1: Active high

24

Rev. 1.0

Si5319

Register 23.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

R

LOS_ MSK

LOSX_

MSK

Type

R/W

Reset value = 0001 1111

Bit

7:2

1

Name

Function

Reserved

Reserved.

LOS_MSK LOS_MSK.

Determines if a LOS on CKIN (LOS_FLG) is used in the generation of an interrupt. Writes

to this register do not change the value held in the LOS_FLG register.

0: LOS alarm triggers active interrupt on INT_CB output (if INT_PIN=1).

1: LOS_FLG ignored in generating interrupt output.

0

LOSX_MSK LOSX_MSK.

Determines if a LOS on XA/XB(LOSX_FLG) is used in the generation of an interrupt.

Writes to this register do not change the value held in the LOSX_FLG register.

0: LOSX alarm triggers active interrupt on INT_CB output (if INT_PIN=1).

1: LOSX_FLG ignored in generating interrupt output.

Register 24.

Bit

D7

D6

D5

D4

Reserved

R

D3

D2

D1

D0

LOL_MSK

R/W

Name

Type

Reset value = 0011 1111

Bit

7:2

0

Name

Function

Reserved

LOL_MSK

Reserved.

LOL_MSK.

Determines if the LOL_FLG is used in the generation of an interrupt. Writes to this regis-

ter do not change the value held in the LOL_FLG register.

0: LOL alarm triggers active interrupt on INT_CB output (if INT_PIN=1).

1: LOL_FLG ignored in generating interrupt output.

Rev. 1.0

25

Si5319

Register 25.

Bit

D7

D6

N1_HS [2:0]

R/W

D5

D4

D3

D2

Reserved

R

D1

D0

Name

Type

Reset value = 0010 0000

Bit

Name

Function

7:5

N1_HS [2:0] N1_HS [2:0].

Sets value for N1 high speed divider which drives NC1_LS low-speed divider.

000: N1= 4

001: N1= 5

010: N1=6

011: N1= 7

100: N1= 8

101: N1= 9

110: N1= 10

111: N1= 11

4:0

Reserved

Reserved.

Register 31.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

Reserved

R

NC1_LS [19:16]

R/W

Reset value = 0000 0000

Bit

7:4

3:0

Name

Function

Reserved

Reserved.

NC1_LS [19:16].

NC1_LS

[19:16]

Sets value for NC1_LS divider, which drives CKOUT output. The value of the register

must be either odd or zero.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

26

Rev. 1.0

Si5319

Register 32.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

NC1_LS [15:8]

R/W

Reset value = 0000 0000

Bit

Name

Function

7:0

NC1_LS

[15:8]

NC1_LS [15:8].

Sets value for NC1_LS, which drives CKOUT output. The value of the register must be

either odd or zero.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Register 33.

Bit

D7

D6

D5

D4

NC1_LS [7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0011 0001

Bit

Name

Function

7:0

NC1_LS

[19:0]

NC1_LS [7:0].

Sets value for NC1_LS, which drives CKOUT output. The value of the register must be

either odd or zero.

00000000000000000000 = 1

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111=2^20

Valid divider values=[1, 2, 4, 6, ..., 2^20]

Rev. 1.0

27

Si5319

Register 40.

Bit

D7

D6

N2_HS [2:0]

R/W

D5

D4

Reserved

R

D3

D2

N2_LS [19:16]

R/W

D1

D0

Name

Type

Reset value = 1100 0000

Bit

Name

Function

7:5

N2_HS [2:0] N2_HS [2:0].

Sets value for N2 high speed divider which drives N2_LS low-speed divider.

000: 4

001: 5

010: 6

011: 7

100: 8

101: 9

110: 10

111: 11

4

Reserved

Reserved.

3:0 N2_LS [19:16] N2_LS [19:16].

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 2^20

Valid divider values = [2, 4, 6, ..., 2^20]

28

Rev. 1.0

Si5319

Register 41.

Bit

D7

D6

D5

D4

N2_LS [15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0000 0000

Bit

Name

N2_LS [15:8] N2_LS [15:8].

Function

7:0

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 2^20

Valid divider values = [2, 4, 6, ..., 2^20]

Register 42.

Bit

D7

D6

D5

D4

N2_LS [7:0]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 1111 1001

Bit

Name

N2_LS [7:0] N2_LS [7:0].

Function

7:0

Sets value for N2 low-speed divider, which drives phase detector.

00000000000000000001 = 2

00000000000000000011 = 4

00000000000000000101 = 6

...

11111111111111111111 = 2^20

Valid divider values = [2, 4, 6, ..., 2^20]

Rev. 1.0

29

Si5319

Register 43.

Bit

D7

D6

D5

Reserved

R

D4

D3

D2

D1

N31 [18:16]

R/W

D0

Name

Type

Reset value = 0000 0000

Bit

7:3

2:0

Name

Function

Reserved

Reserved.

N31 [18:16] N31 [18:16].

Sets value for input divider for CKIN.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 2^19

Valid divider values=[1, 2, 3, ..., 2^19]

Register 44.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N31_[15:8]

R/W

Reset value = 0000 0000

Bit

Name

N31_[15:8] N31_[15:8].

Function

7:0

Sets value for input divider for CKIN.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 2^19

Valid divider values=[1, 2, 3, ..., 2^19]

30

Rev. 1.0

Si5319

Register 45.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N31_[7:0]

R/W

Reset value = 0000 1001

Bit

Name

Function

7:0

N31_[7:0

N31_[7:0].

Sets value for input divider for CKIN.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 2^19

Valid divider values=[1, 2, 3, ..., 2^19]

Register 46.

Bit

D7

D6

D5

Reserved

R

D4

D3

D2

D1

D0

Name

Type

N32_[18:16]

R/W

Reset value = 0000 0000

Bit

7:3

2:0

Name

Function

Reserved

Reserved.

N32_[18:16] N32_[18:16].

Sets value for input divider for the XO clock in free-run mode.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 2^19

Valid divider values=[1, 2, 3, ..., 2^19]

Rev. 1.0

31

Si5319

Register 47.

Bit

D7

D6

D5

D4

N32_[15:8]

R/W

D3

D2

D1

D0

Name

Type

Reset value = 0000 0000

Bit

Name

N32_[15:8] N32_[15:8].

Function

7:0

Sets value for input divider for the XO clock in free-run mode.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 2^19

Valid divider values=[1, 2, 3, ..., 2^19]

Register 48.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N32_[7:0]

R/W

Reset value = 0000 1001

Bit

Name

Function

7:0

N32_[7:0]

N32_[7:0].

Sets value for input divider for the XO clock in free-run mode.

0000000000000000000 = 1

0000000000000000001 = 2

0000000000000000010 = 3

...

1111111111111111111 = 2^19

Valid divider values=[1, 2, 3, ..., 2^19]

32

Rev. 1.0

Si5319

Register 128.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

CK_ACT-

V_REG

Type

R

Reset value = 0010 0000

Bit

7:1

0

Name

Function

Reserved

Reserved.

CK_ACTV_ CK_ACTV_REG.

REG Indicates if CKIN is currently the active clock for the PLL input.

0: CKIN is not the active input clock. Either it is not selected or LOS_INT is 1.

1: CKIN is the active input clock.

Register 129.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

R

LOS_INT LOSX_INT

Type

R

Reset value = 0000 0110

Bit

7:2

1

Name

Function

Reserved

LOS_INT

Reserved.

LOS_INT.

Indicates the LOS status on CKIN.

0: Normal operation.

1: Internal loss-of-signal alarm on CKIN input.

0

LOSX_INT LOSX_INT.

Indicates the LOS status of the external reference on the XA/XB pins.

0: Normal operation.

1: Internal loss-of-signal alarm on XA/XB reference clock input.

Rev. 1.0

33

Si5319

Register 130.

Bit

D7

D6

D5

D4

Reserved

R

D3

D2

D1

D0

LOL_INT

R

Name

Type

Reset value = 0000 0001

Bit

7:3

0

Name

Function

Reserved

LOL_INT

Reserved.

PLL Loss of Lock Status.

0: PLL locked.

1: PLL unlocked.

Register 131.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

LOS_FLG LOSX_FLG

R/W R/W

Name

Reserved

R

Type

Reset value = 0001 1111

Bit

7:2

1

Name

Function

Reserved

LOS_FLG

Reserved.

CKIN Loss-of-Signal Flag.

0: Normal operation

1: Held version of LOS_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOS_MSK bit. Flag cleared by writing 0 to

this bit.

0

LOSX_FLG External Reference (signal on pins XA/XB) Loss-of-Signal Flag.

0: Normal operation

1: Held version of LOSX_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOSX_MSK bit. Flag cleared by writing 0 to

this bit.

34

Rev. 1.0

Si5319

Register 132.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

R

LOL_FLG

R/W

Reserved

R

Type

Reset value = 0000 0010

Bit

7:2, 0

1

Name

Function

Reserved

LOL_FLG

Reserved.

PLL Loss of Lock Flag.

0: PLL locked

1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to

this bit.

Register 134.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

PARTNUM_RO [11:4]

R

Type

Reset value = 0000 0001

Bit

Name

PARTNUM_ Device ID (1 of 2).

RO [11:0] 0000 0001 + 0011: Si5319

Function

7:0

Rev. 1.0

35

Si5319

Register 135.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

PARTNUM_RO [3:0]

R

REVID_RO [3:0]

R

Type

Reset value = 1010 0010

Bit

Name

PARTNUM_ Device ID (2 of 2).

RO [11:0] 0000 0001 + 0011: Si5319

Function

7:4

3:0

REVID_RO Indicates Revision Number of Device.

[3:0]

0000: Revision A

0001: Revision B

0010: Revision C

Others: Reserved

36

Rev. 1.0

Si5319

Register 136.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name RST_REG

ICAL

R/W

Reserved

R

GRADE_RO [1:0]

R

Type

R/W

Reset value = 0000 0000

Bit

Name

RST_REG Internal Reset (Same as Pin Reset).

Function

7

Note: The I2C (or SPI) port may not be accessed until 10 ms after RST_REG is asserted.

0: Normal operation.

1: Reset of all internal logic. Outputs disabled or tristated during reset.

6

ICAL

Start an Internal Calibration Sequence.

For proper operation, the device must go through an internal calibration sequence. ICAL

is a self-clearing bit. Writing a one to this location initiates an ICAL. The calibration is

complete once the LOL alarm goes low. A valid stable clock (within 100 ppm) must be

present to begin ICAL.

Note: Any divider, CLKINn_RATE or BWSEL_REG changes require an ICAL to take

effect.

0: Normal operation.

1: Writing a "1" initiates internal self-calibration. Upon completion of internal self-calibra-

tion, LOL will go low.

5:2

1:0

Reserved

Reserved.

GRADE_RO Indicates Maximum Clock Output Frequency of this Device.

[1:0]

Limits the range of the N1_HS divider.

00: N1_HS x NC1_LS > 4. Maximum clock output frequency = 1.4175 GHz.

01: N1_HS x NC1_LS > 6. Maximum clock output frequency = 808 MHz.

10: N1_HS x NC1_LS > 14. Maximum clock output frequency = 346 MHz.

11: N1_HS x NC1_LS > 20. Maximum clock output frequency = 243 MHz.

Rev. 1.0

37

Si5319

Register 138.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

LOS_EN

[1:1]

Type

R

R/W

Reset value = 0000 1111

Bit

7:3

0

Name

Function

Reserved

Reserved.

LOS_EN [1:0] Enable CKIN LOS Monitoring on the Specified Input (1 of 2).

Note: LOS_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the Family Reference Manual

for details.

Register 139.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

LOS_EN

[0:0]

Reserved

R

Type

R

R/W

Reset value = 1111 1111

Bit

7:5

4

Name

Function

Reserved

Reserved.

LOS_EN [1:0] Enable CKIN LOS Monitoring on the Specified Input (1 of 2).

Note: LOS_EN is split between two registers.

00: Disable LOS monitoring.

01: Reserved.

10: Enable LOSA monitoring.

11: Enable LOS monitoring.

LOSA is a slower and less sensitive version of LOS. See the family reference manual for

details.

3:0

Reserved

Reserved.

38

Rev. 1.0

Si5319

Register 185.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

NVM_REVID [7:0]

R

Type

Reset value = 0001 0011

Bit

Name

NVM_REVID [7:0] NVM_REVID.

Function

7:0

Table 8. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table

CKOUT_ALWAYS_ON SQ_ICAL

Results

0

1

CKOUT OFF until after the first ICAL.

CKOUT OFF until after the first successful

ICAL (i.e., when LOL is low).

1

0

1

CKOUT always ON, including during an

ICAL.

CKOUT always ON, including during an

ICAL. Use these settings to preserve output-

to-output skew.

Table 9 lists all of the register locations that should be followed by an ICAL after their contents are changed.

Table 9. Register Locations Requiring ICAL

Addr

Register

0

BYPASS_REG

CKOUT_ALWAYS_ON

BWSEL_REG

ICMOS

0

2

5

10

11

19

25

31

40

43

DSBL_REG

PD_CK

VALTIME

LOCKT

N1_HS

NC1_LS

N2_HS

N2_LS

N31

Rev. 1.0

39

Si5319

5. Pin Descriptions: Si5319

Pin # Pin Name I/O Signal Level

Description

External Reset.

1

I

LVCMOS

RST

Active low input that performs external hardware reset of device.

Resets all internal logic to a known state and forces the device regis-

ters to their default value. Clock outputs are disabled during reset. The

part must be programmed after a reset or power-on to get a clock out-

put. See Family Reference Manual for details.

This pin has a weak pull-up.

No Connection.

2, 4, 9,

12–14,

30,

NC

—

O

—

Leave floating. Make no external connections to this pin for normal

operation.

33–35

Interrupt/CKIN Invalid Indicator.

3

INT_CB

LVCMOS

This pin functions as a device interrupt output or an alarm output for

CKIN. If used as an interrupt output, INT_PIN must be set to 1. The pin

functions as a maskable interrupt output with active polarity controlled

by the INT_POL register bit.

If used as an alarm output, the pin functions as a LOS alarm indicator

for CKIN. Set CK_BAD_PIN = 1 and INT_PIN = 0.

0 = CKIN present.

1 = LOS on CKIN.

The active polarity is controlled by CK_BAD_POL. If no function is

selected, the pin tristates.

Supply.

5, 10,

32

V

Supply

DD

The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capaci-

tors should be associated with the following V pins:

DD

5

10

32

0.1 μF

A 1.0 μF should also be placed as close to the device as is practical.

Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).

40

Rev. 1.0

Si5319

Pin # Pin Name I/O Signal Level

Description

External Crystal or Reference Clock.

7

6

XB

XA

I

Analog

External crystal should be connected to these pins to use internal

oscillator based reference. Refer to the Family Reference Manual for

interfacing to an external reference. The external reference must be

from a high-quality clock source (TCXO, OCXO). Frequency of crystal

or external clock is set by the RATE pins.

Ground.

8, 31

19,20

Supply

3-Level

GND

Must be connected to system ground. Minimize the ground path

impedance for optimal performance of this device. Grounding these

pins does not eliminate the requirement to ground the GND PAD on

the bottom of the package.

External Crystal or Reference Clock Rate.

11

15

RATE0

RATE1

I

Three level inputs that select the type and rate of external crystal or

reference clock to be applied to the XA/XB port. Refer to the Family

Reference Manual for settings. These pins have both a weak pull-up

and a weak pull-down; they default to M. The "HH" setting is not sup-

ported.

Note: L setting corresponds to ground.

M setting corresponds to V_DD/2.

H setting corresponds to V_DD

.

Some designs may require an external resistor voltage divider when

driven by an active device that will tri-state.

Clock Input.

16

17

CKIN+

CKIN–

I

Multi

Differential input clock. This input can also be driven with a single-

ended signal. Input frequency range is 2 kHz to 710 MHz.

PLL Loss of Lock Indicator.

18

LOL

O

LVCMOS

This pin functions as the active high PLL loss of lock indicator if the

LOL_PIN register bit is set to 1.

0 = PLL locked.

1 = PLL unlocked.

If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the

LOL_POL bit. The PLL lock status will always be reflected in the

LOL_INT read only register bit.

Xtal/Input Clock Select.

21

CS

I

LVCMOS

This pin selects the active DSPLL input clock, which can be a clock

input or a crystal input. See the FREE_EN register for free run settings.

0 = Select clock input (CKIN).

1 = Select crystal or external reference clock.

This pin should not be left open.

Serial Clock/Serial Clock.

22

23

SCL

LVCMOS

2

This pin functions as the serial clock input for both SPI and I C modes.

This pin has a weak pull-down.

Serial Data.

SDA_SDO I/O

2

In I C control mode (CMODE = 0), this pin functions as the bidirec-

tional serial data port.

In SPI control mode (CMODE = 1), this pin functions as the serial data

output.

Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).

Rev. 1.0

41

Si5319

Pin # Pin Name I/O Signal Level

Description

Serial Port Address.

25

24

A1

A0

I

LVCMOS

2

In I C control mode (CMODE = 0), these pins function as hardware

controlled address bits. The I C address is 1101 [A2] [A1] [A0].

2

In SPI control mode (CMODE = 1), these pins are ignored.

These pins have a weak pull-down.

Serial Port Address/Slave Select.

26

27

A2_SS

I

LVCMOS

2

In I C control mode (CMODE = 0), this pin functions as a hardware

controlled address bit [A2].

In SPI control mode (CMODE = 1), this pin functions as the slave

select input.

This pin has a weak pull-down.

Serial Data In.

SDI

I

LVCMOS

Multi

2

In I C control mode (CMODE = 0), this pin is ignored.

In SPI control mode (CMODE = 1), this pin functions as the serial data

input.

This pin has a weak pull-down.

Output Clock.

29

28

CKOUT–

CKOUT+

O

Differential output clock with a frequency range of 10 MHz to

1.4175 GHz. Output signal format is selected by SFOUT1_REG regis-

ter bits. Output is differential for LVPECL, LVDS, and CML compatible

modes. For CMOS format, both output pins drive identical single-

ended clock outputs.

Control Mode.

36

CMODE

I

LVCMOS

Supply

2

Selects I C or SPI control mode for the Si5319.

2

0 = I C Control Mode

1 = SPI Control Mode

Ground Pad.

GND

PAD

GND

The ground pad must provide a low thermal and electrical impedance

to a ground plane.

Note: Internal register names are indicated by underlined italics (e.g., INT_PIN. See Si5319 Register Map).

42

Rev. 1.0

Si5319

6. Ordering Guide

Ordering Part

Output Clock

Frequency Range

ROHS6,

Pb-Free

Package

Temperature Range

Number

Si5319A-C-GM

2 kHz–945 MHz

970–1134 MHz

1.213–1.417 GHz

36-Lead 6 x 6 mm QFN

Yes

–40 to 85 °C

Si5319B-C-GM

Si5319C-C-GM

2 kHz–808 MHz

2 kHz–346 MHz

36-Lead 6 x 6 mm QFN

Yes

–40 to 85 °C

Note: Add an R at the end of the device part number to denote tape and reel ordering options.

Rev. 1.0

43

Si5319

7. Package Outline: 36-Pin QFN

Figure 6 illustrates the package details for the Si5319. Table 10 lists the values for the dimensions shown in the

illustration.

Figure 6. 36-Pin Quad Flat No-lead (QFN)

Table 10. Package Dimensions

Symbol

Millimeters

Nom

Symbol

Millimeters

Min

0.80

0.00

0.18

Max

0.90

0.05

0.30

Min

0.50

—

Nom

0.60

—

Max

0.70

12º

A

A1

b

0.85

L

0.02



0.25

aaa

bbb

ccc

ddd

eee

—

0.10

0.08

0.10

0.05

D

6.00 BSC

4.10

—

D2

e

3.95

4.25

—

0.50 BSC

6.00 BSC

4.10

—

E

—

E2

3.95

4.25

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220, variation VJJD.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

44

Rev. 1.0

Si5319

8. Recommended PCB Layout

Figure 7. PCB Land Pattern Diagram

Figure 8. Ground Pad Recommended Layout

Rev. 1.0

45

Si5319

Table 11. PCB Land Pattern Dimensions

Dimension

MIN

MAX

e

E

0.50 BSC.

5.42 REF.

D

E2

D2

GE

GD

X

4.00

4.53

—

4.20

—

0.28

Y

0.89 REF.

ZE

ZD

—

6.31

Notes (General):

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Notes (Solder Mask Design):

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 μm minimum, all the way around the pad.

Notes (Stencil Design):

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the

center ground pad.

Notes (Card Assembly):

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

46

Rev. 1.0

Si5319

9. Si5319 Device Top Mark

Mark Method:

Font Size:

Laser

0.80 mm

Right-Justified

Line 1 Marking:

Line 2 Marking:

Line 3 Marking:

Si5319

Customer Part Number

Q = Speed Code: A, B, C

See Ordering Guide for options

C-GM

C = Product Revision

G = Temperature Range –40 to 85 °C (RoHS6)

M = QFN Package

YYWWRF

YY = Year

WW = Work Week

R = Die Revision

F = Internal code

Assigned by the Assembly House. Corresponds to the year

and work week of the mold date.

Line 4 Marking:

Pin 1 Identifier

XXXX

Circle = 0.75 mm Diameter

Lower-Left Justified

Internal Code

Rev. 1.0

47

Si5319

Revision 0.43 to Revision 1.0

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

 Replaced the specification tables (tables 1 and 2

from rev. 0.43) with the specification tables from the

Si53x Reference Manual, rev 0.42.

 Changed 1.8 V operating range to ±5%.

 Updated Table 1 on page 4.

 Updated Table 2 on page 5.

 Added table under Figure 3 on page 14.

 Updated "3. Functional Description" on page 16.

 Clarified "5. Pin Descriptions: Si5319" on page 40.

Revision 0.2 to Revision 0.3

 Updated "5. Pin Descriptions: Si5319" on page 40.

Corrected Pins 11 and 15 description in table.

Revision 0.3 to Revision 0.4

 Updated Table 1 on page 4.

 Added "9. Si5319 Device Top Mark" on page 47.

Revision 0.4 to Revision 0.41

 Updated Table 1 on page 4.

Updated Thermal Resistance Junction to Ambient

typical specification.

 Updated Figure 4, “Si5319 Typical Application

2

Circuit (I C Control Mode),” on page 15.

 Updated Figure 5, “Si5319 Typical Application

Circuit (SPI Control Mode),” on page 15.

 Updated NC pin description in "5. Pin Descriptions:

Si5319" on page 40.

 Updated "7. Package Outline: 36-Pin QFN" on page

44.

 Added Figure 8, “Ground Pad Recommended

Layout,” on page 45.

 Added register map documentation.

 Updated Rise/Fall Time values.

Revision 0.41 to Revision 0.42

 Changed register address labels to decimal.

Revision 0.42 to Revision 0.43

 Updated the following:

ESD specifications

phase noise values

absolute Vdd maximum voltage

typical phase noise plot

 Added specification for phase changes due to

temperature variation

 Added information for the N32 register

 Added  specification

JC

48

Rev. 1.0

Si5319

NOTES:

Rev. 1.0

49

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Disclaimer

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型号：	SI5319C-C-GM
厂家：	SILICON
描述：	Clock Generator, 364MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36 时钟外围集成电路晶体
文件：	总50页 (文件大小：1931K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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