S3C9688_技术文档

S3C9688/P9688

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

SAM88RCRI PRODUCT FAMILY

Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated

peripherals, and various mask-programmable ROM sizes.

A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for

applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time

operations. Many SAM88RCRI microcontrollers have an external interface that provides access to external memory and other peripheral

devices.

S3C9688/P9688 MICROCONTROLLER

The S3C9688/P9688 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful

SAM88RCRI CPU core.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal

register file was logically expanded. The S3C9688 has 8 K bytes of program

memory on-chip.

Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:

—

Five configurable I/O ports (32 pins)

20 bit-programmable pins for external interrupts

8-bit timer/counter with three operating modes

Low speed USB function

The S3C9688/P9688 is a versatile microcontroller that can be used in a wide range of low speed USB support general purpose applications. It

is especially suitable for use as a keyboard controller and is available in a 42-pin SDIP and a 44-pin QFP package.

OTP

The S3C9688/P9688 microcontroller is also available in OTP (One Time Programmable) version, S3P9688. S3P9688 microcontroller has an

on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P9688 is comparable to S3C9688/P9688, both in function

and in pin configuration.

1-1

PRODUCT OVERVIEW

S3C9688/P9688

FEATURES

·

One 8-bit basic timer for watchdog function and

CPU

programmable oscillation stabilization interval generation

function

·

SAM88RCRI CPU core

One 8-bit timer/counter with Compare/Overflow

Memory

·

8 K byte internal program memory (ROM)

208 byte RAM

USB Serial Bus

·

Compatible to USB low speed (1.5 Mbps) device 2.0

specification.

Instruction Set

·

1 Control endpoint and 2 Interrupt endpoint

Serial bus interface engine (SIE)

·

41 instructions

IDLE and STOP instructions added for power-down modes

—

Packet decoding/generation

CRC generation and checking

Instruction Execution Time

·

NRZI encoding/decoding and bit-stuffing

0.66 ms at 6 MHz f

OSC

·

8 bytes each receive/transmit USB buffer

Interrupts

Low Voltage Reset

·

29 interrupt sources with one vector, each source has its

pending bit

·

Low voltage detect for RESET

Power on Reset

·

One level, one vector interrupt structure

Oscillation Circuit

Operating Temperature Range

°

C

·

– 40 C to + 85

6 MHz crystal/ceramic oscillator

External clock source (6 MHz)

Operating Voltage Range

Embedded oscillation capacitor (XI, XO, 33pF)

·

4.0 V to 5.25 V

General I/O

Package Types

·

Bit programmable five I/O ports (34 pins total)

(D+/PS2, D-/PS2 Included)

·

42-pin SDIP

44-pin QFP

—

Timer/Counter

1-2

S3C9688/P9688

PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0-P0.7/INT2

P1.0-P1.7

P2.0-P2.7/INT0

Port 0

Port 1

Port 2

SAM88RCRI Bus

P3.0

X

IN

Main

OSC

P3.1

Port 3

P3.2

X

OUT

I/O Port and Interrupt Control

P3.3/CLO

Basic

Timer

P4.0/INT1

P4.1/INT1

P4.2/INT1

P4.3/INT1

Port 4

SAM88RCRI CPU

LVR

D+/PS2

USB

D-/PS2

3.3 V OUT

Timer

208-Byte

40 bytes

USB

4 K/8KB ROM

Register File

Buffer

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW

S3C9688/P9688

PIN ASSIGNMENTS

P3.1

P3.0

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

P3.2

P3.3/CLO

D+/PS2

D-/PS2

3.3V OUT

NC

INT0/P2.0

3

INT0/P2.1

INT0/P2.2

INT0/P2.3

INT0/P2.4

INT0/P2.5

INT0/P2.6

INT0/P2.7

4

5

6

7

P0.0/INT2

P0.1/INT2

P0.2/INT2

P0.3/INT2

P0.4/INT2

P0.5/INT2

P0.6/INT2

P0.7/INT2

P1.0

8

9

S3C9688/P9688

(42-SDIP)

10

11

12

13

14

15

16

17

18

19

20

21

V

DD

V

SS

X

OUT

IN

X

29

28

TEST

INT1/P4.0

INT1/P4.1

RESET

27

26

25

24

23

22

P1.1

P1.2

P1.3

INT1/P4.2

INT1/P4.3

P1.7

P1.4

P1.5

P1.6

Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

1-4

S3C9688/P9688

PRODUCT OVERVIEW

3.3V OUT

34

35

36

37

38

39

40

41

42

43

44

22

21

20

19

18

17

16

15

14

13

12

P1.0

P1.1

P1.2

D- /PS2

D+/PS2

CLO/P3.3

P3.2

P1.3

P1.4

S3C9688/P9688

P3.1

P1.5

44-QFP

P3.0

P1.6

P1.7

(Top View)

P2.0/INT0

P2.1/INT0

P2.2/INT0

P2.3/INT0

P4.3/INT1

P4.2/INT1

RESET

NOTE:

The TEST pin must connect to V

SS (GND) in the normal operation mode.

Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

1-5

PRODUCT OVERVIEW

S3C9688/P9688

PIN DESCRIPTIONS

Table 1-1. S3C9688/P9688 Pin Descriptions

Pin Names

Circuit

Share

Pins

Type

Description

Number

Numbers

P0.0–P0.7

I/O

Bit-programmable I/O port for Schmitt trigger input or open-

drain output. Port0 can be individually configured as external

interrupt inputs. Pull-up resistors are assignable by software.

B

36–29

INT2

(30–23)

P1.0–P1.7

P2.0–P2.7

I/O

Bit-programmable I/O port for Schmitt trigger input or open-

drain output. Pull-up resistors are assignable by software.

B

28–21

–

(22–15)

Bit-programmable I/O port for Schmitt trigger input or open-

drain output. Port2 can be individually configured as external

interrupt inputs. Pull-up resistors are assignable by software.

3–10

INT0

(41–44, 1–4)

P3.0–P3.3

P4.0–P4.3

I/O

Bit-programmable I/O port for Schmitt trigger input, open-

drain or push-pull output. P3.3 can be used to system clock

output (CLO) pin.

C

D

2, 1, 42, 41

(40–37)

P3.3/CLO

INT1

Bit-programmable I/O port for Schmitt trigger input or open-

drain output or push-pull output. Port4 can be individually

configured as external interrupt inputs. In output mode, pull-

up resistors are assignable by software. But in input mode,

pull-up resistors are fixed.

16, 17, 19, 20

(10, 11, 13, 14)

D+/PS2 D-

/PS2

I/O

Programmable port for

or PS2 interface.

USB interface

–

40–39

–

(36–35)

3.3 V

–

3.3 V output from internal voltage regulator

–

38 (34)

–

OUT

X

, X

OUT

System clock input and output pin (crystal/ceramic oscillator,

or external clock source)

14, 13

(8, 7)

IN

INT0

INT1

INT2

I

External interrupt for bit-programmable port0, port2 and port4

pins when set to input mode.

–

3-10, 16,17, 19,

20, 29-36

PORT2/

PORT4/

PORT0

(30-23, 41-44, 1-

4, 10, 11, 13, 14)

RESET

TEST

I

RESET signal input pin. Input with internal pull-up resistor.

A

–

18 (12)

15 (9)

–

Test signal input pin (for factory use only; connected to V

)

SS

V

–

Power input pin

Ground input pin

No connection

11 (5)

DD

V

12, (6)

SS

NC

37 (31,32, 33)

NOTE:

Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.

PIN CIRCUITS DIAGRAMS

Table 1-2. Pin Circuit Assignments for the S3C9688/P9688

Circuit Number

Circuit Type

S3C9688/P9688 Assignments

A

B

C

D

I

RESET signal input

Ports 0, 1, and 2

Port 3

I/O

Port 4

1-6

S3C9688/P9688

PRODUCT OVERVIEW

DD

V

Pull-up

Resistor

Noise

Filter

Figure 1-4. Pin Circuit Type A (RESET)

V

DD

Pull-up

Resistor

Pull-up Enable

Output Disable

Open Data

I/O

V

SS

D0

D1

Input Data

MUX

Mode

Input Data

Output

Input

D0

D1

Figure 1-5. Pin Circuit Type B (Ports 0, 1 and 2)

1-7

PRODUCT OVERVIEW

S3C9688/P9688

V

DD

Output Data

Open Drain

I/O

Output

Disable

V

SS

D0

D1

Input Data

MUX

Mode

Input Data

Output

Input

D0

D1

Figure 1-6. Pin Circuit Type C (Port 3)

V

DD

Pull-up

Resistor

Pull-up Enable

V

DD

Output Data

Open Drain

I/O

Output

Disable

V

SS

D0

D1

Input Data

MUX

Mode

Output

Input

Input Data

D0

D1

Figure 1-7. Pin Circuit Type D (Port 4)

1-8

S3C9688/P9688

PRODUCT OVERVIEW

APPLICATION CIRCUIT

5V

V

DD

0

1

2

3

X

IN

15

OUT

S3C9688/P9688

0

1

2

3

RESET

7

DP

D+/PS2

D-/PS2

H

DM

O

S

T

KEYBOARD

MATRIX

V

SS1

NOTE:

Port4 can use expend keyboard MATRIX.

D+/PS2, D-/PS2 can use PS2 keyboard interface (see PS2CONINT, page 4-34).

Port 4.2, 4.3 can use PS2 mouse interface.

Port 3 can use LED direct drive.

Figure 1-8. Keyboard Application Circuit Diagram

1-9

PRODUCT OVERVIEW

S3C9688/P9688

NOTES

1-10

S3C9688/P9688

ADDRESS SPACES

2

ADDRESS SPACES

OVERVIEW

The S3C9688/P9688 microcontroller has two kinds of address space:

—

Program memory (ROM), internal

Internal register file

A 1 3 -bit address bus supports both program memory. A separate 8-bit register bus carries addresses and data

between the CPU and the internal register file.

The S3C9688 has 8 K bytes of mask-programmable program memory on-chip. There is one program memory

configuration option:

—

Internal ROM mode, in which only the 8 K byte internal program memory is used.

The S3C9688/P9688 microcontroller has 208 general-purpose registers in its internal register file. Twenty -seven

bytes in the register file are mapped for system and peripheral control functions.

2-1

ADDRESS SAPCES

S3C9 688/P9688

P R O G R A M M E M O R Y ( R O M )

N o r m a l O p e r a t i n g M o d e ( I n t e r n a l R O M )

The S3C9688/P9688 has 8 K bytes (locations 0H– 1FFFH) of internal mask-programmable program memory.

The first 2 bytes of the ROM (0000H– 0001H) are an interrupt vector address.

The program reset address in the ROM is 0100H.

(DECIMAL)

8,191

(HEX)

1FFFH (S3C9688/P9688)

8 K byte Internal

Program Memory

Area

4,095

0FFFH

4-Kbyte Internal

Program Memory

Area

256

Program Start

0100H

2

1

0

0002H

0001H

0000H

Interrupt Vector

F i g u r e 2 -1 . P r o g r a m M e m o r y A d d r e s s S p a c e

2-2

S3C9688/P9688

ADDRESS SPACES

R E G I S T E R A R C H I T E C T U R E

The upper 64 by tes of the S3C9688/P9688's internal register file are addressed as working registers, system control

registers and peripheral control registers. The lower 192 bytes of internal register file (00H– BFH) is called the general

purpose register space. The total addressable register space is thereby 256 bytes. 233 registers in this space can

be accessed.; 208 are available for general-purpose use.

For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the

additional of one or more register pages at general purpose register space (00H– BFH). This register file expansion is

not implemented in the S3C9688/P9688, however. Page addressing is controlled by the System Mode Register

( S Y M . 1 – SYM. 0).

The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in

Table 2-1.

T a b l e 2 -1 . R e g i s t e r T y p e S u m m a r y

Register Type

CPU and system control registers

N u m b e r o f B y t e s

11

34

P eripheral, I/O, and clock control and data registers

General-purpose registers (including the 16-bit common working register area)

Total Addressable Bytes

208

253

2-3

ADDRESS SAPCES

S3C9 688/P9688

FFH

Peripheral Control

Register

E0H

DFH

64 Bytes of

Common Area

System Control

Registers

D0H

CFH

Working Register

C0H

BFH

General Purpose

Register File

192 Bytes

and Stack Area

00H

F i g u r e 2 -2. Internal Register File Organization

2-4

S3C9688/P9688

ADDRESS SPACES

C O M M O N W O R K I N G R E G I S TER AREA (C0H–C F H )

The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction form ats to reduce execution time.

This 16-byte address range is called common area. That is, locations in this area can be used as working registers

by operations that address any location on any page in the register file. Typically, these working registers serve as

temporary buffers for data operations between different pages. However, because the S3C9688/P9688 uses only

page 0, you can use the common area for any internal data operation.

The Register (R) addressing mode can be used to access this area

Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the

address of the first 8-bit register is always an even number and the address of the next register is an odd number.

The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte

is always stored in the next (+ 1) odd-numbered register.

MSB

Rn

LSB

n = Even Address

Rn+1

F i g u r e 2 -3. 16-Bit Register Pairs

P R O G R A M M I N G T I P — A d d r e s s i n g t h e C o m m o n W o r k i n g R e g i s t e r A r e a

F

As the following examples show, you should access working registers in the common area, locations C0H– CF H,

using working register addressing mode only.

E x a m p l e s :

1. LD

0C2H, 40H

;

Invalid addressing mode!

Use working register addressing instead:

LD

R2,40H

;

R2 (C2H)

¨

the value in location 40H

2. A D D

0C3H, #45H

Invalid addressing mode!

Use working register addressing instead:

A D D R3,#45H R3 (C3H)

;

¨

R3 + 45H

2-5

ADDRESS SAPCES

S Y S T E M S T A C K

S3C9 688/P9688

S 3 C 9 -series microcontrollers use the system stack for storing data in subroutine call and return. The PUSH and

POP instructions are used to control system stack operations. The S3C9688/P9688 architecture supports stack

operations in the internal register file.

S t a c k O p e r a t i o n s

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of

the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their

original locations. The stack address is always decremented before a push operation and incremented after a pop

operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure

2-4.

High Address

PCL

PCH

Top of

PCH

Stack

Top of

FLAGS

Stack

Stack Contents

After a Call

Instruction

Stack Contents

After an

Low Address

Interrupt

F i g u r e 2 -4. S t a c k O p e r a t i o n s

S t a c k P o i n t e r ( S P )

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,

the SP value is undetermined.

Because only internal memory space is implemented in the S3C9688/P9688, the SP must be initialized to an 8-bit

value in the range 00H– B F H .

N O T E

In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means

that a Stack Pointer access invalid stack area.

2-6

S3C9688/P9688

ADDRESS SPACES

P R O G R A M M I N G T I P — S t a n d a r d S t a c k O p e r a t i o n s U s i n g P U S H a n d P O P

F

The following example shows you how to perform stack operations in the internal register file using PUSH and POP

instructions:

LD

S P , # 0 C 0 H

;

SP

¨

C0H (Normally, the SP is set to 0C0H by the

initialization routine)

•

P U S H

S Y M

C L K C O N

20H

;

S t a c k a d d r e s s 0 B F H ¨ S Y M

S t a c k a d d r e s s 0 B E H ¨ C L K CO N

S t a c k a d d r e s s 0 B D H ¨ 2 0 H

S t a c k a d d r e s s 0 B C H ¨ R 3

P U S H

R3

•

P O P

R3

;

R 3

¨

S t a c k a d d r e s s 0 B C H

P O P

20H

2 0 H ¨ S t a c k a d d r e s s 0 B D H

C L K C O N

S Y M

C L K C O N

¨

S t a c k a d d r e s s 0 B E H

S Y M S t a c k a d d r e s s 0 B F H

¨

2-7

ADDRESS SAPCES

S3C9 688/P9688

N O T E S

2-8

S3C9688/P9688

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to

determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition

codes, immediate data, or a location in the register file, program memory, or data memory.

The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are

available for each instruction. The addressing modes and their symbols are as follows:

—

Register (R)

Indirect Register (IR)

Indexed (X)

Direct Address (D A )

Relative Address (RA)

Immediate (IM)

3-1

ADDRESSING MODES

S3C9688/P9688

R E G I S T E R A D D R E S S I N G M O D E ( R )

In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register

addressing differs from Register addressing because it uses an 16-byte working register space in the register file and

an 4-bit register within that space (see Figure 3-2).

Program Memory

Register File

OPERAND

8-Bit Register

File Address

dst

Point to One

Rigister in Register

File

OPCODE

One-Operand

Instruction

(Example)

Value used in

Instruction Execution

Sample Instruction:

DEC CNTR

;

Where CNTR is the label of an 8-bit register address

F i g u r e 3 -1. Register Addressing

Register File

CFH

Program Memory

4-Bit

4 LSBs

Working Register

dst

OPCODE

src

OPERAND

Point to the

Woking Register

(1 of 16)

Two-Operand

Instruction

C0H

(Example)

Sample Instruction:

ADD R1, R2

;

Where R1 = C1H and R2 = C2H

F i g u r e 3 -2. Working Register Addressing

3-2

S3C9688/P9688

ADDRESSING MODES

I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( I R )

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the

operand. Depending on the instruction used, the actual address may point to a register in the register file, to program

memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly

address another memory location.

Program Memory

Register File

ADDRESS

8-Bit Register

File Address

dst

Point to One

Rigister in Register

File

OPCODE

One-Operand

Instruction

(Example)

Address of Operand

used by Instruction

OPERAND

Value used in

Instruction Execution

Sample Instruction:

RL

@SHIFT

;

Where SHIFT is the label of an 8-Bit register address

F i g u r e 3 -3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

S3C9688/P9688

I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( C o n t i n u e d)

Register File

Program Memory

REGISTER

PAIR

Example

dst

Instruction

Points to

References

Program

Memory

OPCODE

Rigister Pair

16-Bit

Address

Points to

Program

Memory

Program Memory

OPERAND

Sample Instructions:

Value used in

Instruction

CALL

JP

@RR2

F i g u r e 3 -4. Indirect Register Addressing to Program Memory

3-4

S3C9688/P9688

ADDRESSING MODES

I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( C o n t i n u e d)

Register File

CFH

Program Memory

4-Bit

4 LSBs

Working

Register

Address

dst

OPCODE

src

OPERAND

Point to the

Woking Register

(1 of 16)

C0H

Sample Instruction:

OR R6, @R2

Value used in

Instruction

OPERAND

F i g u r e 3 -5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

S3C9688/P9688

I N D I R E C T R E G I S T E R A D D R E S S I N G M O D E ( C o n c l u d e d)

Register File

CFH

Program Memory

4-Bit Working

Register Address

dst

OPCODE

src

Register

Pair

Next 3-Bits Point

to Working

Example Instruction

References either

Program Memory or

Data Memory

Register Pair

(1 of 8)

16-Bit

C0H

address

points to

program

memory

or data

Program Memory

or

LSB Selects

Data Memory

memory

Value used in

Instruction

OPERAND

Sample Instructions:

LCD

LDE

R5,@RR2

; Program memory access

R3,@RR14 ; External data memory access

@RR4, R8 ; External data memory access

F i g u r e 3 -6. Indirect Working Register A d d r e s s i n g t o P r o g r a m o r D a t a M e m o r y

3-6

S3C9688/P9688

ADDRESSING MODES

I N D E X E D A D D R E S S I N G M O D E ( X )

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate

the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the

internal register file or in external memory.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range

– 128 to +127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in

a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see

Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD).

The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program

memory, and for external data memory, when implemented.

Register File

~

Value used in

Instruction

OPERAND

+

Program Memory

X (OFFSET)

4 LSBs

Two-Operand

Instruction

Example

dst

OPCODE

src

INDEX

Point to One of the

Woking Register

(1 of 16)

Sample Instruction:

LD

R0, #BASE[R1] ; Where BASE is an 8-bit immediate value

F i g u r e 3 -7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

S3C9688/P9688

I N D E X E D A D D R E S S I N G M ODE (C o n t i n u e d)

Program Memory

Register File

XS (OFFSET)

4-Bit Working

NEXT 3-Bit

dst

src

Register

Pair

Register Address

Point to Working

Register Pair

(1 of 8)

OPCODE

16-Bit

address

added to

offset

LSB Selects

+

16-Bit

8-Bit

Program Memory

or

Datamemory

Value used in

Instruction

OPERAND

16-Bit

Sample Instructions:

LDC

LDE

R4, #04H[RR2] ; The values in the program address (RR2 + #04H)

are loaded into register R4.

R4,#04H[RR2] ; Identical operation to LDC example, except that

external program memory is accessed.

F i g u r e 3 -8 . I n d e x e d A d d r e s s i n g t o P r o g r a m o r D a t a M e m o r y w i t h S h o r t O f f s e t

3-8

S3C9688/P9688

ADDRESSING MODES

I N D E X E D A D D R E S S I N G M ODE (C o n c l u d e d)

Program Memory

Register File

XL

H

L

(OFFSET)

Register

Pair

NEXT 3-Bit

4-Bit Working

dst

OPCODE

src

Register Address

Point to Working

Register Pair

(1 of 8)

16-Bit

address

added to

offset

LSB Selects

+

16-Bit

Program Memory

or

Datamemory

Value used in

Instruction

OPERAND

16-Bit

Sample Instructions:

LDC

LDE

R4, #1000H[RR2]

R4,#1000H[RR2]

; The values in the program address (RR2 + #1000H)

are loaded into register R4.

; Identical operation to LDC example, except that

external program memory is accessed.

F i g u r e 3 -9 . I n d e x e d A d d r e s s i n g t o P r o g r a m o r D a t a M e m o r y w i t h L o n g O f f s e t

3-9

ADDRESSING MODES

S3C9688/P9688

D I R E C T A D D R E S S M O D E (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load

operations to program memory (LDC) or to external data memory (LDE), if implemented.

Program or

Data Memory

Memory

Address

Program Memory

Used

Upper Address Byte

Lower Address Byte

dst/src

"0" or "1"

LSB Selects Program

Memory or Data Memory:

"0" = Program Memory

"1" = Data Memory

OPCODE

Sample Instructions:

LDC

LDE

R5,1234H ; The values in the program address (1234H)

are loaded into register R5.

R5,1234H ; Identical operation to LDC example, except that

external program memory is accessed.

F i g u r e 3 -10. Direct Addressing for Load Instructions

3-10

S3C9688/P9688

ADDRESSING MODES

D I R E C T A D D R E S S M O D E (C o n t i n u e d)

Program Memory

Next OPCODE

Program

Memory

Address

Used

Upper Address Byte

Lower Address Byte

OPCODE

Sample Instructions:

JP

C,JOB1

;

Where JOB1 is a 16-Bit immediate address

Where DISPLAY is a 16-Bit immediate address

CALL

DISPLAY

F i g u r e 3 -11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES

S3C9688/P9688

R E L A T I V E A D D R E S S M O D E (RA)

In Relative Address (RA) mode, a two's -complement signed displacement between – 128 and + 127 is specified in

the instruction. The displacement value is then added to the current PC value. The result is the address of the next

instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately

following the current instruction.

The instructions that support RA addressing is JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Current

PC Value

+

Displacement

OPCODE

Current Instruction

Signed

Displacement Value

Sample Instructions:

JR

ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128

F i g u r e 3 -12. Relative Addressing

I M M E D I A T E M O D E ( I M )

In Immediate (IM) addressing mode, the operand value used in the in struction is the value supplied in the operand

field itself. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:LD

R0,#0AAH

F i g u r e 3 -1 3 . I m m e d i a t e A d d r e s s i n g

3-12

S3C9688/P9688

CONTROL REGISTERS

4

CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3C9688/P9688 control registers are presented in an easy-to-read format.

These descriptions will help you to familiarize yourself with the mapped locations in the register file. You can also

use them as a quick-reference source when writing application programs.

System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the

standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More information

about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this

manual.

4-1

CONTROL REGISTERS

S3C9688/P9688

T a bl e 4 -1. System and Peripheral control Registers

R e g i s t e r N a m e

M n e m o n i c

T0CNT

D e c i m a l

208

H e x

D0H

D1H

D2H

D3H

R/W

R

Timer 0 counter register

Timer 0 data register

Timer 0 control register

T0DATA

T0CON

209

R/W

210

USB selection and Transceiver crossover point

control register

U S X C O N

211

Clock control register

System flags register

C L K C O N

F L A G S

212

213

214

D4H

D5H

D6H

R/W

D+/PS2, D -/PS2 data register

( O n l y P S 2 M o d e )

P S 2 D A T A

PS2 control and interrupt pending register

Port 0 interrupt control register

Stack pointer

P S 2 C O N I N T

P0INT

215

216

217

218

D7H

D8H

D9H

D A H

R/W

S P

Port 0 interrupt pending register

P 0 P N D

Location DBH is not mapped.

Basic timer control register

Basic timer counter register

B T C O N

220

221

D C H

D D H

R/W

R

B T C N T

Location DEH is not mapped.

System mode register

S Y M

P 0

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

D F H

E 0 H

E 1 H

E 2 H

E 3 H

E 4 H

E 5 H

E 6 H

E 7 H

E 8 H

E 9 H

E A H

E B H

E C H

E D H

E E H

E F H

R/W

Port 0 data register

Port 1 data register

P 1

Port 2 data register

P 2

Port 3 data register

P 3

Port 4 data register

P 4

Port 3 control register

P 3 C O N

P 0 C O N H

P 0 C O N L

P 1 C O N H

P 1 C O N L

P 2 C O N H

P 2 C O N L

P2INT

P 2 P N D

P 4 C O N

P4INTPND

Port 0 control register (high byte)

Port 0 control register (low byte)

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 2 interrupt control register

Port 2 interrupt pending register

Port 4 control register

Port 4 interrupt enable/pending register

4-2

S3C9688/P9688

CONTROL REGISTERS

4-3

CONTROL REGISTERS

S3C9688/P9688

T a b l e 4 -1. System and Peripheral control Registers (Continued)

R e g i s t e r N a m e

M n e m o n i c

F A D D R

D e c i m a l

240

H e x

F 0 H

F 1 H

F 2 H

F 3 H

F 4 H

F 5 H

F 6 H

F 7 H

F 8 H

F 9 H

F A H

F B H

F C H

F D H

F E H

R/W

USB function address register

Control endpoint status register

Interrupt endpoint 1 control status register

Control endpoin t byte count register

Control endpoint FIFO register

Interrupt endpoint 1 FIFO register

USB interrupt pending register

USB interrupt enable register

USB power management register

Interrupt endpoint 2 control status register

Interrupt endpoint 2 FIFO register

Endpoint mode register

E P 0 C S R

E P 1 C S R

E P 0 B C N T

E P 0 F I F O

E P 1 F I F O

U S B P N D

U S B I N T

241

242

243

244

245

246

247

P W R M G R

E P 2 C S R

E P 2 F I F O

E P M O D E

E P 1 B C N T

E P 2 B C N T

U S B C O N

248

249

250

251

Endpoint 1 byte count

252

E n d point 2 byte count

253

USB control register

254

Location FFH is not mapped.

4-4

S3C9688/P9688

CONTROL REGISTERS

Bit number(s) that is/are appended to the

register name for bit addressing

Name of individual

bit or bit function

Register address

(hexadecimal)

Register

Full Register name

mnemonic

D5H

FLAGS- System Flags Register

.7

.6

.5

.4

.3

.2

.1

.0

Bit Identifier

RESETValue

Read/Write

x

0

R/W

.7

Carry Flag (C)

0

1

Operation dose not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit7

.6

Zero Flag

0

1

Operation result is a non-zero value

Operation result is zero

.5

Sign Flag

0

1

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

R = Read-only

W = Write-only

R/W = Read/write

' - ' = Not used

Description of the

effect of specific

bit settings

RESET value notation:

'-' = Not used

'x' = Undetermind value

'0' = Logic zero

'1' = Logic one

Addressing mode or

Bit number:

MSB = Bit 7

LSB = Bit 0

modes you can use to

modify register values

F i g u r e 4 -1. Register Description Format

4-5

CONTROL REGISTERS

S3C9688/P9688

BTCON _{— Basic Timer Control Register}

D C H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

.7-.4

W a t c h d o g T i m e r E n a b l e B i t s

1

0

1

0

Disable watchdog function

Enable watchdog function

Any other value

. 3 and . 2

Basic Timer Input Clock Selection Bits

0

1

0

1

0

1

f

/4096

/1024

/128

OSC

Invalid setting

(note)

B a s i c T i m e r C o u n t e r C l e a r B i t

.1

0

1

No effect

Clear BTCNT

(note)

B a s i c T i m e r D i v i d e r C l e a r B i t

.0

0

1

No effect

Clear both dividers

NOTE:

When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit

is then cleared automatically to "0".

4-6

S3C9688/P9688

CONTROL REGISTERS

CLKCON _{— System Clock Control Register}

D4H

Bit Identifier

.7

0

.6

–

.5

–

.4

0

.3

0

.2

–

.1

–

.0

–

V a l u e

RESET

R e a d / W r i t e

R/W

–

R/W

–

.7

Oscillator IRQ Wake -up Function Bit

0

1

Enable IRQ for main system oscillator wake-up in power down mode

Disable IRQ for main system oscillator wake-up in power down mode

. 6 and . 5

. 4 and . 3

Not used for S3C9688/P9688

(1)

CPU Clock (System Clock) Selection Bits

0

1

0

1

0

1

Divide by 16 (f

Divide by 8 (f

/16)

OSC

/8)

OSC

Divide by 2 (f

/2)

OSC

(2)

)

Non-divided clock (f

OSC

.2–.0

Not used for S3C9688/P9688

NOTES

:

1.

After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the

appropriate values to CLKCON.3 and CLKCON.4.

f

2.

means oscillator frequency.

OSC

4-7

CONTROL REGISTERS

S3C9688/P9688

EP0BCNT

— Endpoint 0 Write Counter Register

F3H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R

R/W

R

.7

D a t a _ T o g g l e _ C h e c k B i t

0

1

DATA0 transaction toggle

DATA1 transaction toggle

.6

Setup_transa ction Bit

0

1

Not setup transaction

Setup transaction

.5

RCV_Over_8_BYTE Bit

0

1

Normal Operation

Indicates over 8 bytes received

.4

E n a b l e B i t

0

1

Disable Endpoint 0

Enable Endpoint 0

.3–.0

The Byte counter of Data that stored in Endpoint 0

0000

1000

Minimum bytes stored in Endpoint 0

Maximum bytes stored in Endpoint 0

4-8

S3C9688/P9688

CONTROL REGISTERS

EP0CSR _{— Control Endpoint 0 Status Register}

F1H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7

Setu p T ran sfer En d Cl ear Bi t

0

1

No effect (when write)

To clear SETUP_ T R A N S F E R _ E N D b i t

.6

.5

.4

.3

O u t P a c k e t R e a d y C l e a r B i t

0

1

No effect (when write)

To clear OUT_PKT_RDY bit

S e n d i n g S t a l l B i t

0

1

No effect (when write)

To send STALL signal

Setup Transfer End Bit

0

1

No effect (when write)

SIE sets this bit when a control transfer ends before DATA_END (bit3) is set

S e t u p D a t a E n d B i t

0

1

No effect (when write)

MCU set this bit after loading or unloading the last packet data into the FIFO

.2

.1

.0

Sent Stall Bit

0

1

MCU clear this bit to end the STALL condition

SIE sets this bit if a control transaction is ended due to a protocol violation

I n P a c k e t R e a d y B i t

0

1

SIE clear this bit once the packet has been successfully sent to the host

MCU sets this bit after writing a packet of data into ENDPOINT0 FIFO

O u t P a c k e t R e a d y B i t

0

1

No effect (when write)

SIE sets this bit once a valid token is written to the FIFO

4-9

CONTROL REGISTERS

S3C9688/P9688

4-10

S3C9688/P9688

CONTROL REGISTERS

EP0FIFO

— Endpoint 0 FIFO Address Register

F4H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7–.0

Endpoint 0 FIFO

This register is bi-directional 8-byte depth FIFO used to transfer control Endpoint 0

data.

4-11

CONTROL REGISTERS

S3C9688/P9688

EP1BCNT

— Endpoint 1 Write Counter Register

F C H

Bit Identifier

.7

0

.6

–

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R

–

R

R/W

R

.7

D a t a _ T o g g l e _ C h e c k B i t

0

1

DATA0 transaction toggle

DATA1 transaction toggle

.6

.5

R e s e r v e d

RCV_Over_8_BYTE Bit

0

1

Normal Operation

Indicates over 8 bytes received

.4

E n a b l e B i t

0

1

Disable Endpoint 1

Enable Endpoint 1

.3–.0

The Byte counter of Data that stored in Endpoint 1

0000

1000

Minimum bytes stored in Endpoint 1

Maximum bytes stored in Endpoint 1

4-12

S3C9688/P9688

CONTROL REGISTERS

EP1CSR

— Control Endpoint 1 Status Register

F2H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

a) The bellows are configured as IN mode

.7

D a t a T o g g l e S e q u e n c e C l e a r B i t

0

1

No effect (when write)

MCU sets this bit to clear the data toggle sequence bit. The data toggle is

initialized to DATA0.

.6–.3

M a x i m u m P a c k e t S i z e B i t s

0

1

No effect (when write)

These bits indicate the maximum packet size for IN endpoint, and needs to be

updated by the MCU before it sets IN_PKT_RDY. Once set, the contents are

valid till MCU re -writes them.

.2

FIFO Flush Bit

0

1

No effect (when write)

When MCU writes a one to this register, the FIFO is flushed, and IN_PKT_RDY

cleared. The MCU should wait for IN_PKT_RDY to be cleared for the flush to take

place.

.1

F o r c e S T A L L B i t

0

1

No effect (when write)

MCU writes a 1 to this register to issue a STALL handshake to USB. MCU clears

this bit, to end the STALL condition.

.0

I n P a c k e t R e a d y B i t

0

1

SIE clear this bit once the packet has been successfully sent to the host

MCU sets this bit, after writing a packet of data into ENDPOINT1 FIFO. USB

clears this bit, once the packet has been successfully sent to the host. An

interrupt is generated when USB clears this bit, so MCU can load the next

packet.

4-13

CONTROL REGISTERS

S3C9688/P9688

EP1CSR

— Control Endpoint 1 Status Register

F2H

Bit Identifier

.7

–

.6

0

.5

–

.4

–

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

–

R/W

–

R/W

b) The bellows are configured as OUT mode

.7

.6

R e s e r v e d

C L R _ O U T _ P K T _ R D Y B i t

0

1

No effect (when write)

Clear OUT_PKT_RDY (bit 0) bit..

.5–.4

.3

R e s e r v e d

R C V _ S T A L L _ S I G B i t

0

1

MCU can clear this bit

SIE sets this bit after sending stall packet

.2

.1

.0

F L U S H _ F I F O B i t

0

1

No effect (when write)

FIFO is flushed, and OUT_PKT_RDY bit is cleared..

F O R C E _ S T A L L B i t

0

1

MCU clears this bit to end the STALL condition

Issues a STALL handshake to USB

O U T _ P a c k e t R e a d y B i t

0

1

No effect (when write)

SIE sets this bit once a valid token is written to the FIFO

4-14

S3C9688/P9688

CONTROL REGISTERS

EP1FIFO

— Endpoint 1 FIFO Address Register

F5H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7–.0

Endpoint 1 FIFO

This register is bi-directional 8-byte depth FIFO used to transfer control Endpoint 1

data.

4-15

CONTROL REGISTERS

S3C9688/P9688

EP2BCNT

— Endpoint 2 Write Counter Register

F D H

Bit Identifier

.7

0

.6

–

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R

–

R

R/W

R

.7

D a t a _ T o g g l e _ C h e c k B i t

0

1

DATA0 transaction toggle

DATA1 transaction toggle

.6

.5

R e s e r v e d

RCV_Over_8_BYTE Bit

0

1

Normal Operation

Indicates over 8 bytes received

.4

E n a b l e B i t

0

1

Disable Endpoint 2

Enable Endpoint 2

.3–.0

The Byte counter of Data that stored in Endpoint 2

0000

1000

Minimum bytes stored in Endpoint 2

Maximum bytes stored in Endpoint 2

4-16

S3C9688/P9688

CONTROL REGISTERS

EP2CSR

— Control Endpoint 2 Status Register

F9H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

a) The bellows are configured as IN mode

.7

D a t a T o g g l e S e q u e n c e C l e a r B i t

0

1

No effect (when write)

MCU sets this bit to clear the data toggle sequence bit. The data toggle is

initialized to DATA0.

.6–.3

M a x i m u m P a c k e t S i z e B i t s

0

1

No effect (when write)

These bits indicate the maximum packet size for IN endpoint, and needs to be

updated by the MCU before it sets IN_PKT_RDY. Once set, the contents are

valid till MCU re -writes them.

.2

FIFO Flush Bit

0

1

No effect (when write)

When MCU writes a one to this register, the FIFO is flushed, and IN_PKT_RDY

cleared. The MCU should wait for IN_PKT_RDY to be cleared for the flush to take

place.

.1

F o r c e S T A L L B i t

0

1

No effect (when write)

MCU writes a 1 to this register to issue a STALL handshake to USB. MCU clears

this bit, to end the STALL condition.

.0

I n P a c k e t R e a d y B i t

0

1

SIE clear this bit once the packet has been successfully sent to the host

MCU sets this bit, after writing a packet of data into ENDPOINT 2 FIFO. USB

clears this bit, once the packet has been successfully sent to the host. An

interrupt is generated when USB clears this bit, so MCU can load the next

packet.

4-17

CONTROL REGISTERS

S3C9688/P9688

EP2CSR

— Control Endpoint 2 Status Register

F9H

Bit Identifier

.7

–

.6

0

.5

–

.4

–

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

–

R/W

–

R/W

b) The bellows are configured a s O U T m o d e

.7

.6

R e s e r v e d

C L R _ O U T _ P K T _ R D Y B i t

0

1

No effect (when write)

Clear OUT_PKT_RDY (bit 0) bit..

.5–.4

.3

R e s e r v e d

R C V _ S T A L L _ S I G B i t

0

1

MCU can clear this bit

SIE sets this bit after sending stall packet

.2

.1

F L U S H _ F I F O B i t

0

1

No effect (when write)

FIFO is flushed, and OUT_PKT_RDY bit is cleared..

F O R C E _ S T A L L B i t

0

1

MCU clears this bit to end the STALL condition

Issues a STALL handshake to USB

.0

O U T _ P a c k e t R e a d y B i t

0

1

No effect (when write)

SIE sets this bit once a valid token is written to the FIFO

4-18

S3C9688/P9688

CONTROL REGISTERS

EP2FIFO

— Endpoint 2 FIFO Address Register

FAH

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7–.0

Endpoint 2 FIFO

This register is bi-directional 8-byte depth FIFO used to transfer control Endpoint 2

data.

4-19

CONTROL REGISTERS

S3C9688/P9688

EPMODE

— Endpoint Mode Register

F B H

Bit Identifier

.7

0

.6

0

.5

–

.4

–

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

–

R/W

. 7 and . 6

Reset Length Selection Bits

0

1

0

1

0

1

20.954us

10.476us

5.236us

2.664us

.5–.4

.3

Not used for C9688/P9688

Chip Test Mode : User must not set this bit.

0

1

Normal mode

Test mode

.2

.1

.0

O u t p u t E n a b l e M o d e

0

1

Enhanced mode

Normal mode

E n d p o i n t 2 M o d e

0

1

Endpoint 2 acts as IN interrupt endpoint

Endpoint 2 acts as an OUT interrupt endpoint

E n d p o i n t 1 M o d e

0

1

Endpoint 1 acts as an IN interrupt endpoint

Endpoint 1 acts as an OUT interrupt endpoint

4-20

S3C9688/P9688

CONTROL REGISTERS

FADDR

— USB Function Address Register

F0H

Bit Identifier

V a l u e

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

.

RESET

R e a d / W r i t e

R/W

.7

This register bit is used as test mode or special purpose mode, so user should set

zero value,

.6–.0

F A D D R

This register holds the USB address assigned by the host computer. FADDR is

located at address F0H and is read/write addressable.

4-21

CONTROL REGISTERS

S3C9688/P9688

FLAGS

— System Flags Register

D5H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

–

.2

–

.1

.0

–

V a l u e

–

RESET

R e a d / W r i t e

R/W

–

.7

Carry Flag (C)

Operation does not generate a carry or borrow condition

0

.6

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

.5

S i g n F l a g ( S )

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

.4

O v e r f l o w F l a g ( V )

0

1

Operation result is

+127 or

– 128

£

³

Operation result is

£

.3–.0

Not used for S3C9688/P9688

4-22

S3C9688/P9688

CONTROL REGISTERS

P0CONH

— Port 0 Control Register (High Byte)

E6H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

. 7 and . 6

Port 0, P0.7 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 0, P0.6 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 0, P0.5 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 0, P0.4 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

4-23

CONTROL REGISTERS

S3C9688/P9688

P0CONL

— Port 0 Control Register (Low Byte)

E7H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d/Write

R/W

. 7 and . 6

Port 0, P0.3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 0, P0.2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 0, P0.1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 0, P0.0 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

4-24

S3C9688/P9688

CONTROL REGISTERS

P0INT

— Port 0 Interrupt Control Register

D8H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7

P0.7 Configuration Bits

0

1

External interrupt disable

External interrupt enable

.6

.5

.4

.3

.2

.1

.0

P0.6 Configuration Bits

0

1

External interrupt disable

External interrupt enable

P0.5 Configuration Bits

0

1

External interrupt dis able

External interrupt enable

P0.4 Configuration Bits

0

1

External interrupt disable

External interrupt enable

P0.3 Configuration Bits

0

1

External interrupt disable

External interrupt enable

P0.2 Configuration Bits

0

1

External interrupt disable

External interrupt enable

P0.1 Configuration Bits

0

1

External interrupt disable

External interrupt enable

P0.0 Configuration Bits

0

1

External interrupt disable

External interrupt enable

4-25

CONTROL REGISTERS

S3C9688/P9688

4-26

S3C9688/P9688

CONTROL REGISTERS

P0PND

— Port 0 Interrupt Pending Register

DAH

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

(NOTE)

R e a d / W r i t e

R/W

.7

P0. 7 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

.6

.5

.4

.3

.2

.1

.0

P0. 6 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P0. 5 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P0. 4 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P0. 3 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P0. 2 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when w rite)

P0. 1 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P0. 0 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

4-27

CONTROL REGISTERS

S3C9688/P9688

4-28

S3C9688/P9688

CONTROL REGISTERS

P1CONH _{— Port 1 Control Register (High Byte)}

E8H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

. 7 a n d .6

Port 1, P1.7 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 1, P1.6 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 1, P1.5 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 1, P1.4 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

4-29

CONTROL REGISTERS

S3C9688/P9688

P1CONL _{— Port 1 Control Register (Low Byte)}

E9H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

. 7 and . 6

Port 1, P1. 3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 1, P1.2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 1, P1.1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 1, P1.0 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

Schmitt trigger input with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

4-30

S3C9688/P9688

CONTROL REGISTERS

P2CONH _{— Port 2 Control Register (High Byte)}

EAH

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

. 7 and . 6

Port 2, P2.7 Configuration Bits

0

1

0

1

0

1

S c h m itt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 2, P2.6 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 2, P2.5 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 2, P2.4 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

4-31

CONTROL REGISTERS

S3C9688/P9688

P2CONL

— Port 2 Control Registe r (Low Byte)

E B H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

. 7 and . 6

Port 2, P2.3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 2, P2.2 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 2, P2.1 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

Port 2, P2.0 Configuration Bits

0

1

0

1

0

1

S c h m itt trigger input, rising edge external interrupt

Schmitt trigger input, falling edges external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

4-32

S3C9688/P9688

CONTROL REGISTERS

P2INT

— Port 2 Interrupt Enable Register

E C H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7

P2. 7 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

.6

.5

.4

.3

.2

.1

.0

P2. 6 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P2. 5 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P2. 4 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P2. 3 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P2. 2 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P2. 1 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P2. 0 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

4-33

CONTROL REGISTERS

S3C9688/P9688

4-34

S3C9688/P9688

CONTROL REGISTERS

P2PND _{— Port 2 Interrupt Pending Register}

E D H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

(NOTE)

R/W

R e a d / W r i t e

.7

P2. 7 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

.6

.5

.4

.3

.2

.1

.0

P2. 6 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P2. 5 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P2. 4 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P2. 3 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P2. 2 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P2. 1 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

P2. 0 Interrupt Pending Bit

0

1

No pending (when read)/clear pending bit (when write)

Pending (when read)/no effect (when write)

4-35

CONTROL REGISTERS

S3C9688/P9688

NOTE

: To clear a port 2 interrupt pending condition, write a "0" to the corresponding P2PND register bit location.

4-36

S3C9688/P9688

CONTROL REGISTERS

P3CON _{— Port 3 Control Register}

E5H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

. 7 and . 6

Port 3, P3.3 Configuration Bits

0

1

0

1

0

1

Schmitt trigger input

System clock output(CLO) mode. CLO comes from system clock circuit.

P u s h-pull output

N -channel open-drain output mode

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 3, P3.2 Configuration Bits

0

1

x

0

1

Schmitt trigger input

P u s h-pull output

N -channel open-drain output mode

Port 3, P3.1 Configuration Bits

0

1

x

0

1

Schmitt trigger input

P u s h-pull output

N -channel open-drain output mode

Port 3, P3.0 Configuration Bits

0

1

x

0

1

Schmitt trigger input

P u s h-pull output

N -channel open-drain output mode

NOTE:

"x" means don't care.

4-37

CONTROL REGISTERS

S3C9688/P9688

P4CON _{— Port 4 Control Register}

E E H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

. 7 and . 6

Port 4, P4.3 Configuration Control Bits

0

1

0

1

0

1

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode with pull-up

N -CH open drain output mode

Output push-pull mode

. 5 and . 4

. 3 and . 2

. 1 and . 0

Port 4, P4.2 Configuration Control Bits

0

1

0

1

0

1

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode with pull-up

N -CH open drain output mode

Output push -pull mode

Port 4, P4.1 Configuration Control Bits

0

1

0

1

0

1

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode with pull-up

N -CH open drain output mode

Output push -pull mode

Port 4, P4.0 Configuration Control Bits

0

1

0

1

0

1

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode with pull-up

N -CH open drain output mode

Output push -pull mode

4-38

S3C9688/P9688

CONTROL REGISTERS

P4INTPND _{— Port 4 Interrupt Enable and Pending Register}

EFH

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

R/W

.7

P4. 3 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

.6

.5

.4

.3

.2

.1

.0

P4. 2 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P4. 1 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P 4. 0 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

P4. 3 Interrupt Pending Bit

0

1

No pending (when bit is read)/clear pending bit (when bit is write)

Pending (when bit is read)/no effect (when bit is write)

P4. 2 Interrupt Pending Bit

0

1

No pending (when bit is read)/clear pending bit (when bit is write)

Pending (when bit is read)/no effect (when bit is write)

P4. 1 Interrupt Pending Bit

0

1

No pending (when bit is read)/clear pending bit (when bit is write)

Pending (when bit is read)/no effect (when bit is write)

P4. 0 Interrupt Pending Bit

0

1

No pending (when bit is read)/clear pending bit (when bit is write)

Pending (when bit is read)/no effect (when bit is write)

4-39

CONTROL REGISTERS

S3C9688/P9688

4-40

S3C9688/P9688

CONTROL REGISTERS

PS2CONINT _{— PS2 Control and Interrupt Pending Register (PS2 Mode only)}

D7H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

V a l u e

0

RESET

R e a d / W r i t e

R/W

. 7 and . 6

D + / P S 2 C o n f i g u r a t i o n C o n trol Bits

0

1

0

1

0

1

Schmitt trigger input, falling edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

. 5 and . 4

D -/PS2 Configuration Control Bits

0

1

0

1

0

1

Schmitt trigger input, falling edge external interrupt

Schmitt trigger input, falling edge external interrupt with pull-up

N -CH open drain output mode

N -CH open drain output mode with pull-up

.4

D+/PS2 Interrupt E n a b l e B i t

0

1

External interrupt disable

External interrupt enable

.3

D -/PS2 Interrupt Enable Bit

0

1

External interrupt disable

External interrupt enable

.1

.0

D + / P S 2 I n t e r r u p t P e n d i n g B i t

0

1

No pending (when bit is read)/clear pending bit (when bit is write)

Pending (when bit is read)/no effect (when bit is write)

D -/ P S 2 I n t e r r u p t P e n d i n g B i t

0

1

No pending (when bit is read)/clear pending bit (when bit is write)

Pending (when bit is read)/no effect (when bit is write)

4-41

CONTROL REGISTERS

S3C9688/P9688

P W R M GR

— U S B Power Management Register

F8H

Bit Identifier

.7

–

.6

–

.5

–

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

–

RESET

R e a d / W r i t e

–

R/W

.7–.5

.4

Not used for C9688/P9688

D A T A + m o n i t o r i n g B i t

0

1

DATA+ is zero

DATA - is one

.3

D A T A - monitoring Bit

0

1

DATA - is zero

DATA - is one

.2

C l e a r S u s p e n d C o u n t e r B i t

0

1

-

Clear internal suspend counter register..

.1

.0

Not used for S3P9688

S U S P E N D S t a t u s B i t

0

Cleared when function receives resume signal from the host while in suspend

m o d e

1

This bit is set when SUSPEND interrupt occur

4-42

S3C9688/P9688

CONTROL REGISTERS

SYM

— System Mode Register

DFH

Bit Identifier

.6

–

.5

–

.4

–

.3

–

.2

0

.1

0

.0

0

.7

–

V a l u e

RESET

R e a d / W r i t e

–

R/W

.7–.3

.2

Not used for S3C9688/P9688

Global Interrupt Enable Bit

(note)

0

1

Disable global interrupt processing

Enable global interrupt processing

. 1 and . 0

P a g e S e l e c t i o n B i t s

0

Addressing page 0 locations for S3C9688/P9688

Not allowed in S3C9688/P9688

Other values

NOTE

:

SYM must be selected bit 1 and 0 into 00 for S3C9688/P9688.

4-43

CONTROL REGISTERS

S3C9688/P9688

T0CON _{— Timer 0 Control Register}

D2H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

. 7 and . 6

T0 Counter Input Clock Selection Bits

0

1

0

1

0

1

CPU clock/4096

CPU clock/256

C P U c l o c k / 8

Invalid selection

. 5 and . 4

T 0 O p e r a t i n g M o d e S e l e c t i o n B i t s

0

Interval timer mode (The counter is automatically cleared whenever T0DATA

value equals to T0CNT value)

0

1

0

1

Invalid selection

Overflow mode (OVF interrupt can occur)

.3

.2

.1

.0

T0 Counter Clear Bit (T0CLR)

0

1

No effect when written

Clear T0 counter

T0 Overflow Interrupt Enable Bit (T0OVF)

0

1

Disable T0 overflow interrupt

Enable T0 overflow interrupt

T0 Match Interrupt Enable Bit (T0INT)

0

1

Disable T0 match interrupt

Enable T0 match interrupt

T0 Interrupt Pending Bit (T0PND)

0

1

No interrupt pending/

Clear this pending bit (when write)

Interrupt is pending(when read)/No effect (when write)

NOTE

:

When you write a "1" to T0CON.3, the timer 0 counter is cleared. The bit is then cleared automatically to "0".

4-44

S3C9688/P9688

CONTROL REGISTERS

USBCON _{— USB Control Register}

F E H

Bit Identifier

.7

–

.6

–

.5

0

.4

0

.3

1

.2

0

.1

1

.0

1

V a l u e

RESET

R e a d / W r i t e

. 7 and . 6

.5

–

R/W

R

R e s e r v e d

DP/DM Control Bit

0

1

DP/DM can not be individually controlled by MCU

DP/DM can be individually controlled by MCU to set USBCON. 4 and USBCON. 3

.4

.3

.2

.1

.0

DP Status Bit

0

1

DP is low

DP is high

DM Status Bit

0

1

DM is low

DM is high

U S B R e s e t M C U B i t

0

1

USB which is been on RESET can not make MCU reset

USB which is been on RESET can be able to reset MCU

M C U r e s e t U S B B i t

0

1

No effect

MCU forces USB be reset

U S B R E S E T S i g n a l R e c e i v e B i t

0

1

USB Reset is detected.

USB Reset is undetected

4-45

CONTROL REGISTERS

S3C9688/P9688

USBINT _{— USB Interrupt Enable Register}

F7H

Bit Identifier

.7

–

.6

–

.5

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

–

RESET

Re ad/Write

–

R/W

.7–.5

.4

Not used for C9688/P9688

USB Reset Interrupt Pending Bit

0

1

Disable USB Reset Interrupt

Enable USB Reset Interrupt

.3

.2

.1

.0

E N D P O I N T 2 I n t e r r u p t P e n d i n g B i t

0

1

Disable ENDPOINT 2 interrupt

Enable ENDPOINT 2 interrupt

S U S P E N D / R E S U M E I n t e r r u p t E n a b l e B i t

0

1

Disable SUSPEND and RESUME interrupt

Enable SUSPEND and RESUME interrupt

E N D P O I N T 1 I n t e r r u p t P e n d i n g B i t

0

1

Disable ENDPOINT 1 interrupt

Enable ENDPOINT 1 interrupt

ENDP OINT0 Interrupt Pending Bit

0

1

Disable ENDPOINT 0 interrupt

Enable ENDPOINT 0 interrupt

4-46

S3C9688/P9688

CONTROL REGISTERS

USBPND _{— USB Interrupt Pending Register}

F6H

Bit Identifier

.7

–

.6

–

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

V a l u e

RESET

R e a d / W r i t e

–

R/W

.7–.6

.5

Not used for C9688/P9688

USB Reset Interrupt Pending Bit

0

1

No effect (Write 1, this bit is cleared )

This bit is set, when USB bus reset is detected on the bus.

.4

.3

.2

.1

.0

E N D P O I N T 2 I n t e r r u p t P e n d i n g B i t

0

1

No effect (Write 1, this bit is cleared)

This bit is set, when endpoint2 needs to be serviced

R E S U M E I n t e r r u p t P e n d i n g B i t

0

1

No effect (Write 1, this bit is cleared)

While in suspend mode, if resume signaling is received this bit gets set

S U S P E N D I n t e r r u p t P e n d i n g B i t

0

1

No effect (Write 1, this bit is cleared )

This bit is set, when suspend signaling is received

E N D P O I N T 1 I n t e r r u p t P e n d i n g B i t

0

1

No effect (Write 1, this bit is cleared)

This bit is set, when endpoint1 needs to be serviced

E N D P O I N T 0 I n t e r r u p t P e n d i n g B i t

0

1

No effect (Write1, this bit is cleared )

This bit is set, while endpoint 0 needs to serviced. It is set under the following

conditions;

—

O UT _PKT _RDY is set

IN_PKT_RDY get cleared

SENT_STALL gets set

SETUP_DATA_END gets cleared

S E T U P _ T R A N S F E R _ E N D g e t s s e t

4-47

CONTROL REGISTERS

S3C9688/P9688

USXCON

— USB Selection and Signal Crossover Point Control Register

D3H

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

.0

0

V a l u e

0

RESET

R e a d / W r i t e

R/W

.7

U S B / P S 2 M o d e s e l e c t B i t

0

1

P S 2 M o d e

U S B M o d e

.6

U S B P u l l -Up Control register

0

1

Pull-Up Disable

Pull-Up Enable

.5–.0

USB Signal Crossover Point Control Bit

Edge delay

Control

Bit 5, (2)

Bit 4, (1)

Bit 3, (0)

Delay

Value

Delay

Unit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

0

1

2

4

RISE

edge

0

(about)

2.5nsec

F A L L

edge

1

NOTE:

Bit 5, 4, 3: DM, Bit 2, 1, 0: DP

4-48

S3C9688/P9688

CONTROL REGISTERS

N O T E S

4-49

S3C9688/P9688

INTERRUPT STRUCTURE

5

INTERRUPT STRUCTURE

OVERVIEW

The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt

sources can be serviced through a interrupt vector which is assig ned in ROM address 0000H– 0001H.

VECTOR

SOURCES

S1

S2

S3

Sn

0000H

0001H

NOTES:

1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).

2. The number of Sn value is expandable.

F i g u r e 5 -1. S3C9-Series Interrupt Type

I N T E R R U P T P R O C E S S I N G C O N T R O L P O I N T S

Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. The

major features of system -level control in the interrupt structure are as follows:

—

Global interrupt enable and disable (by EI and DI instructions)

Interrupt sourc e enable and disable settings in the corresponding peripheral control register(s)

ENABLE/DISABLE INTERR U P T I N S T R U C T I O N S ( E I, DI)

The system mode register, SYM (DFH), is used in settings interrupt processing enabled or disabled.

SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable

Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable

interrupt processing. Although you can manipulate SYM.2 directly to enable and disable interrupts during normal

operation, we recommend that you use the EI and DI instructions for this purpose.

5-1

INTERRUPT STRUCTURE

S3C9688/P9688

I N T E R R U P T P E N D I N G F U N C T I O N T Y P E S

When the interrupt service routine has been executed, the appropriate pending bit must be cleared in the application

program's service routine before the return from interrupt subroutine (IRET) occurs.

I N T E R R U P T P R I O R I T Y

Because there is not a interrupt priority register in SAM88RCRI, the order of service is determined by a sequence of

source which is executed in interrupt service routine.

"EI" Instruction

S

R

Q

Execution

Interrupt Pending Register

RESET

Vector

Interrupt

Cycle

Source

Interrpt priority

Interrupts

is determind by

software polling

method

Source

Interrupt

Enable

Global Interrupt Control

(EI, DI instruction)

F i g u r e 5 -2. Interrupt Function Diagram

I N T E R R U P T S O U R C E S E R V I C E S E Q U E N C E

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request pending bit to "1".

2. The CPU generates an interrupt acknowledge signal.

3. The service routine starts and the source's pending flag is cleared to "0" by software.

4. Interrupt priority must be determined by software polling method.

5-2

S3C9688/P9688

INTERRUPT STRUCTURE

I N T E R R U P T S E R V I C E R O UTINES

Before an interrupt request can be serviced, the following conditions must be met:

—

Interrupt processing must be enabled (EI, SYM.2 = "1")

Interrupt must be enabled at the interrupt's source (peripheral control re gister)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The

CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.2 = "0")

to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags (FLAGs) to stack.

3. Branch to the interrupt vector to fetch the service routine's address.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the

PC and status flags and sets SYM.2 to "1"(EI), allowing the CPU to process the next interrupt request.

G E N E R A T I N G I N T E R R U P T V E C T O R A D D R E S S E S

The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt

processing follows this sequence:

1. Push the program counter's low-byte value to stack.

2. Push the program counter's high-byte value to stack.

3. Push the FLAGS register values to stack.

4. Fetch the service routine's high-byte address from the vector address 0000H.

5. Fetch the service routine's low-byte address from the vector address 0001H.

6. Branch to the service routine specified by the 16-bit vector address.

5-3

INTERRUPT STRUCTURE

S3C9688/P9688

S3C9688/P9688 INTERRU P T S T R U C T U R E

The S3C9688/P9688 microcontroller has 29 peripheral interrupt sources:

—

Timer 0 match interrupt

Timer 0 overflow interrupt

Eight external interrupts for port 2, P2.0– P2. 7

Four external interrupts for port 4, P4.0– P4. 3

D -/PS2 and D+/Ps2 external interrupts (only in PS2 mode)

USB EP0, 1, 2 Interrupt

Suspend interrupt

Resume interrupt

Vector

Pending Bits

Enable/Disable

Sources

Timer 0 Match Interrupt

T0CON.1

T0CON.2

P0INT.X

P2INT.X

T0CON

Timer 0 Overflow Interrupt

P0.X External Interrupt

P2.X External Interrupt

P4.0-3 External Interrupt

Endpoint 0 Interrupt

Endpoint 1 Interrupt

Endpoint 2 Interrupt

D-/PS2 Interrupt

P0PND.X

P2PND.X

P4INTPND.0-3

P4INTPND.0

P4INTPND.1

P4INTPND.4

PS2CONINT.0

PS2CONINT.1

USBPND.2

P4INTPND.4-7

0000H

USBINT.0

USBINT.1

(EI/DI)

SYM.2

USBINT.3

PS2CONINT.2

D+/PS2 Interrupt

PS2CONINT.3

USBINT.2

Suspend Interrupt

Resume Interrupt

USBPND.3

USBINT.2

NOTE:

"X" means 0-7 bit.

F i g u r e 5 -3. S3C9688/P9688 Interrupt Structure

5-4

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

6

SAM88RCRI INSTRUCTION SET

OVERVIEW

The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit

arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O

control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate,

and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set.

R E G I S T E R A D D R E S S I N G

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is

specified. Paired registers can be used to construct 13-bit program memory or data memory addresses. For detailed

information about register addressing, please refer to Section 2, "Address Spaces".

A D D R E S S I N G M O D E S

There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and

Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing

Modes".

6-1

SAM88RI INSTRUCTION SET

S3C9688/P9688

T a b l e 6 -1. Instruction Group Summary

O p e r a n d s Instruction

M n e m o n i c

Load Instructions

CLR

d s t

Clear

LD

dst,src

d s t

Load

LDC

Load program memory

Load external data memory

LDE

L D C D

L D E D

L D C I

L D E I

P O P

P U S H

Load program memory and decrement

Load external data memory and decrement

Load program memory and increment

Load external data memory and increment

Pop from stack

src

P u s h t o s t a c k

Arithmetic Instructions

A D C

A D D

CP

dst,src

d s t

Add with carry

A d d

Compare

D E C

INC

Dec rement

Increment

Subtract with carry

Subtract

d s t

S B C

S U B

dst,src

Logic Instructions

A N D

C O M

O R

dst,src

d s t

Logical AND

Complement

dst,src

Logical OR

XOR

Logical exclusive OR

6-2

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

T a b l e 6 -1. Instruction Group Summary (Continued)

M n e m o n i c

O p e r a n d s

Instruction

Program Control Instructions

C A L L

IRET

JP

d s t

Call procedure

Interrupt return

c c , d s t

d s t

Jump on condition code

Jump unconditional

Jump relative on condition code

Return

JP

JR

c c , d s t

R E T

Bit Manipulation Instru ctions

TCM

TM

dst,src

Test complement under mask

Test under mask

Rotate and Shift Instructions

RL

d s t

Rotate left

RLC

R R

Rotate left through carry

Rotate right

R R C

S R A

Rotate right through carry

Shift right arithmetic

CPU Control Instructions

C C F

D I

Complement carry flag

Disable interrupts

Enable interrupts

Enter Idle mode

No operation

E I

IDLE

N O P

R C F

S C F

S T O P

Reset carry flag

Set carry flag

Enter Stop mode

6-3

SAM88RI INSTRUCTION SET

F L A G S R E G I S T E R ( F L A G S )

S3C9688/P9688

The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits,

F L A G S . 4 – FLAGS.7, can be tested and used with conditional jump instructions;

FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load

instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags

register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the

AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will

occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Carry flag (C)

Not mapped

Zero flag (Z)

Sign flag (S)

Overflow (V)

F i g u r e 6 -1. System Flags Register (FLAGS)

F L A G D E S C R I P T I O N S

O v e r f l o w F l a g ( F L A G S . 4 , V )

The V flag is set to "1" when the result of a two's -complement operation is greater than + 127 or less than – 128. It is

also cleared to "0" following logic operations.

S i g n F l a g ( F L A G S . 5 , S )

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic

zero indicates a positive number and a logic one indicates a negative number.

Zero Flag (FLAGS. 6, Z)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that

test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

C a r r y F l a g ( F L A G S . 7 , C )

The C flag is set to "1" if the result from an arithmetic operation generates a carry -out from or a borrow to the bit

position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register.

Program instructions can set, clear, or complement the carry flag.

7

6-4

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

I N S T R U C T I O N S E T N O T A T I O N

T a b l e 6 -2. Flag Notation Conventions

F l a g

Description

Carry flag

C

Z

S

V

0

1

*

Zero flag

Sign flag

Overflow flag

Cleared to logic zero

Set to logic one

Set or cleared according to operation

Value is unaffected

Value is undefined

–

x

T a b l e 6 -3. Instruction Set Symbols

S y m b o l

Description

Destination operand

d s t

Source operand

src

Indirect register address prefix

Pro gram counter

@

P C

Flags register (D5H)

F L A G S

Immediate operand or register address prefix

Hexadecimal number suffix

Decimal number suffix

Binary number suffix

#

H

D

B

Opcode

opc

6-5

SAM88RI INSTRUCTION SET

S3C9688/P9688

T a b l e 6 -4. Instruction Notation Conventions

Description A c t u a l O p e r a n d R a n g e

Notation

c c

r

Condition code

See list of condition codes in Table 6-6.

Rn (n = 0– 15)

Working register only

rr

Working register pair

RRp (p = 0, 2, 4, ..., 14)

R

Register or working register

Register pair or working register pair

reg or Rn (reg = 0– 255, n = 0– 15)

R R

reg or RRp (reg = 0– 254, even number only, where

p = 0, 2, ..., 14)

Ir

IR

Indirect working register only

@ R n ( n = 0 – 15)

Indirect register or indirect working register

Indirect working register pair only

@Rn or @reg (reg = 0– 255, n = 0– 15)

@RRp (p = 0, 2, ..., 14)

Irr

IRR

Indirect register pair or indirect working

register pair

@RRp or @reg (reg = 0– 254, even only, where

p = 0, 2, ..., 14)

X

Indexed addressing mode

#reg[Rn] (reg = 0– 255, n = 0– 15)

XS

Indexed (short offset) addressing mode

#addr[RRp] (addr = range – 128 to +127, where

p = 0, 2, ..., 14)

x l

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 0– 8191, where

p = 0, 2, ..., 14)

da

ra

Direct addressing mode

Relative addressing mode

addr (addr = range 0– 8191)

addr (addr = number in the range +127 to – 128 that is

an offset relative to the address of the next instruction)

im

Immediate addressing mode

#data (data = 0– 255)

6-6

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

T a b l e 6 -5 . O p c o d e Q u ic k R e f e r e n c e

O P C O D E M A P

L O W E R N I B B L E ( H E X )

–

0

1

2

3

4

5

6

7

U

P

E

R

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

D E C

R1

D E C

IR1

A D D

r1,r2

A D D

r1,Ir2

A D D

R2, R1

IR2,R1

R1,IM

RLC

R1

RLC

IR1

A D C

r1,r2

A D C

r1,Ir2

A D C

R2, R1

IR2,R1

R1,IM

INC

R1

INC

IR1

S U B

r1,r2

S U B

r1,Ir2

R2, R1

IR2,R1

R1,IM

JP

S B C

r1,r2

S B C

r1,Ir2

S B C

IRR1

R2, R1

IR2,R1

R1,IM

O R

r1,r2

r1,Ir2

R2, R1

IR2,R1

R1,IM

P O P

R1

P O P

IR1

A N D

r1,r2

A N D

r1,Ir2

A N D

R2, R1

IR2,R 1

R1,IM

N

I

C O M

R1

C O M

IR1

TCM

r1,r2

TCM

r1,Ir2

R2, R1

IR2,R1

R1,IM

P U S H

R2

P U S H

IR2

TM

r1,r2

r1,Ir2

R2, R1

IR2,R1

R1,IM

B

L

E

LD

r1, x, r2

RL

R1

RL

LD

IR1

r2, x, r1

CP

LDC

r1,r2

r1,Ir2

R2, R1

IR2,R1

R1,IM

r1, Irr2, xL

CLR

R1

CLR

IR1

XOR

r1,r2

XOR

LDC

r1,Ir2

R2, R1

IR2,R1

R1,IM

r2, Irr2, xL

R R C

R1

R R C

IR1

LDC

LD

r1,Irr2

r1, Ir2

H

E

X

S R A

R1

S R A

IR1

LDC

LD

r2,Irr1

IR1,IM

Ir1, r2

R R

R1

R R

L D C D

r1,Irr2

LDC I

LD

LDC

IR1

r1,Irr2

R2, R1

R2,IR1

R1,IM

r1, Irr2, xs

C A L L

IRR1

LD

C A L L

D A 1

LDC

IR2,R1

r2, Irr1, xs

6-7

SAM88RI INSTRUCTION SET

S3C9688/P9688

T a b l e 6 -5 . O p c o d e Q u i c k R e f e r e n c e ( C o n t i n u e d )

O P C O D E M A P

L O W E R N I B B L E ( H E X )

–

0

8

9

A

B

C

D

E

F

U

P

E

R

LD

JR

LD

JP

INC

r1

r1,R2

r2,R1

cc, RA

r1,IM

cc, DA

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

¯

N

I

IDLE

S T O P

D I

B

L

E

E I

R E T

IRET

R C F

S C F

C C F

N O P

H

E

X

LD

JR

LD

JP

INC

r1

r1,R2

r2,R1

cc, RA

r1,IM

cc, DA

6-8

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

C O N D I T I O N C O D E S

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under

which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a

compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump

instructions.

T a b l e 6 -6 . C o n d i t i o n C o d e s

Binary

0000

M n e m o n i c

Description

F l a g s S e t

F

T

Always false

Always true

Carry

–

1000

–

0111 (1)

1111 (1)

0110 (1)

1110 (1)

1101

C

C = 1

C = 0

Z = 1

Z = 0

S = 0

S = 1

V = 1

V = 0

Z = 1

Z = 0

N C

Z

No carry

Zero

N Z

P L

Not zero

Plus

0101

M I

Minus

0100

O V

N O V

E Q

NE

G E

LT

Overflow

No overflow

E q u a l

1100

0110 (1)

1110 (1)

1001

Not equal

Greater than or equal

Less than

(S XOR V) = 0

(S XOR V) = 1

(Z OR (S XOR V)) = 0

(Z OR (S XOR V)) = 1

C = 0

0001

1010

G T

LE

Greater than

0010

Less than or equal

Unsigned greater than or equal

Unsigned less than

Unsigned greater than

Unsigned less than or equal

1111 (1)

0111 (1)

1011

U G E

U L T

U G T

ULE

C = 1

(C = 0 AND Z = 0) = 1

(C OR Z) = 1

0011

NOTES:

1.

Indicate condition codes that are related to two different mnemonics but which test the same flag.

For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;

after a CP instruction, however, EQ would probably be used.

2.

For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-9

SAM88RI INSTRUCTION SET

S3C9688/P9688

I N S T R U C T I O N D E S C R I P T IONS

This section contains detailed information and programming examples for each instruction in the SAM88RCRI

instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The

following information is included in each instruction description:

—

Instruction name (mnemonic)

Full instruction name

Source/destination format of the instruction operand

Shorthand notation of the instruction's operation

Textual description of the instruction's effect

Specific flag settings affected by the instruction

Detailed description of the instruction's format, execution time, and addressing mode(s)

Programming example(s) explaining how to use the instruction

6-10

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

ADC _{— Add With C arry}

A D C

dst,src

O p e r a t i o n :

dst

dst + src + c

¬

The source operand, along with the setting of the carry flag, is added to the destination operand and

the sum is stored in the destination. The contents of the source are unaffected. Two's -complement

addition is performed. In multiple precision arithmetic, this instruction permits the carry from the

addition of low-order operands to be carried into the addition of high-order operands.

Flags:

C :

Z:

Set if there is a carry from the most significant bit of the result; cleared otherwise.

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result is negative; cleared otherwise.

Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D :

H :

Always cleared to "0".

Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

12

13

r

lr

src

d s t

src

3

6

14

15

R

IR

d s t

6

16

R

IM

E x a m p l e s :

Given: R1

=

10H, R2

= 0AH:

=

03H, C flag = "1", register 01H

=

20H, register 02H

=

03H, and

register 03H

A D C

R1, R2

R1

R 1

=

14H, R2

1 B H , R 2

=

03H

0 3 H

®

R 1 , @ R 2

01H,02H

0 1 H , @ 0 2 H

01H,#11H

=

®

Register 01H

=

24H, register 02H

2BH, register 02H

32H

=

03H

=

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and

the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and

the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

6-11

SAM88RI INSTRUCTION SET

S3C9688/P9688

ADD _{— Add}

A D D

dst,src

O p e r a t i o n :

dst

dst + src

¬

The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. Two's -complement addition is performed.

Flags:

C :

Z:

Set if there is a carry from the most significant bit of the result; cleared otherwise

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result is negative; cleared otherwise.

Set if arithmetic overflow occurred, that is, if both operands are of the same sign and

the result is of the opposite sign; cleared otherwise.

D :

H :

Always cleared to "0".

Set if a carry from the low-order nibble occurred.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

02

03

r

lr

src

d s t

src

3

6

04

05

R

IR

d s t

6

06

R

IM

E x a m p l e s :

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

A D D

R1, R2

R1

=

15H, R2

1CH, R2

=

03H

®

R 1 , @ R 2

01H,02H

0 1 H , @ 0 2 H

01H,#25H

=

Register 01H

=

24H, register 02H

2BH, register 02H

46H

=

03H

=

In the first example, destination working regis ter R1 contains 12H and the source working register

R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register

R1.

6-12

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

AND _{— Logical AND}

A N D

dst,src

O p e r a t i o n :

dst

dst AND src

¬

The source operand is logically ANDed with the destination operand. The result is stored in the

destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in

the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source

are unaffected.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result bit 7 is set; cleared otherwise.

Always cleared to "0".

Unaffected.

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

52

53

r

lr

src

d s t

3

6

54

55

R

IR

d s t

src

6

56

R

IM

E x a m p l e s :

Given: R1

=

12H, R2

=

03H, register 01H

=

21H, register 02H

03H

02H, R2 = 03H

=

03H, register 03H

=

0AH:

A N D

R1, R2

R1

=

02H, R2 =

®

R 1 , @ R 2

01H,02H

0 1 H , @ 0 2 H

01H,#25H

®

Register 01H

=

01H, register 02H

00H, register 02H

21H

=

03H

In the first example, destination working register R1 contains the value 12H and the source working

register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with

the destination operand value 12H, leaving the value 02H in register R1.

6-13

SAM88RI INSTRUCTION SET

S3C9688/P9688

CALL

— Call Procedure

C A L L

d s t

O p e r a t i o n :

S P

S P – 1

P C L

¬

@ S P

S P

S P – 1

P C H

@ S P

P C

d s t

The current contents of the program counter are pushed onto the top of the stack. The program

counter value used is the address of the first instruction following the CALL instruction. The specified

destination address is then loaded into the program counter and points to the first instruction of a

procedure. At the end of the procedure the return instruction (RET) can be used to return to the

original program flow. RET pops the top of the stack back into the program counter.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

3

14

F6

DA

d s t

2

12

F4

IRR

E x a m p l e s :

Given: R 0

=

1 5 H , R 1 = 2 1 H , P C

=

1 A 4 7 H , a n d S P

=

0 B 2 H :

C A L L

1521H

S P

= 0 B 0 H

®

(Memory locations 00H

=

1AH, 01H = 4AH, where 4AH

is the address that follows the instruction.)

C A L L

@ R R 0

S P = 0 B 0 H ( 0 0 H 1 A H , 0 1 H 4 9 H )

=

®

In the first example, if the program counter value is 1A47H and the stack pointer contains the value

0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The

stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the

address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the

statement "CALL @RR0" produces the same result except that the 49H is stored in stack location

01H (because the two-byte instruction format was used). The PC is then loaded with the value

1521H, the address of the first instruction in the program sequence to be executed.

6-14

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

CCF

— Complement Carry Flag

C C F

O p e r a t i o n :

C

NOT

C

¬

The carry flag (C) is complemented. If C

=

"1", the value of the carry flag is changed to logic zero; if

C

= "0", the value of the carry flag is changed to logic one.

Flags:

C :

Complemented.

No other flags are affected.

F o r m at:

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

4

E F

E x a m p l e :

Given: The carry flag

C C F

= "0":

If the carry flag

= "0", the CCF instruction complements it in the FLAGS register (0D5H), changing

its value from logic zero to logic one.

6-15

SAM88RI INSTRUCTION SET

S3C9688/P9688

CLR

— Clear

C L R

d s t

dst

O p e r a t i o n :

"0"

¬

The destination location is cleared to "0".

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

B 0

B 1

R

IR

E x a m p l e s :

Given: Register 00H

=

4FH, register 01H

=

02H, and register 02H

=

5EH:

00H

CLR

00H

Register 00H

Register 01H

=

00H

®

@ 0 1 H

02H, register 02H =

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H

value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)

addressing mode to clear the 02H register value to 00H.

6-16

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

COM

— Complement

C O M

d s t

dst

O p e r a t i o n :

N O T d s t

¬

The contents of the destination location are complemented (one's comple ment); all "1s" are

changed to "0s", and vice-versa.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result bit 7 is set; cleared otherwise.

Always reset to "0".

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

60

61

R

IR

E x a m p l e s :

Given: R1

=

07H and register 07H

=

0F1H:

0 F 8 H

C O M

R1

R 1 =

®

@ R 1

R1

=

07H, register 07H

=

0EH

®

In the first example, destination working register R1 contains the value 07H (00000111B). The

statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and

vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of

destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-17

SAM88RI INSTRUCTION SET

S3C9688/P9688

CP

— Compare

CP

dst,src

O p e r a t i o n :

dst – src

The source operand is compared to (subtracted from) the destination operand, and the appropriate

flags are set accordingly. The contents of both operands are unaffected by the comparison.

Flags:

C :

Z:

Set if a "borrow" occurred (src > dst); cleared otherwise.

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result is negative; cleared otherwise.

Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and

the sign of the result is of the same as the sign of the source operand; cleared otherwise.

D :

H :

Unaffected.

F o r m a t:

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

A 2

A 3

r

lr

src

d s t

src

3

6

A 4

A 5

R

IR

d s t

6

A 6

R

IM

E x a m p l e s :

1. Given: R1

CP

=

02H and R2

R1, R2

= 03H:

Set the C and S flags

®

Destination working register R1 contains the value 02H and source register R2 contains the value

03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value

(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".

2. Given: R 1 = 0 5 H a n d R 2 = 0 A H :

CP

JP

R1, R2

UGE, SKIP

R1

INC

LD

SKIP

R3, R1

In this example, destination working register R1 contains the value 05H which is less than the

contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"

and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"

executes, the value 06H remains in working register R3.

6-18

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

DEC _{— Decrement}

D EC

d s t

dst

O p e r a t i o n :

dst – 1

¬

The contents of the destination operand are decremented by one.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if result is negative; cleared otherwise.

S :

V :

Set if arithmetic overflow occurred, that is, dst value is – 128(80H) and result value

is +127 (7FH); cleared otherwise.

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

00

01

R

IR

E x a m p l e s :

Given: R1

=

03H and register 03H

=

10H:

0 2 H

D E C

R1

R 1 =

®

@ R 1

Register 03H

=

0FH

®

In the first example, if working register R1 contains the value 03H, the statement "DEC R1"

decrements the hexadecimal value by one, leaving the value 02H. In the second example, the

statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one,

leaving the value 0FH.

6-19

SAM88RI INSTRUCTION SET

S3C9688/P9688

DI

— Disable Interrupts

D I

O p e r a t i o n :

S Y M ( 2 )

0

¬

Bit zero of the system mode register, SYM.2, is cleared to "0", glo bally disabling all interrupt

processing. Interrupt requests will continue to set their respective interrupt pending bits, but the

CPU will not service them while interrupt processing is disabled.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

4

8F

E x a m p l e :

Given: S Y M

D I

=

0 4 H :

If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register

and clears SYM.2 to "0", disabling interrupt processing.

6-20

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

EI _{— Enable Interrupts}

EI

O p e r a t i o n :

S Y M ( 2 )

1

¬

An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be

serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled

(by executing a DI instruction), it will be serviced when you execute the EI instruction.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

4

9F

E x a m p l e :

Given: S Y M

E I

=

0 0 H :

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement

"EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt

processing).

6-21

SAM88RI INSTRUCTION SET

S3C9688/P9688

IDLE _{— Idle Operation}

I D L E

O p e r a t i o n :

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle

mode can be released by an interrupt request (IRQ) or an external reset operation.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

1

4

6F

–

E x a m p l e :

The instruction

IDLE

stops the CPU clock but not the system clock.

6-22

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

INC _{— Increment}

INC

d s t

dst

O p e r a t i o n :

dst + 1

¬

The contents of the destination operand are incremented by one.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result is negative; cleared otherwise.

S :

V :

Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is –

128(80H); cleared otherwise.

D :

H :

Unaffected.

F o rm a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

|

opc

1

4

rE

r

=

0

to F

opc

d s t

2

4

20

21

R

IR

E x a m p l e s :

Given: R0

=

1BH, register 00H

=

0CH, and register 1BH = 0FH:

INC

R0

R 0 = 1 C H

®

00H

Register 00H

= 0DH

@ R 0

R0 1BH, register 01H = 10H

=

®

In the first example, if destination working register R0 contains the value 1BH, the statement "INC

R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it

contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of

register 1BH from 0FH to 10H.

6-23

SAM88RI INSTRUCTION SET

S3C9688/P9688

IRET _{— Interrupt Return}

IRET

O p e r a t i o n :

F L A G S

@ S P

¬

S P

+

1

¬

P C

@ S P

¬

S P

+

2

¬

S Y M ( 2 )

1

¬

This instruction is used at the end of an interrupt service routine. It restores the flag register and the

program counter. It also re -enables global interrupts.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

F o r m a t :

IRET

B y t e s

C y c l e s

O p c o d e

( H e x )

(Normal)

opc

1

6

B F

6-24

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

JP

— Jump

JP

cc, dst

d s t

(Conditional)

JP

(Unconditional)

O p e r a t i o n :

If cc is true, PC

d s t

¬

The conditional JUMP instruction transfers program control to the destination address if the

condition specified by the condition code (cc) is true; otherwise, the instruction following the JP

instruction is executed. The unconditional JP simply replaces the contents of the PC with the

contents of the specified register pair. Control then passes to the statement addressed by the PC.

Flags:

No flags are affected.

(1)

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

(2)

opc

(3)

cc

|

d s t

3

8

c c D

DA

cc = 0 to F

opc

d s t

2

8

30

four bits.

20H:

IRR

NOTES:

1.

2.

The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both

E x a m p l e s :

Given: The carry flag (C) = "1", register 00

=

01H, and register 01

1 0 0 0 H , P C 1 0 0 0 H

=

JP

C , L A B E L _ W

@ 0 0 H

L A B E L _ W

P C

=

®

=

0 1 2 0 H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement

"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to

that location. Had the carry flag not been set, control would then have passed to the statement

immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of

the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-25

SAM88RI INSTRUCTION SET

S3C9688/P9688

JR

— Jump Relative

JR

c c , d s t

O p e r a t i o n :

If cc is true, PC

P C

+

d s t

¬

If the condition specified by the condition code (cc) is true, the relative address is added to the

program counter and control passes to the statement whose address is now in the program counter;

otherwise, the instruction following the JR instruction is executed (See list of condition codes).

The range of the relative address is +127, – 128, and the original value of the program counter is

taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

(1)

opc

(2)

cc

|

d s t

2

6

c c B

RA

cc = 0 to F

NOTE

:

In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.

E x a m p l e :

Given: The carry flag = "1" and LABEL_X

= 1FF7H:

JR C , L A B E L _ X P C 1 F F 7 H

=

®

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will

pass control to the statement whose address is now in the PC. Otherwise, the program instruction

following the JR would be executed.

6-26

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

LD

— Load

L D

dst,src

O p e r a t i o n :

dst

src

¬

The contents of the source are loaded into the destination. The source's c ontents are unaffected.

No flags are affected.

Flags:

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

IM

R

dst

src

|

opc

src

d s t

|

2

4

rC

r8

r

|

2

3

4

r9

R

r

r = 0 to F

opc

dst

src

4

C7

D7

r

lr

r

Ir

src

d s t

src

6

E 4

E 5

R

IR

6

E 6

D6

R

IM

IR

opc

src

d s t

3

6

F5

87

97

IR

r

R

x [r]

r

dst

src

|

src

dst

x

x [r]

6-27

SAM88RI INSTRUCTION SET

S3C9688/P9688

LD

— Load

L D

(Continued)

E x a m p l e s :

Given: R0

=

01H, R1

=

0AH, register 00H

=

01H, register 01H

0FFH:

= 20H,

register 02H

=

02H, LOOP

=

30H, and register 3AH =

LD

R0,#10H

R0,01H

R 0

R0

=

1 0 H

20H, register 01H

01H, R0

01H

0AH, register 01H

®

=

20H

01H

01H,R0

Register 01H

=

R 1 , @ R 0

@ R 0 , R 1

00H,01H

R1

R0

=

20H, R0

01H, R1

=

0AH

Register 00H

Register 02H

Register 00H

=

20H, register 01H

=

20H

01H

0 2 H , @ 0 0 H

20H, register 00H

0AH

®

0 0 H , # 0 A H

=

@00H, #10H

@ 0 0 H , 0 2 H

=

01H, register 01H

=

10H

02, register 02H

= 02H

R0, #LOOP[R1]

#LOOP[R0], R1

R 0

=

0 F F H , R 1

=

0 A H

Register 31H

=

0AH, R0

=

01H, R1 = 0AH

6-28

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

LDC/LDE

— Load Memory

L DC/ L DE

dst,src

dst

O p e r a t i o n :

src

¬

This instruction loads a byte from program or data memory into a working register or vice-versa. The

source values are unaffected. LDC refers to program m emory and LDE to data memory. The

assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data

m e m o r y .

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

1.

2.

3.

4.

5.

opc

dst

src

dst

src

dst

|

src

dst

src

dst

src

2

10

C3

D3

E7

F7

A7

r

Irr

2

3

4

10

12

14

Irr

r

XS

XL

r

XS [rr]

r

XS [rr]

r

XL

XL [rr]

L

H

6.

7.

opc

XL

DA

src

|

dst

4

14

B7

A7

B7

A7

B7

XL [rr]

r

DA

r

L

DA

dst | 0000

src | 0000

dst | 0001

src | 0001

r

L

H

8.

DA

r

L

H

9.

DA

r

10.

DA

NOTES:

1.

2.

3.

4.

The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.

For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte.

For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes.

The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values,

used in formats 9 and 10, are used to address data memory.

6-29

SAM88RI INSTRUCTION SET

S3C9688/P9688

LDC/LDE _{— Load Memory}

L DC/ L DE

(Continued)

E x a m p l e s :

Given: R0

=

11H, R1

AAH, 0103H

External data memory locations 0061H

=

34H, R2

=

01H, R3

=

04H, R4

=

00H, R5

=

60H; Program memory

locations 0061

=

4FH, 0104H

=

1A, 0105H

=

6DH, and 1104H

= 88H.

=

BBH, 0103H

=

5FH, 0104H

=

2AH, 0105H = 7DH,

and 1104H

= 98H:

LDC

R 0 , @ R R 2

@ R R 2 , R 0

;

R0

R 0

R0

R 0

contents of program memory location 0104H

1 A H , R 2 0 1 H , R 3 0 4 H

contents of external data memory location 0104H

2 A H , R 2 0 1 H , R 3 0 4 H

¬

=

LDE

¬

=

LDC *

11H (contents of R0) is loaded into program memory

location 0104H (RR2),

working registers R0, R2, R3

no change

®

LDE

LDC

LDE

@ R R 2 , R 0

11H (contents of R0) is loaded into external data memory

location 0104H (RR2),

working registers R0, R2, R3

no change

contents of program memory location 0061H

(01H + RR4),

®

R0,#01H[RR4]

R0

¬

R 0

R0

=

A A H , R 2

contents of external data memory location 0061H

BBH, R4 00H, R5 60H

= 0 0 H , R 3 = 6 0 H

R0,#01H[RR4]

#01H[RR4],R0

R0,#1000H[RR2]

¬

(01H + RR4), R0

=

(note)

LDC

11H (contents of R0) is loaded into program memory location

0061H (01H + 0060H)

LDE

LDC

LDE

11H (contents of R0) is loaded into external data memory

location 0061H (01H + 0060H)

R0

contents of program memory location 1104H

(1000H + 0104H), R0 88H, R2 01H, R3 04H

R0 contents of external data memory location 1104H

(1000H + 0104H), R0 98H, R2 01H, R3 04H

¬

=

¬

=

LDC

LDE

R0,1104H

R0

R 0

contents of program memory location 1104H, R0

contents of external data memory location 1104H,

9 8 H

= 88H

¬

=

(note)

LDC

1105H,R0

11H (contents of R0) is loaded into program memory location

1105H, (1105H) 11H

11H (contents of R0) is loaded into external data memory

location 1105H, (1105H) 11H

¬

LDE

¬

NOTE:

These instructions are not supported by masked ROM type devices.

6-30

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

LDCD/LDED

— Load Memory and Decrement

L D C D / L D E D

O p e r a t i o n :

dst,src

dst

src

rr – 1

¬

rr

¬

These instructions are used for user stacks or block transfers of data from program or data memory

to the register file. The address of the memory location is specified by a working register pair. The

contents of the source location are loaded into the destination location. The memory address is then

decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler

makes ‘ Irr’ an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

10

E 2

r

Irr

E x a m p l e s :

Given: R6

=

10H, R7

=

33H, R8

=

12H, program memory location 1033H

= 0DDH:

=

0CDH, and

external data memory location 1033H

L D C D

R 8 , @ R R 6

;

0CDH (contents of program memory location 1033H) is loaded

into R8 and RR6 is decremented by one

R8

0DDH (contents of data memory location 1033H) is loaded

into R8 and RR6 is decremented by one (RR6 RR6 – 1)

=

0CDH, R6

=

10H, R7

=

32H (RR6

RR6 – 1)

¬

L D E D

R 8 , @ R R 6

¬

R8

= 0DDH, R6 = 10H, R7 = 32H

6-31

SAM88RI INSTRUCTION SET

S3C9688/P9688

LDCI/LDEI

— Load Memory and Increment

LDCI/LDEI

O p e r a t i o n :

dst,src

dst

rr

src

+

¬

rr

1

¬

These instructions are used for user stacks or block transfers of data from program or data memory

to the register file. The address of the memory location is specified by a working register pair. The

contents of the source location are loaded into the destination location. The memory address is then

incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data mem ory. The assembler makes 'Irr'

even for program memory and odd for data memory.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

10

E 3

r

Irr

E x a m p l e s :

Given: R6

=

10H, R7

=

33H, R8

=

12H, program memory locations 1033H 0CDH and

=

1034H

=

0C5H; external data memory locations 1033H

=

0DDH and 1034H = 0D5H:

L D C I

R 8 , @ R R 6

;

0CDH (contents of program memory location 1033H) is loaded

into R8 and RR6 is incremented by one (RR6 R R 6 + 1 )

¬

R8

0DDH (contents of data memory location 1033H) is loaded

into R8 and RR6 is incremented by one (RR6 R R 6 + 1 )

= 0CDH, R6 = 10H, R7 = 34H

L D E I

¬

R8

= 0DDH, R6 = 10H, R7 = 34H

6-32

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

NOP _{— No Operation}

N O P

O p e r a t i o n :

No action is performed when the CPU executes this instruction. Typically, one or more NOPs are

executed in sequence in order to effect a timing delay of variable duration.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

4

F F

E x a m p l e :

When the instruction

N O P

is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution

time.

6-33

SAM88RI INSTRUCTION SET

S3C9688/P9688

OR _{— Logical OR}

O R

dst,src

O p e r a t i o n :

dst

dst OR src

¬

The source operand is logically ORed with the destination operand and the result is stored in the

destination. The contents of the source are unaffected. The OR operation results in a "1" being

stored whenever either of the corresponding bits in the two operands is a "1"; otherwis e a "0" is

stored.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result bit 7 is set; cleared otherwise.

Always cleared to "0".

Unaffected.

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

42

43

r

lr

src

d s t

3

6

44

45

R

IR

d s t

src

3

6

46

R

IM

E x a m p l e s :

Given: R0

=

15H, R1

= 8AH:

=

2AH, R2

=

01H, register 00H

=

08H, register 01H

=

37H, and

register 08H

O R

R0, R1

R 0

=

3 F H , R 1

37H, R2

=

2 A H

01H, register 01H

®

R 0 , @ R 2

00H,01H

0 1 H , @ 0 0 H

00H,#02H

R0

=

37H

0BFH

®

Register 00H

=

3FH, register 01H

08H, register 01H

0AH

=

®

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the

statement "OR R0, R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in

destination register R0.

The other examples show the use of the logical OR instruction with the various addressing modes

and formats.

6-34

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

POP

— POP From Stack

P O P

d s t

O p e r a t i o n :

dst

S P

@ S P

S P

¬

+

1

The contents of the location addressed by the stack pointer are loaded into the destination. The

stack pointer is then incremented by one.

Flags:

No flags affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

8

50

51

R

IR

E x a m p l e s :

Given: Register 00H

5 5 H :

= 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH

=

P O P

00H

Register 00H

=

55H, SP

= 0BCH

®

@ 0 0 H

01H, register 01H

= 55H, SP = 0BCH

In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads

the contents of location 0BBH (55H) into destination register 00H and then increments the stack

pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.

6-35

SAM88RI INSTRUCTION SET

S3C9688/P9688

PUSH

— Push To Stack

P U S H

src

S P

O p e r a t i o n :

S P

– 1

¬

@ S P

src

¬

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)

into the location addressed by the decremented stack pointer. The operation then adds the new

value to the top of the stack.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

src

2

8

70

71

R

IR

E x a m p l e s :

Given: Register 40H

=

4FH, register 4FH

=

0AAH, SP

=

0C0H:

P U S H

40H

Register 40H

S P 0 B F H

=

4FH, stack register 0BFH = 4FH,

®

=

@ 4 0 H

Register 40H

0 B F H

=

4FH, register 4FH

0 B F H

= 0AAH, stack register

=

0 A A H , S P

=

In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value

4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the

contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP

points to location 0BFH.

6-36

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

RCF

— Reset Carry Flag

R C F

O p e r a t i o n :

C

0

¬

The carry flag is cleared to logic zero, regardless of its previous value.

C : Cleared to "0".

Flags:

No other flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

4

C F

E x a m p l e :

Given: C = "1" or "0":

The instruction RCF clears the carry flag (C) to logic zero.

6-37

SAM88RI INSTRUCTION SET

S3C9688/P9688

RET

— Return

RET

O p e r a t i o n :

P C

S P

@ S P

S P

¬

+

2

The RET instruction is normally used to return to the previously executing procedure at the end of a

procedure entered by a CALL instruction. The contents of the location addre ssed by the stack

pointer are popped into the program counter. The next statement that is executed is the one that is

addressed by the new program counter value.

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

8

A F

E x a m p l e :

Given: S P

R E T

=

0 B C H , ( S P )

P C

=

1 0 1 A H , a n d P C

=

1 2 3 4 :

=

1 0 1 A H , S P = 0 B E H

®

The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of

the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's

low byte and the instruction at location 101AH is executed. The stack pointer now points to memory

location 0BEH.

6-38

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

RL

— Rotate Left

R L

d s t

C

O p e r a t i o n :

dst (7)

1) dst (n),

¬

dst (0)

dst (n

¬

+

n = 0– 6

¬

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is

moved to the bit zero (LSB) position and also replaces the carry flag.

7

0

C

Flags:

C :

Z:

Set if the bit rotated from the most significant bit position (bit 7) was "1".

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result bit 7 is set; cleared otherwise.

Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

90

91

R

IR

E x a m p l e s :

Given: Register 00H

=

0AAH, register 01H

Register 00H

=

02H and register 02H

55H, C "1"

02H, register 02H

=

17H:

RL

00H

=

®

@ 0 1 H

Register 01H

=

2EH, C = "0"

®

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement

"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and

setting the carry and overflow flags.

6-39

SAM88RI INSTRUCTION SET

S3C9688/P9688

RLC

— Rotate Left Through Carry

R L C

O p e r a t i o n :

d s t

dst (0)

C

¬

C

dst (7)

1)

¬

dst (n

+

dst (n), n = 0– 6

¬

The contents of the destination operand with the carry flag are rotated left one bit position. The initial

value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

7

0

C

Flags:

C :

Z:

Set if the bit rotated from the most significant bit position (bit 7) was "1".

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result bit 7 is set; cleared otherwise.

Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwis e.

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

10

11

R

IR

E x a m p l e s :

Given: Register 00H

=

0AAH, register 01H

Register 00H

=

02H, and register 02H

54H, C "1"

02H, register 02H = 2EH, C = "0"

=

17H, C

=

"0":

RLC

00H

=

®

@ 0 1 H

Register 01H

®

In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC

00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the

initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The

MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

6-40

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

RR _{— Rotate Right}

R R

d s t

C

O p e r a t i o n :

dst (0)

¬

dst (7)

dst (n)

dst (0)

dst (n

¬

+

1), n = 0– 6

The contents of the destination operand are rotated right one bit position. The initial value of bit zero

(LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

7

0

C

Flags:

C :

Z:

Set if the bit rotated from the least significant bit position (bit zero) was "1".

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result bit 7 is set; cleared otherwise.

Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

E 0

E 1

R

IR

E x a m p l e s :

Given: Register 00H

=

31H, register 01H

=

02H, and register 02H

Register 00H = 98H, C "1"

Register 01H 02H, register 02H

=

17H:

R R

00H

=

®

@ 0 1 H

=

8BH, C = "1"

In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR

00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7,

leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the

C flag to "1" and the sign flag and overflow flag are also set to "1".

6-41

SAM88RI INSTRUCTION SET

S3C9688/P9688

RRC _{— Rotate Right Through Carry}

R R C

d s t

O p e r a t i o n :

dst (7)

C

¬

C

dst (0)

dst (n

¬

dst (n)

+ 1), n = 0– 6

¬

The contents of the destination operand and the carry flag are rotated right one bit position. The

initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7

(MSB).

7

0

C

Flags:

C :

Z:

Set if the bit rotated from the least significant bit position (bit zero) was "1".

Set if the result is "0" cleared otherwise.

S :

V :

Set if the result bit 7 is set; cleared otherwise.

Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

C0

C1

R

IR

E x a m p l e s :

Given: Register 00H

=

55H, register 01H

=

02H, register 02H

=

17H, and C = "0":

R R C

00H

Register 00H

Register 01H

=

2AH, C

= "1"

®

@ 0 1 H

02H, register 02H

= 0BH, C = "1"

In the first example, if general register 00H contains the value 55H (01010101B), the statement

"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces

the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH

(00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".

6-42

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

SBC _{— Subtract With Carry}

S B C

dst,src

O p e r a t i o n :

dst

dst – src – c

¬

The source operand, along with the current value of the carry flag, is subtracted from the destination

operand and the result is stored in the destination. The contents of the source are unaffected.

Subtraction is performed by adding the two's -complement of the source operand to the destination

operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the

subtraction of the low-order operands to be subtracted from the subtraction of high-order operands.

Flags:

C :

Z:

Set if a borrow occurred (src > dst); cleared otherwise.

Set if the result is "0"; cleared otherwise.

S :

V :

Set if the result is negative; cleared otherwise.

Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the

sign of the result is the same as the sign of the source; cleared otherwise.

D :

H :

Always set to "1".

Cleared if there is a carry from the most significant bit of the low-order four bits of the

result; set otherwise, indicating a "borrow".

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

32

33

r

lr

src

d s t

3

6

34

35

R

IR

d s t

src

6

36

R

IM

E x a m p l e s :

Given: R1

=

10H, R2

=

03H, C = "1", register 01H = 20H, register 02H = 03H, and register

0 3 H

= 0 A H :

S B C

R1, R2

R1

=

0CH, R2

05H, R2

=

03H

03H, register 03H

®

R 1 , @ R 2

01H,02H

0 1 H , @ 0 2 H

0 1 H , # 8 A H

=

0AH

®

Register 01H

=

1CH, register 02H

15H,register 02H

95H; C, S, and V

= 03H

=

03H, register 03H

"1"

= 0AH

=

In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the

statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the

destination (10H) and then stores the result (0CH) in register R1.

6-43

SAM88RI INSTRUCTION SET

S3C9688/P9688

SCF

— Set Carry Flag

S C F

O p e r a t i o n :

C

1

¬

The carry flag (C) is set to logic one, regardless of its previous value.

Flags:

C :

Set to "1".

No other flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

opc

1

4

D F

E x a m p l e :

The statement

S C F

sets the carry flag to logic one.

6-44

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

SRA _{— Shift Right Arithmetic}

S R A

d s t

O p e r a t i o n :

dst (7)

dst (0)

dst (n

¬

C

¬

dst (n)

+ 1), n = 0– 6

¬

An arithmetic shift -right of one bit position is performed on the destination operand. Bit zero (the

LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit

position 6.

7

6

0

C

Flags:

C :

Z:

Set if the bit shifted from the LSB position (bit zero) was "1".

Set if the result is "0"; cleared otherwise.

Set if the result is negative; cleared otherwise.

Always cleared to "0".

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

opc

d s t

2

4

D0

D1

R

IR

E x a m p l e s :

Given: Register 00H

=

9AH, register 02H

=

03H, register 03H

=

0BCH, and C

=

"1":

S R A

00H

Register 00H

Register 02H

=

0CD, C

= "0"

®

@ 0 2 H

03H, register 03H

= 0DEH, C = "0"

In the first example, if general register 00H contains the value 9AH (10011010B), the statement

"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag

and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value

0CDH (11001101B) in destination register 00H.

6-45

SAM88RI INSTRUCTION SET

S3C9688/P9688

STOP

— Stop Operation

S T O P

O p e r a t i o n :

The STOP instruction stops both the CPU clock and system clock and causes the microcontroller

to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers,

and I/O port control and data registers are retained. Stop mode can be released by an external reset

operation or External interrupt input. For the reset operation, the

until the required oscillation stabilization interval has elapsed.

pin must be held to Low level

RESET

Flags:

No flags are affected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

1

4

7F

–

E x a m p l e :

The statement

S T O P

halts all microcontroller operations.

6-46

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

SUB _{— Subtract}

S U B

dst,src

O p e r a t i o n :

dst

dst – src

¬

The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. Subtraction is performed by adding the two's

complement of the source operand to the destination operand.

Flags:

C :

Z:

Set if a "borrow" occurred; cleared otherwise.

Set if the result is "0"; cleared otherwise.

Set if the re sult is negative; cleared otherwise.

S :

V :

Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the

sign of the result is of the same as the sign of the source operand; cleared otherwise.

D :

H :

Always set to "1".

Cleared if there is a carry from the most significant bit of the low-order four bits of the

result; set otherwise indicating a "borrow".

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

22

23

r

lr

src

d s t

3

6

24

25

R

IR

d s t

src

6

26

R

IM

E x a m p l e s :

Given: R1

=

12H, R2

=

03H, register 01H

=

21H, register 02H

=

03H, register 03H

=

0AH:

S U B

R1, R2

R 1

R1

=

0 F H , R 2

08H, R2

=

0 3 H

03H

®

R 1 , @ R 2

01H,02H

0 1 H , @ 0 2 H

01H,#90H

01H,#65H

®

Register 01H

=

1EH, register 02H

17H, register 02H

91H; C, S, and V

=

03H

"1"

=

0BCH; C and S

= "1", V = "0"

In the first example, if working register R1 contains the value 12H and if register R2 contains the

value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value

(12H) and stores the result (0FH) in destination register R1.

6-47

SAM88RI INSTRUCTION SET

S3C9688/P9688

TCM

— Test Complement Under Mask

T C M

dst,src

(NOT dst) AND src

O p e r a t i o n :

This instruction tests selected bits in the destination operand for a logic one value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand (mask).

The TCM statement complements the destination operand, which is then ANDed with the source

mask. The zero (Z) flag can then be checked to determine the result. The destination and source

operands are unaffected.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result bit 7 is set; cleared otherwise.

Always cleared to "0".

Unaffected.

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

62

63

r

lr

src

d s t

src

3

6

64

65

R

IR

d s t

3

6

66

R

IM

E x a m p l e s :

Given: R0

=

0C7H, R1

= 23H:

=

02H, R2

=

12H, register 00H

=

2BH, register 01H

=

02H, and

register 02H

TCM

R0, R1

R0

=

0C7H, R1

=

02H, Z

= "1"

®

R 0 , @ R 1

00H,01H

0 0 H , @ 0 1 H

=

02H, register 02H

=

23H, Z

=

"0"

®

Register 00H

=

2BH, register 01H

=

02H, Z

02H,

= "1"

Register 00H

register 02H

= 2BH, register 01H

=

23H, Z

=

"1"

"0"

TCM

00H,#34

Register 00H

=

2BH, Z =

®

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the

value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a

"1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can

be tested to determine the result of the TCM operation.

6-48

S3C9688/P9688

SAM88RCRI INSTRUCTION SET

TM

— Test Under Mask

T M

dst,src

O p e r a t i o n :

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be

tested are specified by setting a "1" bit in the corresponding position of the source operand (mask),

which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine

the result. The destination and source operands are unaffected.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result bit 7 is set; cleared otherwise.

Always reset to "0".

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

72

73

r

lr

src

d s t

src

3

6

74

75

R

IR

d s t

3

6

76

R

IM

E x a m p l e s :

Given: R0

=

0C7H, R1

= 23H:

=

02H, R2

=

18H, register 00H

=

2BH, register 01H

=

02H, and

register 02H

TM

R0, R1

R0

=

0C7H, R1

=

02H, Z

= "0"

®

R 0 , @ R 1

00H,01H

0 0 H , @ 0 1 H

=

02H, register 02H

=

23H, Z

02H, Z

2BH, register 01H = 02H,

=

"0"

®

Register 00H

=

2BH, register 01H

=

= "0"

Register 00H

register 02H

=

23H, Z

=

"0"

TM

00H,#54H

Register 00H

=

2BH, Z =

"1"

®

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the

value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0"

value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and

can be tested to determine the result of the TM operation.

6-49

SAM88RI INSTRUCTION SET

S3C9688/P9688

XOR _{— Logical Exclusive OR}

X O R

dst,src

O p e r a t i o n :

dst

dst XOR src

¬

The source operand is logically exclusive -ORed with the destination operand and the result is stored

in the destination. The exclusive -OR operation results in a "1" bit being stored whenever the

corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C :

Z:

Unaffected.

Set if the result is "0"; cleared otherwise.

Set if the result bit 7 is set; cleared otherwise.

Always reset to "0".

S :

V :

D :

H :

Unaffected.

F o r m a t :

B y t e s

C y c l e s

O p c o d e

( H e x )

A d d r M o d e

dst

src

opc

dst | src

2

4

6

B 2

B 3

r

lr

src

d s t

src

3

6

B 4

B 5

R

IR

d s t

3

6

B 6

R

IM

E x a m p l e s :

Given: R0

=

0C7H, R1

= 23H:

=

02H, R2

=

18H, register 00H

=

2BH, register 01H

=

02H, and

register 02H

XOR

R0, R1

R0

=

0C5H, R1

0E4H, R1

=

02H

02H, register 02H

®

R 0 , @ R 1

00H,01H

0 0 H , @ 0 1 H

00H,#54H

=

23H

®

Register 00H

=

29H, register 01H

08H, register 01H

7FH

=

02H

02H, register 02H

=

23H

In the first example, if working register R0 contains the value 0C7H and if register R1 contains the

value 02H, the statement "XOR R0,R1" logically exclusive -ORs the R1 value with the R0 value and

stores the result (0C5H) in the destination register R0.

6-50

S3C9688/P9688

CLOCK CIRCUIT

7

CLOCK CIRCUIT

OVERVIEWAE

The crystal or ceramic oscillation source provides a maximum 6 MHz clock for the S3C9688/P9688. The X and X

IN

OUT

pins are connected with the oscillation source to the on-chip clock circuit.

X

IN

S3C9688/P9688

6 MHz

X

OUT

F i g u r e 7 -1. Main Oscillator Circuit (Crystal/Ceramic Oscillator)

M A I N O S C I L L A T O R L O G IC

To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator

circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the CPU

to efficiently process logic operations.

C L O C K S T A T U S D U R I N G P O W E R -D O W N M O D E S

The two power-down modes, Stop mode and Id le mode, affect clock oscillation as follows:

—

In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and

current system register values are retained. Stop mode is released, and the oscillator started, by a reset

operation or by an external interrupt with RC-delay noise filter (for S3C9688/P9688, INT0 – INT2).

—

In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The

current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is

retained. Idle mode is released by a reset or by an interrupt (external or internally -generated).

7-1

CLOCK CIRCUIT

S3C9688/P9688

S Y S T E M C L O C K C O N T R O L R E G I S T E R ( C L K C O N )

The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the

following functions:

—

Oscillator IRQ wake-up function enable/disable (CLKCON.7)

Oscillator frequency divide-by value: non-divided, 2, 8 or 16 (CLKCON.4 and CLKCON.3)

The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release (This

is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.

After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the

f

/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock

OSC

speed to f

, f

/2 or f /8.

OSC OSC

s

System Clock Control Register (CLKCON)

D4H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Oscillator IRQ wake-up enable bit:

0 = Enable IRQ for main-system

oscillator wake-up function

Not used for S3C9688/P9688

Divide-by selection bits for

CPU clock frequency:

00 = f OSC/16

1 = Disable IRQ for main-system

oscillator wake-up function

01 = f OSC/8

10 = f OSC/2

11 = f OSC (non-divided)

Not used for S3C9688/P9688

F i g u r e 7 -2. System Clock Control Register (CLKCON)

7-2

S3C9688/P9688

CLOCK CIRCUIT

Stop

CLKCON.3, .4

Instruction

Oscillator

Stop

1/2

1/8

M

U

X

Main

OSC

CPU Clock

P3.3/CLO

Oscillator

Wake-up

1/16

P3CON

Noise

Filter

CLKCON.7

INT Pin

F i g u r e 7 -3. System Clock Circuit Diagram

7-3

CLOCK CIRCUIT

S3C9688/P9688

N O T E S

7-4

S3C9688/P9688

RESET AND POWER-D O W N

8

AND POWER-D O W N

RESET

S Y S T E M R E S E T

O V E R V I E W

During a power-on reset, the voltage at V

is High level and the

pin is forced to Low level. The

signal is

RESET

DD

input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the

S3C9688/P9688 into a known operating status.

The RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance

in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation stabilization

16

time for a reset is approximately 10ms (@ 2

f

, f

= 6 MHz).

/

OSC OSC

When a reset occurs during normal operation (with both V

and

at Hig h level), the signal at the

pin is

RESET

DD

forced Low and the reset operation starts. All system and peripheral control registers are then set to their default

hardware reset values (see Table 8-1).

The following sequence of events occurs during a reset operation:

—

All interrupts are disabled.

The watchdog function (basic timer) is enabled.

Ports 0-4 are set to schmitt trigger input mode and all pull-up resistors are disabled.

Peripheral control and data registers are disabled and reset to their initial values.

The program counter is loaded with the ROM reset address, 0100H.

When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location

0100H (and 0101H) is fetched and executed.

N O T E

To program the duration of the oscillation stabilization interval, you must make the appropriate settings to

the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the

basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you

can disable it by writing '1010B' to the upper nibble of BTCON.

8-1

RESET AND POWER-D O W N

S3C9688/P9688

P O W E R -D O W N M O D E S

S T O P M O D E

Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all

peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than

300 A. All system functions are halted when the clock "freezes", but data stored in the internal register fi le is

m

retained. Stop mode can be released in both ways: by a

signal or by an external interrupt.

RESET

U s i n g R E S E T t o R e l e a s e S t o p M o d e

Stop mode is released when the

signal is released and returns to High level. All system and peripheral control

RESET

registers are then reset to their default values and the contents of all data registers are retained. A reset operation

automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to ‘ 00B’ . A fter the

oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by fetching the 16-bit

address stored in ROM locations 0100H and 0101H.

Us i n g a n E x t e rn a l I n t e rru p t t o Re l e a s e S t o p M o d e

Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related

external interrupts cannot be used). External interrupts INT0 – INT2 in the S3C9688/P9688 interrupt structure meet

this criteria.

Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control

registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4 register

values remain unchanged, and the currently selected clock value is used. If you use an external interrupt for Stop

mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make

the appropriate control and clock settings

entering Stop mode.

before

The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine,

the instruction immediately following the one that initiated Stop mode is executed.

I D L E M O D E

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select

peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt logic

and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.

There are two ways to release Idle mode:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of

all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and

CLKCON.4 are cleared to ‘ 00B’ . If interrupts are masked, a reset is the only way to release Idle mode.

2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle

mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value

is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction immediately

following the one that initiated Idle mode is executed.

N O T E

Only external interrupts that are not clock-related can be used to release Stop mode. To release Idle mode,

however, any type of interrupt (that is, internal or external) can be used.

8-

2

S3C9688/P9688

RESET AND POWER-D O W N

H A R D W A R E R E S E T V A L U E S

Tables 8-1 through 8-3 list the values for CPU and system registers, peripheral control registers and peripheral data

registers following a reset operation in normal operating mode. The following notation is used in these tables to

represent specific reset values:

A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

¾

An 'x' means that the bit value is undefined following a reset.

¾

A dash ('-') means that the bit is either not used or not mapped.

¾

T a b l e 8 -1. Register Values after a Reset

R e g i s t e r N a m e

M n e m o n i c

Address

D e c H e x

Bit Values after RESET

7

x

0

1

0

6

x

0

1

0

5

x

0

1

0

4

x

3

x

2

x

1

x

0

1

0

x

0

1

0

General purpose registers

Working registers

–

000– 191 00H– B F H

192– 207 C0H– C F H

R0– R15

T0CNT

T0DATA

T0CON

U S X C O N

x

Timer 0 counter

208

209

210

211

D0H

D1H

D2H

D3H

0

1

0

1

0

1

0

Timer 0 data register

Timer 0 control register

USB selection and transceiver

crossover point control register

Clock control register

System flags register

C L K C O N

F L A G S

212

213

214

D4H

D5H

D6H

0

–

0

–

0

–

0

–

0

D+/PS2, D -/PS2 data register

(only PS2 mode)

P S 2 D A T A

PS2 control and interrupt

pending register

P S 2 C O N I N T

214

D7H

0

Port 0 interrupt control register

Stack pointer

P0INT

S P

216

217

218

D8H

D9H

D A H

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

Port 0 interrupt pending register

P 0 P N D

Location DBH is not mapped.

Basic timer control register

Basic timer counter

B T C O N

B T C N T

220

221

D C H

D D H

0

Location DEH is not mapped.

System mode register

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

S Y M

P 0

223

224

225

226

227

228

D F H

E 0 H

E 1 H

E 2 H

E 3 H

E 4 H

–

0

–

0

–

0

–

0

–

0

P 1

P 2

P 3

P 4

8-

3

RESET AND POWER-D O W N

S3C9688/P9688

T a b l e 8 -1. Register Values after a Reset (conti n u e d )

B a n k 0 R e g i s t e r N a m e

M n e m o n i c

Address

D e c

B i t V a l u e s a f t e r a R e s e t

H e x

E 5 H

E 6 H

E 7 H

E 8 H

E 9 H

E A H

E B H

E C H

E D H

E E H

E F H

F 0 H

F 1 H

F 2 H

F 3 H

F 4 H

F 5 H

F 6 H

F 7 H

F 8 H

F 9 H

7

0

x

6

0

x

5

0

x

4

0

x

3

0

x

2

0

x

1

0

x

0

x

Port 3 control register

P 3 C O N

P 0 C O N H

P 0 C O N L

P 1 C O N H

P 1 C O N L

P 2 C O N H

P 2 C O N L

P2INT

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

Port 0 control register (high byte)

Port 0 control register (low byte)

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 2 control register (h igh byte)

Port 2 control register (low byte)

Port 2 interrupt enable register

Port 2 interrupt pending register

Port 4 control register

P 2 P N D

P 4 C O N

Port 4 interrupt enable/pending register

USB function address register

Control endpoint status register

Interrupt endpoint status register

Control endpoint byte count register

Control endpoint FIFO register

Interrupt endpoint FIFO register

USB interrupt pending register

USB interrupt enable register

USB power management register

P4INTPND

F A D D R

E P 0 C S R

E P 1 C S R

E P 0 B C N T

E P 0 F I F O

E P 1 F I F O

U S B P N D

U S B I N T

P W R M G R

E P 2 C S R

x

0

1

0

1

0

1

0

Interrupt endpoint 2 control status

register

Interrupt endpoint 2 FIFO register

Endpoint mode register

Endpoint 1 byte count

E P 2 F I F O

E P M O D E

E P 1 B C N T

E P 2 B C N T

U S B C O N

250

251

252

253

254

F A H

F B H

F C H

F D H

F E H

x

0

x

0

x

0

x

0

x

0

1

x

0

x

0

1

x

0

1

Endpoint 2 byte count

USB control register

Location FFH is not mapped

8-

4

S3C9688/P9688

I/O PORTS

9

I/O PORTS

OVERVIEW

The S3C9688/P9688 USB Mode has five I/O ports (0 – 4) with a total of 32 pins.

PS2 Mode has two I/O ports (D+/PS2, D -/PS2) with a total of 34 pins.

You can acces s these ports directly by writing or reading port data register addresses.

For keyboard applications, ports 0, 1 and 2 are usually configured as keyboard matrix input/output. Port 3 can be

configured as LED drive. Port 4 is used for host communication or for controlling a mouse or other external device.

T a b l e 9 -1. S3C9688/P9688 Port Configuration Overview

Port

Function Description

P r o g r a m m a b i l i t y

0

Bit-programmable I/O port for schmitt trigger input or open-drain output.

Port0 can be individually configured as external interrupt inputs. Pull-up

resistors are assignable by software.

Bit

1

2

Bit-programmable I/O port for schmitt trigger input or open-drain output.

Pull-up resistors are assignable by software.

Bit

Bit-programmable I/O port for schmitt trigger input or open-drain output.

Port2 can be individually configured as external interrupt inputs. Pull-up

resistors are assignable by software.

3

4

Bit-programmable I/O port for schmitt trigger input, open-drain or push-pull

output. P3.3 can be used to system clock output (CLO) pin.

Bit

Bit-programmable I/O port for schmitt trigger input or open-drain output or

p u s h-pull output. Port4 can be individually configured as external interrupt

inputs. In output mode, pull-up resistors are assignable by software. But in

input mode, pull-up resistors are fixed.

D + / P S 2

D -/ P S 2

Bit-programmable I/O port for schmitt trigger input or open-drain output or

p u s h-pull output. This port individually configured as external interrupt

inputs. In output mode, pull-up resistors are assignable by software. But in

input mode, pull-up resistors are fixed.

Bit

( P S 2 m o d e

Only)

9-1

I/O PORTS

S3C9688/P9688

P O R T D A T A R E G I S T E R S

Table 9-2 gives you an overview of the port data register names, locations and addressing characteristics. Data

registers for ports 0– 4 have the structure shown in Figure 9-1.

T a b l e 9 -2 . P o r t D a t a R e g i s t e r S u m m a r y

Register Na m e

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

M n e m o n i c

D e c i m a l

224

H e x

E 0 H

E 1 H

E 2 H

E 3 H

E 4 H

R/W

P 0

P 1

P 2

P 3

P 4

225

226

227

228

I/O Port n Data Register (n = 0-4)

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pn.7

NOTE:

Because only the four lower-ni ble pins of port 3

Because only the four lower-nibble pins of port 3

and port 4 are mapped, data register bits P3.4-P3.7

and P4.4-P4.7 are not used.

F i g u r e 9 -1 . P o r t D a t a R e g i s t e r F o r m a t

9-2

S3C9688/P9688

I/O PORTS

P O R T 0 A N D P O R T 1

Ports 0 bit-programmable, general-purpose, I/O ports. You can select schmitt trigger input mode, N -CH open drain

output mode.

You can access ports 0 and 1 directly by writing or reading the corresponding port data registers — P0 (E0H) and P1

(E1H). A reset clears the port control registers P0CONH, P0CONL, P1CONH and P1CONL to '00H', configuring all

port 0 and port 1 pins as schmitt trigger inputs.

In typical keyboard controller applications, the sixteen port 0 and port 1 pins can be used to check pressed key from

keyboard matrix by generating keystroke output signals.

Port 0 Control Registers

P0CONH, E6H, R/W, P0CONL, E7H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0CONH

P0CONL

P0.7/INT2

P0.3/INT2

P0.6/INT2

P0.2/INT2

P0.5/INT2

P0.1/INT2

P0.4/INT2

P0.0/INT2

7,5,3,1 6,4,2,0

Port Mode Selection

0

1

Schmitt trigger input, rising edge external interrupt mode

Schmitt trigger input, falling edge external interrupt mode

with pull-up

1

0

1

N-CH open drain output mode

N-CH open drain output mode with pull-up

F i g u r e 9 -2. Port 0 Control Registers (P0CONH, P 0 C O N L )

9-3

I/O PORTS

S3C9688/P9688

Port 1 Control Registers

P1CONH, E8H, R/W, P1CONL, E9H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1CONH

P1CONL

P1.7

P1.3

P1.6

P1.2

P1.5

P1.1

P1.4

P1.0

7,5,3,1 6,4,2,0

Port Mode Selection

Schmitt trigger input mode

0

1

0

1

0

1

Schmitt trigger input mode with pull-up

N-CH open-drain output mode

N-CH open-drain output mode with pull-up

F i g u r e 9 -3. Port 1 Control Registers (P1CONH, P1CONL)

9-4

S3C9688/P9688

P O R T 2

I/O PORTS

Port 2 is an 8-bit I/O port with individually configurable pins. It can be used for general I/O (Schmitt trigger input mode

or push-pull output mode). Or, you can use port 2 pins as external interrupt (INT0) inputs. In addition, you can

configure a pull-up resistor to individual pins using control register settings. All port 2 pin circuits have noise filters.

In typical keyboard controller applications, the port 2 pins are programmed to receive key input data from the

keyboard matrix.

You can address port 2 bits directly by writing or reading the port 2 data register, P2 (E2H). The port 2 high-byte and

low-byte control registers, P2CONH and P2CONL, are located at addresses EAH and EBH, respectively.

Two additional registers, are used for interrupt control: P2INT (ECH) and P2PND (EDH). By setting bits in the port 2

interrupt enable register P2INT, you can configure specific port 2 pins to generate interrupt requests when rising or

falling signal edges are detected. The application program polls the port 2 interrupt pending register, P2PND, to

detect interrupt requests. When an interrupt request is acknowledged, the corresponding pending bit must be cleared

by the interrupt service routine.

In case of keyboard applications, the port 2 pins can be used to read key value from key matrix.

Port 2 Control Registers

P2CONH, EAH, R/W, P2CONL, EBH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2CONH

P2CONL

P2.7/INT0

P2.3/INT0

P2.6/INT0

P2.2/INT0

P2.5/INT0

P2.1/INT0

P2.4/INT0

P2.0/INT0

7,5,3,1 6,4,2,0

Port Mode Selection

0

1

Schmitt trigger input, rising edge external interrupt

Schmitt trigger input, falling edge external interrupt

with pull-up

1

0

1

N-CH open-drain

N-CH open-drain with pull-up

F i g u r e 9 -4. Port 2 Control Registers (P2CONH, P2CONL)

9-5

I/O PORTS

S3C9688/P9688

Port 2 Interrupt Enable Register (P2INT)

ECH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/INT0

P2.1/INT0

P2.2/INT0

P2.3/INT0

P2.4/INT0

P2.5/INT0

P2.6/INT0

P2.7/INT0

Port 2 Interrupt Control Settings:

0 = Disable interrupt at P2.n pin

1 = Enable interrupt at P2.n pin

F i g u r e 9 -5. Port 2 Interrupt Enable Register (P2INT)

Port 2 Interrupt Pending Register (P2PND)

EDH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/INT0

P2.1/INT0

P2.2/INT0

P2.3/INT0

P2.4/INT0

P2.5/INT0

P2.6/INT0

P2.7/INT0

Port 2 Interrupt Request Pending Bits:

0 = Not interrupt is pending

1 = Interrupt request is pending

F i g u r e 9 -6. Port 2 Interrupt Pending Register (P2PND)

9-6

S3C9688/P9688

P O R T 3

I/O PORTS

Port 3 is a 4-bit, bit-configurable, general I/O port. It is designed for high-current functions such as LED drive.

A reset configures P3.0-P3.3 to schmitt trigger input mode. Using the P3CON register (E5H), you can alternatively

configure the port 3 pins as n-channel, open-drain outputs. P3.3 can be used to system clock output (CLO) port.

Port 3 Control Register (P3CON)

E5H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P3.0

P3.1

P3.2

P3.3/CLO

Bit 7 Bit 6

Port Mode Selection (P3.3)

0

1

Schmitt trigger input

System Clock Ouput (CLO) mode.

CLO comes from System clock circuit.

Push-pull output

1

0

1

N-CH open drain output

5,3,1 4,2,0

Port Mode Selection (P3.2-P3.0)

0

1

x

0

1

Schmitt trigger input,

Push-pull output

N-CH open drain output

F i g u r e 9 -7. Port 3 Control Register (P3CON)

9-7

I/O PORTS

P O R T 4

S3C9688/P9688

Port 4 is a 4-bit I/O port with individually configurable pins. It can be used for general I/O (Schmitt trigger, N -CH open

drain output mode, push-pull output mode). Or, you can use port 4 pins as external interrupt (INT1) inputs. In

addition, you can configure a pull-up resistor to individual pins using control register settings. All port 4 pins have

noise filters.

A reset configures P4.0-P4.3 to input mode. You address port 4 directly by writing or reading the port 4 data register,

P4 (E4H). The port 4 control register, P4CON, is located at E E H .

A additional registers used for interrupt control: P4INTPND (EFH). By setting bits in the port 4 interrupt enable and

pending register P4INTPND.7-P4INTPND.4, you can configure specific port 4 pins to generate interrupt requests

when falling signal edges are detected. The application program polls the interrupt pending register, P4INTPND.3-

P4INTPND.0, to detect interrupt requests. When an interrupt request is acknowledged, the corresponding pending bit

must be cleared by the interrupt service routine.

Port 4 Control Register (P4CON)

EEH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P4.0/INT1

P4.1/INT1

P4.2/INT1

P4.3/INT1

P4CON Pin Configuration Settings:

00

01

10

11

Schmitt trigger input, falling edge external interrupt with pull-up

N-CH open-drain output with pull-up register

N-CH open-drain output

Push-pull output

F i g u r e 9 -8. Port 4 Control Register (P4CON)

9-8

S3C9688/P9688

I/O PORTS

Port 4 Interrupt Enable and Pending Register (P4INTPND)

EFH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P4.0/INT1

P4.1/INT1

P4.2/INT1

P4.3/INT1

P4.0/INT1

P4.1/INT1

P4.2/INT1

P4.3/INT1

P4INTPND.7-.4: Port 4 interrupt control settings:

0 = Disable interrupt at P4.n pin

1 = Enable interrupt at P4.n pin

P4INTPND.3-.0: Port 4 interrupt pending bit:

0 = No interrupt request pending

1 = Interrupt request is pending

F i g u r e 9 -9. Port 4 Interrupt Enable and Pending Register (P4INTPND)

9-9

I/O PORTS

S3C9688/P9688

D+/PS2, D -/ P S 2

PS2 Control and Interrupt and Pending Register

D7H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

D-/PS2PND

D+/PS2PND

D-/PS2INT

D+/PS2INT

D-/PS2

D+/PS2

PS2CONINT.7-4 Pin Configration Settings: D+/PS2, D-/PS2

00 Schmitt trigger input, falling edge external interrupt

01 Schmitt trigger input, falling edge external interrupt with pull-up

10 N-CH open-drain output

11 N-CH open-drain output with pull-up register

PS2CONINT.3-2 : Interrupt Control Setting

0 = Disable interrupt

1 = Enable interrupt

PS2CONINT.1-0 : Interrupt Pending Bit

0 = No interrupt request pending

1 = Interrupt request pending

NOTE

:

Used only PS2MODE.

F i g u r e 9 -1 0 . P S 2 C o n t r o l a n d I n t e r r u p t a n d P e n d i n g R e g i s t e r ( P S 2 C O N I N T )

9-10

S3C9688/P9688

BASIC TIMER AND TIMER 0

10

BASIC TIMER and TIMER 0

M O D U L E O V E R V I E W

The S3C9688/P9688 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The

8-bit timer/counter is called timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

—

As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.

To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

The functional components of the basic timer block are:

—

Clock frequency divider (f

divided by 4096, 1024, or 128) with multiplexer

OSC

—

8-bit basic timer counter, BTCNT (DDH, read-only)

Basic tim er control register, BTCON (DCH, read/write)

T i m e r 0

Timer 0 has two operating modes, one of which you select by the appropriate T0CON setting:

—

Interval timer mode

Overflow mode

Timer 0 has the following functional components:

—

Clock frequency divider (f

divided by 4096, 256, or 8) with multiplexer

OSC

—

8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)

Timer 0 overflow interrupt (T0OVF) and match interrupt (T0INT) generation

Timer 0 control re gister, T0CON

10-1

BASIC TIMER AND TIMER 0

S3C9688/P9688

B A S I C T I M E R C O N T R O L R E G I S T E R ( B T C O N )

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter

and frequency dividers, and to enable or disable the watchdog timer function.

A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of

f

/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic tim er register

OSC

control bits BTCON.7-BTCON. 4.

The 8-bit basic timer counter, BTCNT, can be cleared at any time during normal operation by writing a "1" to

BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1"

to BTCON. 0.

Basic Timer Control Register (BTCON)

DCH, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Divider clear bit for basic:

0 = No effect

Watchdog timer enable bits:

1 = Clear both dividers

1010B

= Disable watchdog

function

Other value = Enable watchdog

function

Basic timer counter clear bit:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00 = f OSC/4096

01 = f OSC/1024

10 = f OSC/128

11 = Invalid selection

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

S3C9688/P9688

BASIC TIMER AND TIMER 0

B A S I C T I M E R F U N C T I O N D E S C R I P T I O N

W a t c h d o g T i m e r F unction

You can program the basic timer overflow signal to generate a reset by setting BTCON.7-BTCON.4 to any value other

than '1010B' (The '1010B' value disables the watchdog function). A reset clears BTCON to '00H', automatically

enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON

register setting) divided by 4096 as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must

prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be

cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will

not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the

basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear

instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop

mode has been released by an external interrupt.

In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts

increasing at the rate of f

/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When

OSC

BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock

signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when Stop mode is released:

1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and

oscillation starts.

2. If a power-on reset occurred, the basic timer counter will increase at the rate of f

/4096. If an external interrupt

OSC

is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.

4. When a BTCNT. 4 is set, normal CPU operation resumes.

Figures 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release

10-3

BASIC TIMER AND TIMER 0

S3C9688/P9688

Oscillation Stabilization

Normal Operating mode

0.5 V DD

V

DD

Reset ReleaseVoltage

RESET

~

trst RC

~

Internal

Reset

Release

0.5 V DD

Oscillator

(XOUT

)

Oscillator Stabilization Time

BTCNT

clock

10000B

BTCNT

value

00000B

tWAIT = (4096x16)/f OSC

Basic timer increment and

CPU operations are IDLE mode

NOTE:

During of the oscillator stabilization wait time, t

by a Power-on-reset is 4096x16/fosc.

WAIT, when it is released

~

trst RC (R is external resister and C is on chip capacitor)

~

Figure 10-2. Oscillation Stabilization Time on RESET

10-4

S3C9688/P9688

BASIC TIMER AND TIMER 0

Normal

Operating

Mode

STOP Mode

Oscillation Stabilization Time

Normal

Operating

Mode

V

DD

STOP

Instruction

Execution

STOP Mode

Release Signal

External

Interrupt

RESET

STOP

Release

Signal

Oscillator

(XOUT

)

BTCNT

clock

10000B

BTCNT

Value

00000B

t

WAIT

Basic Timer Increment

NOTE:

Duration of the oscillator stabilzation wait time, tWAIT, it is released by an

interrupt is determined by the setting in basic timer control register, BTCON.

BTCON.3

BTCON.2

t

WAIT

t

WAIT (When f OSC is 6 MHz)

0

1

0

(4096 x 16)/fosc

(1024 x 16)/fosc

(128 x 16)/fosc

Invalid setting

10.92 ms

1

0

1

2.7 ms

0.34 ms

Figure 10-3 . O s c i l l a t i o n S t a b i l i z a t i o n T i m e o n S T O P M o d e R e l e a s e

10-5

BASIC TIMER AND TIMER 0

S3C9688/P9688

T I M E R 0 C O N T R O L R E G IS T E R ( T 0 C O N )

T0CON is located at address D2H, and is read/write addressable.

A reset clears T0CON to '00H'. This sets timer 0 to normal interval match mode, selects an input clock frequency of

/4096, and disables the timer 0 overflow interrupt and match interrupt. You can clear the timer 0 counter at any

f

OSC

time during normal operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt can be enabled by writing a "1" to T0CON.2. When a timer 0 overflow interrupt occurs

and is serviced by the CPU, the pending condition must be cleared by software by writing a "0" to the timer 0

interrupt pending bit, T0CON.0.

To enable the timer 0 match interrupt, you must write T0CON.1 to "1". To detect an interrupt pending condition, the

application program polls T0CON.0. When a "1" is detected, a timer 0 match/ capture interrupt is pending. When the

interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0

interrupt pending bit, T0CON.0.

Timer 0 Control Register (T0CON)

D2H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

00 = f OSC/4096

Timer 0 interrupt pending bit:

0 = No interrupt pending

01 = f OSC/256

0 = Clear pending bit (when write)

1 = Interrupt is pending (When read)

No effect (When write)

10 = f

/8

OSC

11 = Invalid selection

Timer 0 match interrupt enable bit:

0 = Disable match interrupt

1 = Enable match interrupt

Timer 0 operating mode selection bits:

00 = Interval match mode

01 = Invalid selection

10 = Invalid selection

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

11 = Overflow mode

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Figure 10-4. Timer 0 Control Register (T0CON)

10-6

S3C9688/P9688

BASIC TIMER AND TIMER 0

T I M E R 0 F U N C T I O N D E S C R I P T I O N

I n t e r v a l M a t c h M o d e

In interval match mode, a match signal is generated when the counter value is identical to the value written to the T0

reference data register, T0DATA. The match signal generates a timer 0 match interrupt and then clears the counter.

If for example, you write the value '10H' to T0DATA, the counter will increment until it reaches '10H'. At this point, the

T0 match interrupt is generated, the counter value is reset and counting resumes.

O v e r f l o w M o d e

In overflow mode, a overflow signal is generated regardless of the value written to the T0 reference data register when

the counter value is overflowed. The overflow signal generates a timer 0 overflow interrupt and then T0 counter is

cleared.

T0OVF

Data Bus

T0PND

8

T0INT

CLK

Counter

R

Match

Comparator

T0DATA Buffer

Register

When 8-Bit counter is cleared,

this buffer is open

T0DATA

8

Data Bus

Figure 10-5 . S i m p l i f i e d T i m e r 0 F u n c t i o n D i a g r a m : I n t e r v a l T i m e r M o d e

10-7

BASIC TIMER AND TIMER 0

S3C9688/P9688

Write '1010xxxxB' to disable

Bits 7, 6, 5, 4

Data Bus

8

Bit 1

RESET or STOP

1/4096

8-Bit Basic Counter

OVF

RESET

(

BTCNT, Read-only)

1/1024

DIV

XIN

MUX

1/128

R

When BTCNT. 4 is set after releasing from

RESET or STOP mode, CPU clock start.

Bit 2

Bits 3, 2

Bits 7, 6

OVINT

Bit 0

Data Bus

8

Overflow

R

Bit 3

1/4096

8-Bit Counter

T0CLR

R

2-Bit

SCA

LER

(T0CNT, Read-only)

1/256

DIV

1/8

Match

Signal

Bit 1

8

T0INT

Match/

8-Bit Comparator

Overflow

Bits 5, 4

Bit 0

IRQ

8

T0DATA Buffer Register

When 8-bit counter is cleared,

this buffer is open.

T0DATA

8

Data Bus

Basic Timer Control Register

Timer 0 Control Register

Figure 10-6 . B a s i c T i m e r a n d T i m e r 0 B l o c k D i a g r a m

10-8

S3C9688/P9688

UNIVERSAL SERIAL BUS

11

UNIVERSAL SERIAL BUS

OVERVIEW

Universal Serial Bus (USB) is a communication architecture that supports data transfer between a host computer

and a wide range of PC peripherals. USB is actually a cable bus in which the peripherals share its bandwidth through

a host scheduled token based protocol.

The USB module in S3C9688/P9688 is designed to serve at a low speed transfer rate (1.5 Mbs) USB device as

described in the Universal Serial Bus Specification Revision 2.0. S3C9688/P9688 can be briefly describe as a

microcontroller with SAM 88RCRI core with an on-chip USB peripheral as can be seen in figure 11-1.

The S3C9688/P9688 comes equipped with Serial Interface Engine (SIE), which handles the communication protocol

of the USB. The S3C9688/P9688 supports the following control logic: packet decoding/generation, CRC

generation/checking, NRZI encoding/decoding, Sync detection, EOP (end of packet) detection and bit stuffing.

S3C9688/P9688 supports two types of data transfers; control and interrupt. Three endpoints are used in this device;

Endpoint 0, Endpoint 1, and Endpoint 2 . Please refer to the USB specification revision 2.0 for detail description of

U S B .

11-1

UNIVERSAL SERIAL BUS

S3C9688/P9688

D+/PS2

D-/PS2

Transceiver

Voltage

Regulator

SAM88RCRI

Core

SIE

(Serial Interface

Engine)

Endpoint 0 FIFO

Endpoint 1, 2

FIFO

Interface

Figure 11-1 . U S B Peripheral Interface

11-2

S3C9688/P9688

UNIVERSAL SERIAL BUS

Serial Bus Interface Engine (SIE)

The Serial Interface Engine interfaces to the USB serial data and handles, deserialization/serialization of data, NRZI

encoding/decoding, clock extraction, CRC generation and checking, bit stuffing and other specifications pertaining to

the USB protocol such as handling inter packet time out and PID decoding.

Control Logic

The USB control logic manages data movements between the CPU and the transceiver by manipulating the

transceiver and the endpoin t register. This includes both transmit and receive operations on the USB. The logic

contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use this to

determine the number of bytes to transfer. The same buffer is used for receive transactions to count the number of

bytes received and transfer that number to the receive endpoint's byte count register at the end of the transaction.

The control logic in S3C9688/P9688, when transmitting, manages parallel to serial conversion, packet generation,

CRC generation, NRZI encoding and bit stuffing.

When receiving, the control logic in S3C9688/P9688 handles Sync detection, packet decoding, EOP (end of packet)

detection, bit stuffing, NRZI decoding, CRC checking and serial to parallel conversion

Bus Protocol

All bus transactions involve the transmission of packets. S3C9688/P9688 supports three packet types; Token, Data

and Handshake. Each transaction starts when the host controller sends a Token Packet to the USB devi ce. The

Token packets are generated by the USB host and decoded by the USB device. A Token Packet includes the type

description, direction of the transaction, USB device address and the endpoint number.

Data and Handshake packets are both decoded and generated by the USB device. In any transaction, the data is

transferred from the host to a device or from a device to the host. The transaction source then sends a Data Packet

or indicates that it has no data to transfer. The destination then responds with a Handshake Packet indicating

whether the transfer was successful.

D a t a T r a n s f e r T y p e s

USB data transfer occurs between the host software and a specific endpoint on the USB device. An endpoint

supports a specific type of data transfer. The S3C9688/P9688 supports two data transfer endpoints: control and

interrupt.

Control transfer configures and assigns an address to the device when detected. Control transfer also supports

status transaction, returning status information from device to host.

Interrupt transfe r refers to a small, spontaneous data transfer from USB device to host.

Endpoints

Communication flows between the host software and the endpoints on the USB device. Each endpoint on a device

has an identifier number. In addition to the endpoint number, each endpoint supports a specific transfer type.

S3C9688/P9688 supports three endpoints: Endpoint 0 supports control transfer, and Endpoint 1 and Endpoint 2

supports interrupt transfer.

11-3

UNIVERSAL SERIAL BUS

S3C9688/P9688

S T R U C T U R E O F U S B A N D P S / 2 C O M B I N A T I O N A L P O R T

Pull-up Enable

USB Enable

[A]

[B]

DM

DP

Voltage Regulator

(3.3 V Generation)

USB Signal Transceiver

(With Pull-up)

USB Control

[C]

PS/2 Signal Transceiver

(With Pull-up)

PS/2 Control

(P2CONINT)

NOTE:

That block explain USB block can be enabled or disabled with pull-up by s/w.

Voltage regulator also disabled automatically when USB block was disabled.

And PS/2 block can be controlled by software with pull-up.

Figure 11-2 . B l o c k D i a g r a m o f U S B a n d P S / 2 T r a n s c e i v e r

11-4

S3C9688/P9688

UNIVERSAL SERIAL BUS

S T R U C T U R E O F V O L T A G E R E G U L A T O R

Enable

Reference

Current

Voltage

3.3 V

Amplifier

Generator

A

B

NOTE:

This block can give a explanation how it can be controlled automatically.

If the 3.3 voltage regulator is enabled by software, it operates to cover fluctuation of

the line load, sometimes the line is unstable and the driving ability dropped.

As it operates in the normal stage without any peak, power will be supplied with

8 mA, and when the operating. It was designed to cover by 50 mA, the peak current

consumption. It means any kind of load problem will be compensated with the above

design.

Figure 11-3 . B l o c k D i a g r a m o f V o l t a g e R e g u l a t o r

11-5

UNIVERSAL SERIAL BUS

S3C9688/P9688

Pull-up Control

R, 1.5 K

W 5 %

+

C

A

B

DM

D-

DM

DP

V3.3IN

TX/RX

Control

Sinals

Slope

CTRL

D+

Control

DP

Enable

TX/RX

D

NOTE:

We didn't used the by-pass capacitor on the 3.3 V out, since the 3.3 V regulator and clamp

circuit will give a solution through the feedback.

USB block was designed to cover the line load, the typically designed value is 300 pF (max: 800 pF).

The clamp block operating after it detect the voltage variation

(actually the current fluctuation will be feedback into voltage variation, di/dt to dt/dt variation.

Bias controls the slope.

Control signal means NRZI, EOP, XCON, IN/OUT.

Enable is for the Tx, Rx.

Internal pull-up resistor will be 1.5 k

W +10 %

Figure 11-4 . B l o c k D i a g r a m o f U S B S i g n a l T r a n s c e i v e r

V

DD

VDD

DM_DRVP

DP_DRVP

Pull-up Enable

DP_DRVN

DM

DP

DM_DRVN

PS/2 Data

PS/2 Clock

NOTE:

It explain the PS2 block.

The pull-up resistor value will be 4.3 k

20 %

W +

This block can be controlled with pull-up resistor and it was designed with totally

different from usb.

Figure 11-5 . B l o c k D i a g r a m o f G P I O S i g n a l T r a n s m i t t e r

11-6

S3C9688/P9688

UNIVERSAL SERIAL BUS

U S B F U N C T I O N A D D R E S S R E G I S T E R ( F A D D R )

This register holds the USB address assigned by the host computer. FADDR is located at address F0H and is

read/write addressable.

Bit7

This register bit is used as test mode or special purpose mode, so user should set zero value,

Bit6– 0 FADDR:

MCU updates this register once it decodes a SET_ADDRESS command. MCU must write this

register before it clears OUT_PKT_RDY (bit0) and sets DATA_END (bit3) in the EP0CSR register. The

function controller use this register's value to decode USB Token packet address. At reset, if the device

is not yet configured the value is reset to 0.

USB Function Address Register (FADDR)

F0H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

This register bit sets zero value

7-bit programming device address. This register

maintains the USB address assigned by the host.

The function controller uses this register's value to

decode USB token packet address. At reset when

the device is not yet configured the value is reset to 0.

Figure 11-6. USB Function Address Register (FADDR)

11-7

UNIVERSAL SERIAL BUS

S3C9688/P9688

C O N T R O L E N D P O I N T S T A T U S R E G I S T E R ( E P 0 C S R)

EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is

located at F1H and is read/write addressable.

Bit7

Bit6

Bit5

C L E A R _ S E T U P _ E N D : MCU writes "1" to this bit to clear SETUP_END bit (bit4). This bit is

automatically cleared after clearing SETUP_END bit by SIE. So read value will be always "0".

C L E A R _ O U T _ P K T _ R D Y : MCU writes "1" to this bit to clear OUT_PKT_RDY bit (bit0). This bit is

automatically cleare d after clearing OUT_PKT_RDY bit by USB block. So read value will be always "0".

S E N D _ S T A L L : MCU writes "1" to this bit to send STALL packet to Host, it must clear OUT_PKT_RDY

(bit 0) at the same time. If MCU receive invalid command then should write #60h to this register. The SIE

issues a STALL handshake to the current control transfer(Means next transaction). This bit will be cleared

after sending STALL handshake.

Bit4

Bit3

S E T U P _ E N D : SIE sets this bit, when a control transfer ends without setting D ATA_END bit (bit3). MCU

clears this bit, by writing a "1" to CLEAR_SETUP_END bit (bit7). When SIE sets this bit, an interrupt is

generated to MCU. When such condition occurs, SIE flushes the FIFO. MCU can not access to FIFO

until this bit cleared. This flag is a read only bit so MCU can not write to this bit directly.

D A T A _ E N D : MCU sets this bit:

— After loading the last packet of data into the FIFO, and at the same time IN_PKT_RDY bit should be

set.

— While it clears OUT_PKT_RDY bit after unloading the last packet of data.

— For a zero length data phase, this bit should be set when it clears OUT_PKT_RDY bit.

Bit2

S E N T _ S T A L L : SIE sets this bit after send stall handshake to host. There are two cases which issue stall

packet to host. If MCU set SEND_STALL bit, then SIE will send stall to the next transaction and set this

bit. The other case is send stall by SIE automatically since protocol violation. An interrupt is generated

when this bit gets set. This bit is a read/write bit so MCU s hould clears this bit to end the STALL

condition.

Bit1

Bit0

I N _ P K T _ R D Y : MCU sets this bit, after loading data into Endpoint 0 FIFO. SIE clears this bit, once the

packet has been successfully sent to the host. An interrupt is generated when SIE clears this bit so that

MCU can load the next packet. For a zero length data phase, MCU sets IN_PKT_RDY bit without load

data to FIFO.

O U T _ P K T _ R D Y : SIE sets this bit, if the device receive valid data from host. An interrupt is generated,

when SIE sets this bit. MCU should download data and clears this bit by writing "1" to

CLEAR_OUT_PKT_RDY bit at the end of execution.

N O T E

When SETUP_END bit is set, OUT_PKT_RDY bit may also be set. This happens when the current transfer

has terminated by new setup transaction. In such case, MCU should first clear SETUP_END bit, and then

start servicing the

new control transfer.

11-8

S3C9688/P9688

UNIVERSAL SERIAL BUS

Control Endpoint Status Register (EP0CSR)

F1H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

OUT_PKT_RDY

IN_PKT_RDY

SENT_STALL

DATA_END

CLEAR_

SETUP_END

CLEAR_

OUT_PKT_RDY

SEND_STALL

SETUP_END

Figure 11-7. Control Endpoint Status Register (EP0CSR)

11-9

UNIVERSAL SERIAL BUS

S3C9688/P9688

I N T R R U P T E N D P O I N T S S T A T U S R E G I S T E R ( E P 1 C S R , E P 2 C S R )— I N M O D E

E P 1CSR register controls Endpoint 1, and also holds status bits for Endpoint 1. EP1CSR is located at F2H and is

read/write addressable. EP2CSR register controls Endpoint2, and the contents is perfectly same to EP1CSR.

EP2CSR is located at F9H and is read/write addressable.

EP1CSR and EP2CSR have two modes. These are IN and OUT mode which are decided by ENDPOINT_MODE

register. The below is IN mode configuration.

Bit7

C L R _ D A T A _ T O G G L E : MCU write "1" to this bit for initializing data toggle sequence. Data toggle

sequence can be monitored through WRT_CNT register.

Bit6

Bit5

Bit4

Bit3

MAXP[3].

MAXP[2].

MAXP[1].

MAXP[0].

— S3P9688 is a low speed USB controller so the maximum packet size is 8 bytes,

— This part is a limitation of MAXMUM packet size so the device can not send more data than this value.

Bit2

U C _ F I F O _ F L U S H : MCU sets this bit for initializing the FIFO. MCU can not clear IN_PKT_RDY so if

MCU want to clear IN_PKT_RDY after set then MCU should issue UC_FIFO_FLUSH for clearing

IN_PKT_RDY.

Bit1

Bit0

F O R C E _ S T A L L : MCU sets this bit for sending stall packet. This flag will not be cleared by SIE. So MCU

should clear this flag for stopping stall condition. Device will send stall until this flag is cleared.

I N _ P K T _ R D Y : MCU sets this bit after loading data to FIFO. SIE will clear this flag after sending data to

host. An interrupt is generated when this flag is cleared. If MCU issue UC_FIFO_FLUSH during this flag

set then this flag is cleared and generate interrupt to MCU. So MCU will get interrupt directly after setting

UC_FIFO_FLUSH flag if this flag was set.

11-10

S3C9688/P9688

UNIVERSAL SERIAL BUS

I N T R R U P T E N D P O I N T S S T A T U S R E G I S T E R ( E P 1 C S R , E P 2 C S R )— O U T M O D E

The below is OUT mode configuration.

Bit7

Bit6

R e s e r v e d .

C L E A R _ O U T _ P K T _ R D Y : MCU writes "1" to this bit to clear OUT_PKT_RDY bit (bit0). This bit is

automatically cleared after clearing OUT_PKT_RDY bit by SIE. So read value will be always "0".

Bit5

Bit4

Bit3

R e s e r v e d .

S E N T _ S T A L L : This flag is set by SIE after sending stall packet. And this flag is just for monitoring the

action of SIE so it does not mean any other things. This flag can be cleared by MCU.

Bit2

U C _ F I F O _ F L U S H : MCU sets this bit for initializing the FIFO. MCU can not clear IN_PKT_RDY so if

MCU want to clear IN_PKT_RDY after set then MCU should issue UC_FIFO_FLUSH for clearing

IN_PKT_RDY.

Bit1

Bit0

F O R C E _ S T A L L : MCU sets this bit for sending stall packet. This flag will not be cleared by SIE. So MCU

should clear this flag for stopping stall condition. Device will send stall until this flag is cleare d.

O U T _ P K T _ R D Y : SIE sets this bit, if the device receive valid data from host. An interrupt is generated,

when SIE sets this bit. MCU should download data and clears this bit by writing "1" to

CLEAR_OUT_PKT_RDY bit at the end of execution.

11-11

UNIVERSAL SERIAL BUS

S3C9688/P9688

E N D P O I N T 0 W R I T E C O U N T R E G I S T E R ( E P 0 B C N T )

EP0BCNT register contains data count value, some monitoring and flow control flag. EP0BCNT is located at F3H and

is read addressable.

Bit7

Bit6

D A T A _ T O G G L E : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.

T O K E N : This flag is for monitoring. If this value is set then it means the last received token packet is

SETUP token and if the value is "0" then the last received token packet is OUT or IN packet.

Bit5

Bit4

O V E R _ 8 :.If device receive over 8 bytes SETUP or OUT transaction then the device does not answer to

these transaction and set this flag as a error indicator.

ENABLE:. MCU set this bit for disabling endpoint 0. Device does not answer to any traffic if addressed to

endpoint 0 until this bit is cleared.

Bit3

Bit2

Bit1

Bit0

E P 0 W R T _ C N T [ 3 ].

E P 0 W R T _ C N T [ 2 ].

E P 0 W R T _ C N T [ 1 ].

EP0WRT_CNT[0]: SIE store data count after receive valid data from host. The maximum value is 8. And

if MCU downloading the FIFO then this value also decreased according to remain data count.

11-12

S3C9688/P9688

UNIVERSAL SERIAL BUS

E N D P O I N T 1 W R I T E C O U N T R E G I S T E R ( E P 1 B C N T )

EP1BCNT register contains data count value, some monitoring and flow control flag. EP1BCNT is located at FCH

and is read/write addressable.

Bit7

Bit6

Bit5

D A T A _ T O G G L E : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.

R e s e r v e d .

O V E R _ 8 :.If device receive over 8 bytes SETUP or OUT transaction then the device does not answer to

these transaction and set this flag as a error indicator.

Bit4

ENABLE:. MCU set this bit for disabling endpoint 1. Device does not answer to any traffic if addressed to

endpoint 1 until this bit is cleared.

Bit3

Bit2

Bit1

Bit0

E P 1 W R T _ C N T [ 3 ].

E P 1 W R T _ C N T [ 2 ].

E P 1 W R T _ C N T [ 1 ].

EP1WRT_CNT[0]: SIE store data count after receive valid data from host. The maximum value is 8. And

if MCU downloading the FIFO then this value also decreased according to remain data count.

11-13

UNIVERSAL SERIAL BUS

S3C9688/P9688

E N D P O I N T 2 W R I T E C O U N T R E G I S T E R ( E P 2 B C N T )

EP2BCNT register contains data count value, some monitoring and flow control flag. EP2BCNT is located at FDH

and is read/write addressable.

Bit7

Bit6

Bit5

D A T A _ T O G G L E : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.

R e s e r v e d .

O V E R _ 8 :.If device receive over 8 bytes SETUP or OUT trans action then the device does not answer to

these transaction and set this flag as a error indicator.

Bit4

ENABLE:. MCU set this bit for disabling endpoint 2. Device does not answer to any traffic if addressed to

endpoint 1 until this bit is cleared.

Bit3

Bit2

Bit1

Bit0

E P 1 W R T _ C N T [ 3 ].

E P 1 W R T _ C N T [ 2 ].

E P 1 W R T _ C N T [ 1 ].

EP1WRT_CNT[0]: SIE store data count after receive valid data from host. The maximum value is 8.

And if MCU downloading the FIFO then this value also decreased according to remain data count.

11-14

S3C9688/P9688

UNIVERSAL SERIAL BUS

E N D P O I N T M O D E R E G I S T E R ( E P M O D E )

EPMODE register contains the field which defines USB reset signal length and the field which defines the direction of

endpoints. EPMODE is located at FBH and is read/write addressable.

Bit7

Bit6

RESET_LENGTH[1].

RESET_LENGTH[0]: This field defines the length of USB reset signal. The reset value is "00". MCU can

control USB reset length through this field. The definition is as below.

—

"00" : 20.954 us.

"01" : 10.476 us.

"10" : 5.236 us.

"11" : 2. 664 us.

Bit5

Bit4

Bit3

R e s e r v e d .

C H I P _ T E S T _ M O D E : If this value is "1" then Test mode and If this value is "0" then Normal mode. User

must not set this bit. The Reset value is "0"

Bit2

Bit1

O U T P U T _ E N A B L E _ M O D E : If this value is "1" then Normal mode and If this value is "0" then Enhanced

mode. The Reset value is "0".

ENDPOINT_MODE[1]: MCU can defines direction of interrupt transfer. If this value is "1" then endpoint 2

act as a OUT interrupt endpoint and if this value is "0" then endpoint 2 act as a IN interrupt endpoint. The

reset value is "0".

Bit0

ENDPOINT_MODE[0]: MCU can defines direction of interrupt transfer. If this value is "1" then endpoint 1

act as a OUT interrupt endpoint and if this value is "0" then endpoint 1 act as a IN interrupt endpoint. The

reset value is "0".

11-15

UNIVERSAL SERIAL BUS

S3C9688/P9688

U S B P O W E R M A N A G E M E N T R E G I S T E R ( P W R M G R )

PWRMGR register interacts with the Host's power management system to execute system power events such as

SUSPEND or RESUME. And this register also contains monitoring field for detail control of MCU. This register is

located at address F8H and is read/write addressable.

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

R e s e r v e d .

V P I N _ M O N I T O R : If this value is "1" then DATA - is one and If this value is "0" then DATA+ is zero.

V M I N _ M O N I T O R : If this value is "1" then DATA - is one and If this value is "0" then DATA - is one.

C L E A R _ S U S P _ C N T : MCU write "1" value to this bit for clearing suspend counter which count 3 ms. And

during this value stay "1" the suspend counter does not proceed. That means the USB controller can not

go into suspend state during this value stays "1".

Bit1

Bit0

R e s e r v e d .

S U S P E N D _ S T A T E : Suspend state is set when the MCU sets suspend interrupt. This bit is cleared

automatically when:

—

MCU writes "0" to SEND_RESUME bit to end the RESUME signaling (after SEND_RESUME is set

for 10ms).

MCU receives RESUME signaling from the Host while in SUSPEND mode.

11-16

S3C9688/P9688

UNIVERSAL SERIAL BUS

USB Power Mangement Register (PWRMGR)

F8H, R/W

.7

.6

.5

.4

.3

.2

.1

.0

MSB

LSB

Reserved

SUSPEND_STATE

Reserved

CLEAR_SUSP_CNT

VPIN

VMIN

Figure 11-8 . U S B P o w e r M a n a g e m e n t R e g i s t e r ( P W R M G R )

11-17

UNIVERSAL SERIAL BUS

S3C9688/P9688

C O N T R O L E N D P O I N T F I F O R E G I S T E R ( E P 0 F I F O )

This register is bi-directional, 8 byte depth FIFO used to transfer Control Endpoint data. EP0FIFO is located at

address F4H and is read/write addressable.

Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control transfer,

that is, after MCU unload the setup token bytes, and clears OUT_PKT_RDY, the direction of FIFO is changed

automatically from MCU to the Host.

I N T E R R U P T E N D P O I N T 1 F I F O R E G I S T E R ( E P 1 F I F O )

EP1FIFO is an bi-direction 8-byte depth FIFO used to transfer data from the MCU to the Host or from the Host to the

MCU. MCU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB receives valid

data through this register , it sets OUT_PKT_RDY, after MCU unload Data bytes, and clears OUT_PKT_RDY , This

register is located at address F5H.

I N T E R R U P T E N D P O I N T 2 F I F O R E G I S T E R ( E P 2 F I F O )

EP2FIFO is an bi-direction 8-byte depth FIFO used to transfer data from the MCU to the Host or from the Host to the

M C U . M CU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB receives valid

data through this register , it sets OUT_PKT_RDY, after MCU unload Data bytes, and clears OUT_PKT_RDY , This

register is located at address FAH.

U S B I N T E R R U P T P E N D I N G R E G I S T E R ( U S B P N D )

USBPND register has the interrupt bits for endpoints and power management.

This register is cleared once read by MCU.

While any one of the bits is set, an interrupt is generated. USBPND is located at address F6H.

Bit7– 6 Not used

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

U S B _ R S T _ P N D : This bit is set, when usb reset signal is received.

E N D P T 2 _ P N D : This bit is set, when suspend signaling is received.

R E S U M E _ P N D : While in suspend mode, if resume signaling is received this bit gets set.

S U S P E N D _ P N D : This bit is set, when suspend signaling is received.

E N D P T 1 _ P N D : This bit is set, when Endpoint 1 needs to be serviced.

E N D P T 0 _ P N D : This bit is set, when Endpoint 0 needs to be serviced. It is set under any one of the

following conditions:

— OUT_PKT_RDY is set.

— IN_PKT_RDY gets cleared.

— SENT_STALL gets set.

— DATA_END gets cleared.

— S E T U P _ E N D g e t s s e t .

11-18

S3C9688/P9688

UNIVERSAL SERIAL BUS

USB Interrupt Pending Register (USBPND)

F6H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

USB_RST_PND

ENDPT2_PND

RESUM E_PND

SUSPEND_PND

ENDPT0_PND

ENDPT1_PND

Figure 11-9. USB Interrupt Pending Register (USBPND)

11-19

UNIVERSAL SERIAL BUS

S3C9688/P9688

U S B I N T E R R U P T E N A B L E R E G I S T E R ( U S B I N T )

USBINT is located at address F7H and is read/write addressable. This register serves as an interrupt mask register.

If the corresponding bit = 1 then the respective interrupt is enabled.

By default, all interrupts except suspend interrupt is enabled. Interrupt enables bits for suspend and resume is

combined into a single bit (bit 2).

Bit7– 5 Not used

Bit4

Bit3

Bit2

Bit1

Bit0

E N A B L E _ U S B _ R S T _ I N T :

1: Enable USB RESET INTERRUPT (default)

0: Disable USB RESET INTERRUPT

ENABLE_ENDPT2_INT:

1: Enable ENDPOINT 2 INTERRUPT (default)

0: Disable ENDPOINT 2 INTERRUPT

E N A B L E _ S U S P E N D _ R E S U M E _ I N T :

1 : E n a b l e S U S P E N D a n d R E S U M E I N T E R R U P T

0: Disable SUSPEND and RESUME INTERRUPT (default)

ENABLE_ENDPT1_INT:

1: Enable ENDPOINT 1 INTERRUPT (default)

0: Disable ENDPOINT 1 INTERR U P T

ENABLE_ENDPT0_INT:

1: Enable ENDPOINT 0 INTERRUPT (default)

0: Disable ENDPOINT 0 INTERRUPT

USB Interrupt Enable Register (USBINT)

F7H, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used

ENABLE_ENDPT0_INT

ENABLE_ENDPT1_INT

ENABLE_SUSPEND_RESUME_INT

ENABLE_ENDPT2_INT

ENABLE_USB_RST_INT

Figure 11-10. USB Interrupt Enable Register (USBINT)

11-20

S3C9688/P9688

UNIVERSAL SERIAL BUS

U S B C O N T R O L R E G I S T E R ( U S B C O N )

USBCON is for the control of USB data line and the control of reset .This register is located at address FEH and is

read/write addressable.

Bit5

Bit4

DP /DM Control: When this bit is set , DP/DM lines can be controlled by MCU as bellows

D P : On the condition of bit5 set, if this bit is 1, DP line is to be high and the other case this bit is 0

DP line is low .

Bit3

Bit2

D M : On the condition of bit5 set, if this bit is 1, DM line is to be high and the other case this bit is 0

DM line is low .

U S B _ R E S E T _ E N : When this bit is set, it is USB is made reset , which trigger MCU reset

automatically

Bit1

M C U _ R E S E T : When this bit is set, MCU makes USB reset

U S B _ R S T N : USB reset status bit

0: USB is not reset

1: USB is reset

USB Control Register (USBCON)

FEH (Page 0), R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Reserved

USB_RSTN

MCU_RESET

USB_RESET_EN

DP/

DM_CONTROL

DM

DP

Figure 11-11. USB Control Register (USBCON)

11-21

UNIVERSAL SERIAL BUS

S3C9688/P9688

U S B S I G N A L A N D S I G N A L C R O S S O V E R P O I N T C O N T R O L R E G I S T E R ( U S X CO N )

USXCON is located at address D3H and is read/write addressable. You can select protocol mode between USB PS2

and adjust USB signal crossover point.

Bit7

Bit6

Bit5

U S B / P S 2 m o d e s e l e c t b i t :

0: PS2 mode (Default)

1: USB mode (This bit is set when the D+/PS2, D -/PS2 port set the D+, D -)

U S B P u l l -Up Control bit:

0 : P ull-Up Disable

1: Pull-Up Enable

USB signal crossover point control bit:

E d g e D e l a y

Bit 5, (2)

Bit 4, (1)

Bit 3, (0)

D e l a y V a l u e

D e l a y U n i t

Control

Rising

Edge

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

0

1

2

4

(about)

2. 5 msec

Falling

Edge

1

NOTE:

The value is recommended by chip Vendor.

11-22

S3C9688/P9688

LVR (LOW VOLTAGE RESET)

12

LVR (LOW VOLTAGE RESET)

OVERVIEW

The S3C9688/P9688 have a LVR (Low Voltage Reset) for power on reset and voltage reset.

Reference

Start Up

Voltage

Generator

Comparator

Glitch Filter

RESET

Voltage

Divider

Figure 12-1. LVR Architecture

—

Low Voltage Reset generated

signal.

RESET

Start Up Circuit: Start up refe rence voltage generator circuit when device is powered.

Reference Voltage Generator: Supply Voltage independent reference voltage generator.

Voltage Divider: Divide supply voltage by "N"

Comparator: Compare reference voltage and divided voltage.

Glitch Filter: Remove glitch and noise signal.

12-1

LVR (LOW VOLTAGE RES ET)

S3C9688/P9688

Vc (Compare Voltage)

Divide Voltage

NOTES:

1. LVR Operation Voltage Range: 2.3 V-6.0 V

2. LVR Detection Voltage Range: 3.4 V

3. LVR Current Consum ption:

Less then 10 uA (normally 5 uA)

4. LVR Powered Reset Release Time:

more then 500 usec (LVR only, typical)

Reference Voltage

+ 0.4 V

5. LVR Simulation Conditions (Hspice Simulation)

o

Temp: 0 - 80

C

Process Veriation: Worst to best conditions

Test Voltage: 0.0 V - 7.0 V

V

DD (Supply Voltage)

Normal Operation

Reset Operation

by LVR

Powered Slew Rate: 5 V/1 usec- 5 V/100 msec

Figure 12-2. LVR Characteristics

12-2

S3C9688/P9688

LVR (LOW VOLTAGE RESET)

L V R A N D P O W E R O N

O P E R A T I O N S

RESET

T2

Normal Operating mode

Oscillation Stabilization Time

V

DD

LVD

RESET

T1

LVD RESET Release Time

Release

Internal

RESET

Release

Oscillator

OUT

(X

)

T3

Oscillator Stabilization Time

BTCNT

clock

10000B

BTCNT

value

00000B

t

WAIT = (4096x16)/f OSC

Basic timer increment and

CPU operations are IDLE mode

NOTES:

1. T1 = 500 usc (at normal)

2. T2 = T1 + (4096 x 16)/f

OSC

Figure 12-3 . L V R a n d P o w e r O n

O p e r a t i o n

RESET

12-3

LVR (LOW VOLTAGE RES ET)

S3C9688/P9688

N O T E S

12-4

S3C9688/P9688

ELECTRICAL DATA

13

ELECTRICAL DATA

OVERVIEW

In this section, the following S3C9688/P9688 electrical characteristics are presented in tables and graphs:

—

Absolute maximum ratings

D.C. electrical characteristics

Input/Output capacitance

A.C. electrical characteristics

Input timing for external interrupt (Ports 0, 2, and 4) D+/PS2, D -/ P S 2 : P S 2 M o d e O n l y

Input timing for RESET

Oscillator characteristics

Oscillation stabilization time

Clock timing measurement points at X

IN

—

Data retention supply voltage in Stop mode

Stop mode release timing when initiated by a reset

Stop mode release timing when initiated by an external interrupt

Characteristic curves

13-1

ELECTRICAL DATA

S3C9688/P9688

T a b l e 1 3 -1 . A b s o l u t e M a x i m u m R a t i n g s

(T

= 2 5 C )

°

A

P a r a m e t e r

S y m b o l

Conditions

Rating

Unit

Supply Voltage

Input Voltage

V

–

– 0.3 to + 6.5

V

DD

IN

V

All input ports

– 0.3 to

V

+ 0. 3

V

DD

Output Voltage

Output Current High

V

All output ports

+ 0. 3

O

I

One I/O pin active

– 18

m A

OH

All I/O pins active

One I/O pin active

– 60

+ 3 0

Output Current Low

I

m A

OL

Total pin current for ports 3

+ 100

Total pin current for ports 0, 1, 2, 4

–

Operating Temperature

Storage Temperature

T

– 40 to + 85

– 65 to + 150

C

°

A

T

–

C

°

STG

13-2

S3C9688/P9688

ELECTRICAL DATA

T a b l e 1 3 -2. D.C. Electrical Characteristics

(T

=

– 40 C to + 85 C, V

=

4 . 0 V t o 5 . 2 5 V )

°

A

DD

P a r a m e t e r

S y m b o l

Conditions

= 6 M H z

Min

T y p

M a x

Unit

Operating Voltage

V

f

4.0

5.0

5.25

V

DD

OSC

(instruction clock = 1 MHz)

Input High Voltage

V

All input pins except V

0.8 V

–

V

IH1

IH2

DD

V

X

V

– 0.5

V

IH2

IN

DD

V

0.5V

RESET

IH3

DD

Input Low Voltage

V

All input pins except V

–

0.2 V

IL1

IL2

DD

V

X

0.4

IL2

IN

V

0.5V

–

RESET

IL2

DD

Output High Voltage

Output Low Voltage

Output Low Current

V

I

=

– 200 A; All output ports

V

– 1.0

–

V

m

OH

DD

except ports 0, 1 and 2, D+, D –

= 1 m A

V

I

–

8

–

0.4

23

OL

All output port except D+, D –

= 3V

I

V

15

m A

OL

Port 3 only

= V

(3)

Input High

I

V

–

3

A

m

LIH1

IN

DD

Leakage Current

All inputs except I

LIH2

except D+, D –

(3)

I

V

X

= V

X

–

20

A

m

LIH2

IN

DD

RESET

IN, OUT,

(3)

Input Low

I

V

= 0 V

– 3

A

m

LIL1

IN

Leakage Current

All inputs except I

LIL2

e x c e p t D + , D –

(3)

I

V

X

= 0 V

X

–

– 20

A

m

LIL2

IN

RESET

IN, OUT,

13-3

ELECTRICAL DATA

S3C9688/P9688

T a b l e 1 3 -2. D.C. Electrical Characteristics (Continued)

4 . 0 V t o 5 . 2 5 V )

Conditions

(T

=

– 40 C to + 85 C, V

=

°

A

DD

P a r a m e t e r

S y m b o l

Min

T y p

M a x

Unit

(1)

Output High

I

V

= V

–

3

A

m

LOH

OUT

DD

Leakage Current

All I/O pins and output pins

except D+, D –

(1)

Output Low

I

V

= 0 V

–

– 3

100

A

m

LOL

OUT

Leakage Current

All I/O pins and output pins

except D+, D –

Pull-up Resistors

R

V

= 0 V

25

50

k

W

L1

IN

Ports 0, 1, 2, 4.2-3, Reset

= 0 V ; P 4 . 0 -1

R

V

2

–

5

–

IN

L2

(2)

Supply Current

I

Normal operation mode

6 M H z C P U c l o c k

5.5

12

m A

DD1

I

Idle mode; 6 MHz oscillator

S t o p m o d e

2.2

6

5

DD2

I

15

A

m

DD3

NOTES

:

1.

Except X and X .

IN OUT

2.

3.

Supply current does not include current drawn through internal pull-up resistors or external output current loads.

When USB Mode Only in 4.2 V to 5.25 V, D+ and D– satisfy the USB spec 1.1.

13-4

S3C9688/P9688

ELECTRICAL DATA

T a b l e 1 3 -3. Input/Output Capacitance

(T

=

– 40 C to + 85 C, V

= 0 V )

°

A

DD

P a r a m e t e r

S y m b o l

Conditions

Min

T y p

M a x

Unit

Input

C

f = 1 MHz; Unmeasured pins

–

10

pF

IN

Capacitance

are connected to V

SS

Output

C

OUT

Capacitance

I/O Capacitance

C

IO

T a b l e 1 3 -4. A.C. Electrical Characteristics

(T

=

– 40 C to + 85 C, V

=

4 . 0 V t o 5 . 2 5 V )

°

A

DD

P a r a m e t e r

S y m b o l

Conditions

P0, P2 and P 4

Min

T y p

M a x

Unit

Interrupt Input

t

, t

–

200

–

ns

INTH

INTL

High, Low Width

RESET Input Low

W i d t h

t

10

–

s

m

RESET

RSL

t

INTH

INTL

tRSL

0.8 V DD

0.2 V DD

Figure 13-1. Input timing for External Interrupt (Ports 0, 2, and 4)

t

RSL

RESET

0.5 V

DD

Figure 13-2. Input Timing for

RESET

13-5

ELECTRICAL DATA

S3C9688/P9688

T a b l e 1 3 -5. Oscillator Characteristics

(T

=

– 40 C + 8 5 C, V

= 4 . 0 V t o 5 . 2 5 V )

°

A

DD

Oscillator

Clock Circuit

Test Condition

Min

T y p

M a x

Unit

Main crystal Main

ceramic (f

Oscillation frequency

–

6.0

–

M H z

X

IN

)

OSC

X

OUT

External clock

Oscillation frequency

–

6.0

–

IN

X

OUT

X

T a b l e 1 3 -6. Oscillation Stabilization Time

4 . 0 V t o 5 . 2 5 V )

Test Condition

(T

=

– 40 C + 8 5 C, V

=

°

A

DD

Oscillator

Min

T y p

M a x

Unit

Main Crystal

Main Ceramic

f

= 6 . 0 M H z

–

10

m s

OSC

(Oscillation stabilization occurs when V

the minimum oscillator voltage range.)

is equal to

DD

16

Oscillator

t

stop m ode release time by a reset

–

2

/ f

–

WAIT

OSC

Stabilization Wait

T i m e

t

stop mode release time by an interrupt

(note)

WAIT

NOTE

:

The oscillator stabilization wait time, t

, is determined by the setting in the basic timer control register, BTCON.

WAIT

T a b l e 1 3 -7 . D a t a R e t e n t i o n S u p p l y V o l t a g e i n S t o p M o d e

(T

=

– 40 C to + 85 C )

° °

A

P a r a m e t e r

S y m b o l

Conditions

S t o p m o d e

Min

T y p

M a x

Unit

Data Retention

Supply Voltage

V

2.0

–

6

V

DDDR

Data Retention

Supply Current

I

Stop mode; V

= 2.0 V

–

300

A

m

DDDR

13-6

S3C9688/P9688

ELECTRICAL DATA

Internal Reset

Operation

IDLE Mode

(Basic Timer Active)

Stop Mode

Data Retention Mode

DD

V

Normal

Operating

Mode

V

DDDR

Execution of

Stop Instrction

RESET

0.5 V DD

t

WAIT

Figure 13-3 . S t o p M o d e R e l e a s e T i m i n g W h e n I n i t i a t e d b y a R e s e t

IDLE Mode

(Basic Timer Active)

Stop Mode

Data Retention Mode

V

DD

Normal

Operating

Mode

V

DDDR

Execution Of

Stop Instrction

External

Interrupt

0.8 V DD

WAIT

0.2 V DD

t

Figure 13-4 . S t o p M o d e R e l e a s e T i m i n g W h e n I n i t i a t e d b y a n E x t e r n a l I n t e r r u p t

13-7

ELECTRICAL DATA

S3C9688/P9688

T a b l e 1 3 -8. Low Speed USB Electrical Characteristics

= 2. 8 V to 3. 5 V, t y p 3 , 3 V )

(T

=

– 40 C to + 85 C, Voltage Regulator Output V

°

A

33out

P a r a m e t e r

S y m b o l

Conditions

Min

M a x

Unit

Transition Time:

Rise Time

Tr

Tf

CL = 50 pF

75

–

ns

CL = 350 pF

CL = 50 pF

300

–

Fall Time

75

–

CL = 350 pF

(Tr/Tf) CL = 50 pF

CL = 50 pF

300

120

2.0

3.5

Rise/Fall Time Matching

Trfm

Vcrs

80

1.3

2.8

%

V

Output Signal Crossover Voltage

Voltage Regulator Output Voltage

V

with V

to GND 0. 1

F

V

m

33OUT

capacitor

Test

2.8 V

90 %

Point

Measurement

Points

S/W

R2

10 %

D. U. T

R1

C2

Tr

Tf

R1 = 15 K

R2 = 1.5 K

W

DM: S/W ON

DP: S/W OFF

W

CL = 50 pF - 350 pF

Figure 13-5 . U S B D a t a S i g n a l R i s e a n d F a l l T i m e

3.3 V

DP

MAX: 2.0 V

Vcrs

MIN: 1.3 V

0 V

DM

Figure 13-6. USB Output Signal Crossover Point Voltage

13-8

S3C9688/P9688

ELECTRICAL DATA

T a b l e 1 3 -9. Low Speed USB Electrical Characteristics

(T

=

– 40 C to + 85 C )

°

A

P a r a m e t e r

S y m b o l

Conditions

Min

T y p

M a x

Unit

Low level detect voltage

V

–

3.00

3.40

3.80

V

LVD

13-9

ELECTRICAL DATA

S3C9688/P9688

N O T E S

13-10

S3C9688/P9688

MECHANICAL DATA

14

MECHANICAL DATA

OVERVIEW

The S3C9688/P9688 is available in a 42-pin SDIP package (Samsung: 42-SDIP -600) and a 44-pin QFP package

(44-Q F P -1010B). Package dimensions are shown in Figures 14-1 and 14-2.

#42

#22

0-15

42-SDIP-600

#1

#21

39.50 MAX

39.10 ± 0.2

0.50 ± 0.1

1.78

(1.77)

1.00 ± 0.1

Dimensions are in millimeters.

NOTE :

Figure 14-1. 42-P i n S D I P P a c k a g e M e c h a n i c a l D a t a ( 4 2 -SDIP -600 )

14-1

MECHANICAL DATA

S3C9688/P9688

13.20 + 0.3

10.00 + 0.2

0-8

+ 0.10

- 0.05

0.15

0.10 MAX

44-QFP-1010B

#44

+ 0.10

0.35 - 0.05

#1

0.05 MIN

0.80

(1.00)

2.05 + 0.10

2.30 MAX

NOTE : Dimensions are in millimeters.

Figure 14-2. 44-P i n Q F P P a c k a g e M e c h a n i c a l D a t a ( 4 4 -Q F P -1010B)

14-2

S3C9688/P9688

S3P9688 OTP

15

S3P9688 OTP

OVERVIEW

The S3P9688 single -chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9688

microcontroller. It has an on-c h i p O T P R O M i n s t e a d o f m a s k e d R O M . T h e E P R O M i s a c c essed by serial data

format.

The S3P9688 is fully compatible with the S3C9688, both in function and in pin configuration. Because of its simple

programming requirements, the S3P9688 is ideal for use as an evaluation chip for the S3C9688.

P3.2

P3.3/CLO

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

P3.1

P3.0

1

2

INT0/P2.0

D+/PS2

D-/PS2

3

INT0/P2.1

INT0/P2.2

4

3.3V OUT

NC

P0.0/INT2

5

INT0/P2.3

INT0/P2.4

INT0/P2.5

6

7

P0.1/INT2

P0.2/INT2

8

/INT0/P2.6

SDAT

9

SCLK /INT0/P2.7

P0.3/INT2

P0.4/INT2

10

11

12

13

14

15

16

17

18

19

20

21

S3P9688

(42-SDIP)

V

DD/V DD

P0.5/INT2

P0.6/INT2

V

SS/V SS

X

OUT/X OUT

X

IN/XIN

P0.7/INT2

P1.0

TEST /TEST

INT1/P4.0

P1.1

P1.2

P1.3

INT1/P4.1

RESET/ RESET

INT1/P4.2

P1.4

P1.5

P1.6

INT1/P4.3

P1.7

NOTE:

The TEST pin must be connected to V

SS (GND) in normal operation mode.

Th pins which used in writing OTP-ROM codes are assigned in bold.

Figure 15-1. S3P9688 Pin Assignments (42-S D I P P a c k a g e )

15-1

S3P9688 OTP

S3C9688/P9688

3.3V OUT

34

35

36

37

38

39

40

41

42

43

44

P1.0

P1.1

P1.2

22

21

20

19

18

17

16

15

14

13

12

D- /PS2

D+/PS2

CLO/P3.3

P1.3

P1.4

P1.5

P3.2

P3.1

P3.0

S3P9688

44-QFP

P1.6

P1.7

(Top View)

P2.0/INT0

P2.1/INT0

P2.2/INT0

P2.3/INT0

P4.3/INT1

P4.2/INT1

RESET/ RESET

SS

(GND) in the normal operation mode.

NOTE:

The TEST pin must connect to V

The bold is assigned to OTP pin name.

Figure 15-2. S3P9688 Pin Assignments (44-Q F P P a c k a g e )

15-2

S3C9688/P9688

S3P9688 OTP

T a b l e 1 5 -1. Descriptions of Pins Used to Read/Write the EPROM

D u r i n g P r o g r a m m i n g

M a i n C h i p

P i n N a m e

P2. 6

P i n N a m e

P i n N o .

I/O

Function

(3)

S D A T

9

I/O

Serial Data Pin (Output when reading, Input when

writing) Input and Push-pull Output Port can be

assigned

(4)

P2. 7

S C L K

T E S T

10

I/O

I

Serial Clock Pin (Input Only Pin)

(9)

T E S T

15

Chip Initialization and EPROM Cell Writing Power

Supply Pin (Indicates OTP Mode Entering) When

writing 12.5 V is applied and when reading.

(12)

18

I

0 V: OTP write and test mode

5 V: Operating mode

RESET

(5)

(6)

V

/ V

V

/ V

11 /12

–

Logic Power Supply Pin.

DD

SS

DD

SS

NOTE:

( ) means 44 QFP package.

T a b l e 1 5 -2 . C o m p a r i s o n o f S 3 P 9 6 8 8 a n d S 3 C 9 6 8 8 F e a t u r e s

S 3 P 9 6 8 8

Characteristic

S3C9688

8-K b y t e m a s k R O M

4.0 V to 5.25 V

Program Memory

8-K b y t e E P R O M

4.0 V to 5.25 V

Operating Voltage (V

)

DD

OTP Programming Mode

V

= 5 V , V

(RESET) = 12. 5 V

DD

PP

Pin Configuration

4 2 S D I P / 4 4 Q F P

EPROM Programmability

User Program 1 time

Programmed at the factory

O P E R A T I N G M O D E C H A R A CTERISTICS

When 12.5 V is supplied to the V

(

) pin of the S3P9688, the EPROM programming mode is entered. The

RESET

PP

operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table

15-3 below.

T a b l e 1 5 -3 . O p e r a t i n g M o d e S e l e c t i o n C r i t e r i a

V

V p p

R E G /

M E M

Address

(A15–A0)

R/W

M o d e

D D

(RESET)

5 V

0

1

0000H

0 E 3 F H

1

0

1

0

E P R O M r e a d

12.5 V

E P R O M p r o g r a m

EPROM verify

EPROM read protection

NOTE

:

"0" means Low level; "1" means High level.

15-3

S3P9688 OTP

S3C9688/P9688

START

Address = First Location

V

DD = 5V, V PP = 12.5V

x = 0

Program One 1ms Pulse

Increment X

YES

x = 10

NO

FAIL

NO

Verify Byte

Verify 1 Byte

Last Address

Increment Address

V

DD = V PP = 5 V

FAIL

Compare All Byte

PASS

Device Passed

Device Failed

Figure 15-3 . O T P P r o g r a m m i n g A l g o r i t h m

15-4

S3C9688/P9688

S3P9688 OTP

T a b l e 1 5 -4. D.C. Electrical Characteristics

(T

=

– 40 °C to + 85 C, V

=

4 . 0 V t o 5 . 2 5 V )

°

A

DD

P a r a m e t e r

S y m b o l

Conditions

Normal mode;

Min

T y p

M a x

Unit

Supply Current

I

–

5.5

12

m A

DD1

6 M H z C P U c l o c k

(note)

I

Idle mode;

2.2

6

5

DD2

6 M H z C P U c l o c k

I

S t o p m o d e

15

A

m

DD3

NOTE

:

Supply current does not include current drawn through internal pull-up resistors or external output current loads.

15-5

S3P9688 OTP

S3C9688/P9688

N O T E S

15-6

S3C9688/P9688

DEVELOPMENT TOOLS

16

DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development

support system is configured with a host system, debugging tools, and support software. For the host system, any

standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool

including hardware and software is provided: the sophisticated and powerful in -circuit emulator, SMDS2+, for S3C7,

S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also

offers support software that includes debugger, assembler, and a program for setting options.

S H I N E

Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It

has an advanced, multiple -windowed user interface that emphasizes ease of use. Each window can be sized, moved,

scrolled, highlighted, added, or removed completely.

S A M A A S S E M B L E R

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object

c ode in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data

and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary

definition (DEF) file with device specific information.

S A S M 8 6

The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source

file containing assembly language statements and translates into a corresponding source code, object code and

comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It

produces the relocatable object code only, so the user should link object file. Object files can be linked with other

object files and loaded into memory.

H E X 2 R O M

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value "FF" is filled into the unused ROM area upto the maximum ROM size of the target device

automatically.

16-1

DEVELOPMENT TOOLS

T A R G E T B O A R D S

S3C9688/P9688

Target boards are available for the test of all S3C9-series microcontrollers. All required target system cables and

adapters are included with the device-specific target board.

O T P s

One times programmable microcontrollers (OTPs) are under development for S3C9688/P9688 microcontroller.

IBM-PC AT or

Compatible

RS-232C

SMDS2+

Target

Application

System

PROM/OTP Writer Unit

RAM Break/Display Unit

Trace/Timer Unit

Probe

Adapter

TB9688

Target

Board

POD

SAM4 Base Unit

EVA

Chip

Power Supply Unit

Figure 16-1 . S M D S P r o d u c t C o n f i g u r a t i o n ( S M D S 2 + )

16-2

S3C9688/P9688

DEVELOPMENT TOOLS

T B 9 6 8 8 T A R G E T B O A R D

The TB9688 target board is used for the S3C9688/P9688 microcontrollers. It is supported by the SMDS2+

development systems. The TB9688 target board can also be used for S3C9688/P9688.

TB9688

To User_V CC

Off

On

RESET

Idle

+

Stop

+

25

J101

80

41

1

50

40

81

160 QFP

S3E9680

EVA Chip

CN1

1

120

160

121

1

U1

Y2

SEL1

SEL0

H

L

EXTTRIG1

EXTTRIG2

25

26

L

SMDS2

SMDS2+

Figure 16-2. TB9688 Target Board Configuration

16-3

DEVELOPMENT TOOLS

S3C9688/P9688

T a b l e 1 6 -1. Power Selection Settings for TB9688

O p e r a t i n g M o d e

'To User_Vcc' Settings

C o m m e n t s

T h e S M D S 2 / S M D S 2 + s u p p l i e s

V to the target board

To User_VCC

TB9688

CC

Target

V

CC

SS

Off

On

(evaluation chip) and the target

s y s t e m .

System

V

CC

SMDS2/SMDS2+

TB9688

T h e S M D S 2 / S M D S 2 + s u p p l i e s

To User_V CC

V

only to the target board

External

Target

CC

V

CC

Off

On

(evaluation chip). The target

system must have its own

power supply.

System

SS

V

CC

SMDS2+

NOTE

:

The following symbol in the "To User_V_CC" Setting column indicates the electrical short (off) configuration:

S M D S 2 + S e l e c t i o n ( S A M 8 )

In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for

SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.

T a b l e 1 6 -2 . T h e S M D S 2 + T o o l S e l e c t i o n S e t t i n g

" S W 1 " S e t t i n g

O p e r a t i n g M o d e

S M D S 2

S M D S 2 +

R/W*

Target

Board

SMDS2+

S M D S 2

S M D S 2 +

R/W*

Target

Board

R/W* is not

available

SMDS2+

16-4

S3C9688/P9688

DEVELOPMENT TOOLS

T a b l e 1 6 -3. The 'SEL0, SEL1' Selection Setting

C o m m e n t s

'SEL0, SEL1' Settings

H

L

H

L

This 'SEL0, SEL1' Pin is not Used.

( N o C o n n e c t e d )

SEL0

SEL1

T a b l e 1 6 -4 . U s i n g S i n g l e H e a d e r P i n s a s t h e I n p u t P a t h f o r E x t e r n a l T r i g g e r S o u r c e s

T a r g e t B o a r d P a r t C o m m e n t s

Connector from

external Trigger

sources of the

application System

EXTTRIG1

EXTTRIG2

CH1

CH2

You can connect an external trigger source to one of the two external

trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace

functions.

16-5

DEVELOPMENT TOOLS

S3C9688/P9688

J101

P3.1

P3.0

P3.2

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

2

P3.3/CLO

D+/PS2

D-/PS2

P2.0/INT0

3

P2.1/INT0

P2.2/INT0

4

5

3.3V OUT

N.C

P2.3/INT0

P2.4/INT0

6

7

P0.0/INT2

P0.1/INT2

P0.2/INT2

P2.5/INT0

8

P2.6/INT0

P2.7/INT0

9

10

11

12

13

14

15

16

17

18

19

20

21

P0.3/INT2

P0.4/INT2

P0.5/INT2

V

DD

V

SS

X

OUT

P0.6/INT2

P0.7/INT2

IN

X

TEST

P4.0/INT1

P1.0

P1.1

P1.2

P4.1/INT1

RESET

P1.3

P1.4

P1.5

P1.6

P4.2/INT1

P4.3/INT1

P1.7

Figure 16-3. 42 Pin Connector for TB9688

Target Board

J101

50

Target System

User System

1

J101

42

50

1

Part Name: (AP42SD-J)

Order Code: SM6524

Probe for User

System

21

25 26

22

25

26

Figure 16-4 . S 3 C 9 6 8 8 P r o b e A d a p t e r C a b l e f o r 4 2 -S D I P P a c k a g e

16-6


型号：	S3C9688
厂家：	SAMSUNG
描述：	8-bit single-chip CMOS microcontrollers 8位单芯片CMOS微控制器微控制器
文件：	总209页 (文件大小：600K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S3C9688 [SAMSUNG]

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