S3CB205 [SAMSUNG]
S3CB205/FB205;
SAMSUNG 
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Format:
ADC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:ꢀ
<op1> ← <op1> + <op2> + C
ADC adds the values of <op1> and <op2> and carry (C) and stores the result back into <op1>
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
.
Example:ꢀ
ꢀ
ADC
R0, 80h
R0, R1
// If eid = 0, R0 ← R0 + DM[0080h] + C
// If eid = 1, R0 ← R0 + DM[IDH:80h] + C
ADC
// R0 ← R0 + R1 + C
ADD
ADC
R0, R2
R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of “ADD R0, R2” is not zero, Z flag can be set to ‘1’ if the result
of “ADC R1,R3” is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit addition, take care of the change of Z flag.
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Format:
ADD <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:ꢀ
<op1> ← <op1> + <op2>
ADD adds the values of <op1> and <op2> and stores the result back into <op1>.
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
.
Example:ꢀ
Given: IDH:IDL0 = 80FFh, eid = 1
ADD
ADD
ADD
R0, 80h
R0, #12h
R1, R2
// R0 ← R0 + DM[8080h]
// R0 ← R0 + 12h
// R1 ← R1 + R2
ADD
ADD
ADD
ADD
R0, @ID0 + 2
R0, @[ID0 – 3]
R0, @[ID0 + 2]!
R0, @[ID0 – 2]!
// R0 ← R0 + DM[80FFh], IDH ← 81h, IDL0 ← 01h
// R0 ← R0 + DM[80FCh], IDH ← 80h, IDL0 ← FCh
// R0 ← R0 + DM[8101h], IDH ← 80h, IDL0 ← FFh
// R0 ← R0 + DM[80FDh], IDH ← 80h, IDL0 ← FFh
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
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Format:
AND <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:ꢀ
<op1> ← <op1> & <op2>
AND performs bit-wise AND on the values in <op1> and <op2> and stores the result in <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: set if the MSB of result is 1. Reset if not.
Example:ꢀ
Given: IDH:IDL0 = 01FFh, eid = 1
AND
AND
AND
R0, 7Ah
R1, #40h
R0, R1
// R0 ← R0 & DM[017Ah]
// R1 ← R1 & 40h
// R0 ← R0 & R1
AND
AND
AND
AND
R1, @ID0 + 3
R1, @[ID0 – 5]
R1, @[ID0 + 7]!
R1, @[ID0 – 2]!
// R1 ← R1 & DM[01FFh], IDH:IDL0 ← 0202h
// R1 ← R1 & DM[01FAh], IDH:IDL0 ← 01FAh
// R1 ← R1 & DM[0206h], IDH:IDL0 ← 01FFh
// R1 ← R1 & DM[01FDh], IDH:IDL0 ← 01FFh
ꢀ
In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data memory
DM[0051h-007Fh] are not mapped in S3CB205/FB205. In the last two instructions, the value of
IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing
mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
ꢑꢒꢁꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢊꢁꢋꢈꢂꢄꢌꢀꢁꢀꢌꢅꢆꢍꢄꢅꢎꢏꢀꢂꢐꢑꢀꢄꢅꢆꢇꢀꢒꢓꢔꢀ
Format:
AND SR0, #imm:8
Operation:ꢀ
SR0 ← SR0 & imm:8
AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the
result in SR0.
Flags:
–
Example:ꢀ
Given: SR0 = 11000010b
nIE
EQU
EQU
EQU
~02h
~40h
~80h
nIE0
nIE1
ꢀ
ꢀ
AND
AND
SR0, #nIE | nIE0 | nIE1
SR0, #11111101b
ꢀ
ꢀ
In the first example, the statement “AND SR0, #nIE|nIE0|nIE1” clear all of bits of the global interrupt,
interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to ‘1’ by instruction “OR SR0,
#imm:8”. Refer to instruction OR SR0 for more detailed explanation about enabling bit.
In the second example, the statement “AND SR0, #11111101b” is equal to instruction DI, which is
disabling interrupt globally.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢁꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢍꢊꢁꢎꢀꢁꢀꢕꢖꢓꢀꢌꢉꢗꢘꢀꢎꢏꢙꢏꢚꢆꢅꢛꢗꢀ
Format:
BANK #imm:2
SR0[4:3] ← imm:2
–
Operation:ꢀ
Flags:
ꢋꢏꢌꢐꢔꢀ ꢀ
For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3.ꢀ
Example:ꢀ
ꢀ
BANK
LD
#1
// Select register bank 1
R0, #11h
// Bank1’s R0 ← 11h
BANK
LD
#2
// Select register bank 2
R1, #22h
// Bank2’s R1 ← 22h
ꢑꢒꢁꢕꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢍꢀꢃꢆꢀꢁꢀꢌꢅꢆꢀꢈꢛꢜꢝꢙꢏꢜꢏꢗꢆꢀ
Format:
BITC adr:8.bs
bs: 3-digit bit specifier
R3 ← ((adr:8) ^ (2**bs))
Operation:ꢀ
if (TF == 0)
ꢀ
(adr:8) ← ((adr:8) ^ (2**bs)) if (TF == 1)
ꢀ
BITC complements the specified bit of a value read from memory and stores the result in R3 or
back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
ꢋꢏꢌꢐꢔꢀ ꢀ
Since the destination register R3 is fixed, it is not specified explicitly.ꢀ
Given: IDH = 01, DM[0180h] = FFh, eid = 1
Example:ꢀ
BMC
BITC
// TF ← 0
80h.0
80h.1
// R3 ← FEh, DM[0180h] = FFh
BMS
BITC
// TF ← 1
// DM[0180h] ← FDh
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢁꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢍꢀꢃꢄꢀꢁꢀꢌꢅꢆꢀꢓꢏꢎꢏꢆꢀ
Format:
BITR adr:8.bs
bs: 3-digit bit specifier
Operation:ꢀ
R3 ← ((adr:8) & ((11111111)ꢁ - (2**bs)))
if (TF == 0)
ꢀ
(adr:8) ← ((adr:8) & ((11111111)ꢁ - (2**bs))) if (TF == 1)
ꢀ
BITR resets the specified bit of a value read from memory and stores the result in R3 or back
into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
ꢋꢏꢌꢐꢔꢀ ꢀ
Since the destination register R3 is fixed, it is not specified explicitly.ꢀ
Given: IDH = 01, DM[0180h] = FFh, eid = 1
Example:ꢀ
BMC
BITR
// TF ← 0
80h.1
80h.2
// R3 ← FDh, DM[0180h] = FFh
BMS
BITR
// TF ← 1
// DM[0180h] ← FBh
ꢑꢒꢁꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢍꢀꢃꢂꢀꢁꢀꢌꢅꢆꢀꢒꢏꢆꢀ
Format:
BITS adr:8.bs
bs: 3-digit bit specifier.
Operation:ꢀ
R3 ← ((adr:8) | (2**bs))
if (TF == 0)
ꢀ
(adr:8) ← ((adr:8) | (2**bs)) if (TF == 1)
ꢀ
BITS sets the specified bit of a value read from memory and stores the result in R3 or back into
memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
ꢋꢏꢌꢐꢔꢀ ꢀ
Since the destination register R3 is fixed, it is not specified explicitly.ꢀ
Given: IDH = 01, DM[0180h] = F0h, eid = 1
Example:ꢀ
BMC
BITS
// TF ← 0
80h.1
80h.2
// R3 ← 0F2h, DM[0180h] = F0h
BMS
BITS
// TF ← 1
// DM[0180h] ← F4h
ꢀ
ꢀ
ꢀ
ꢑꢒꢁꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢍꢀꢃꢃ ꢁꢀꢌꢅꢆꢀꢞꢏꢎꢆꢀ
Format:
BITT adr:8.bs
bs: 3-digit bit specifier.
Operation:ꢀ
Z ← ~((adr:8) & (2**bs))
BITT tests the specified bit of a value read from memory.
Z: set if result is zero. Reset if not.
Flags:
Example:ꢀ
Given: DM[0080h] = F7h, eid = 0
BITT
JR
•ꢀ
80h.3
Z, %1
// Z flag is set to ‘1’
// Jump to label %1 because condition is true.
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
•ꢀ
%1ꢀ
BITS
NOP
•ꢀ
80h.3
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
ꢑꢒꢁꢗꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢍꢏꢆꢐꢍꢏꢂ ꢀꢞ!ꢀ"ꢅꢆꢀꢚꢙꢏꢉꢊ#ꢎꢏꢆ
Format:
BMS/BMC
Operation:
BMC/BMS clears (sets) the TF bit.
TF ← 0 if BMC
TF ← 1 if BMS
TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR, and
BITS.
Flags:
–ꢀ
ꢋꢏꢌꢐꢔꢉꢉ ꢉ
BMC/BMS are the only instructions that modify the content of the TF bit.ꢀ
Example:ꢀ
ꢀ
BMS
BITS
// TF ← 1
// TF ← 0
81h.1
BMC
BITR
LD
81h.2
R0, R3
ꢀ
ꢀ
ꢀ
ꢑꢒꢁꢘꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢆꢊꢑꢑꢀꢁꢀꢈꢛꢗꢃꢅꢆꢅꢛꢗꢉꢙꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀꢈꢉꢙꢙꢀ%ꢖꢎꢏ$ꢃꢛꢀ&ꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:
CALL cc:4, imm:20
CALL imm:12
ꢏꢙꢚꢛꢜꢝꢞ !ꢔꢉ
2(ꢂ0G33@ꢂꢎꢇꢅꢂꢇꢎꢎꢔꢊꢊꢂꢋꢚꢔꢂꢋꢇꢌ/ꢔꢋꢂꢇꢉꢉꢌꢔꢊꢊꢂꢇꢅꢉꢂꢋꢚꢔꢌꢔꢂꢄꢊꢂꢅꢏꢂꢎꢏꢅꢉꢄꢋꢄꢏꢅꢇꢈꢂꢎꢏꢉꢔꢂ#ꢎꢎ7;'ꢞꢂ0G33ꢂꢎꢏꢓꢓꢇꢅꢉꢂꢄꢊꢂꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢇꢊꢊꢔꢓꢖꢈꢔꢉꢂꢋꢏꢂ0G33@ꢂ#ꢗꢃAꢏꢌꢉꢂꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅ'ꢂꢄꢅꢂꢈꢄꢅ-ꢄꢅ/ꢂꢋꢄꢓꢔꢞꢂꢔꢈꢊꢔꢂꢋꢚꢔꢂ0G33ꢂꢄꢊꢂꢇꢊꢊꢔꢓꢖꢈꢔꢉꢂꢋꢏꢂ30G33ꢂ#ꢘꢃAꢏꢌꢉꢂꢂ
ꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅ'ꢐꢂ
ꢂ
Example:ꢀ
ꢀ
ꢀ
ꢀ
CALL
•ꢀ
C, Wait
// HS[sptr][15:0] ← current PC + 2, sptr ← sptr + 2
ꢀ
// 2-word instructionꢀ
ꢀ
ꢀ
ꢂꢂ
ꢀ
ꢀ
ꢂ
•ꢀ
•ꢀ
CALL
•ꢀ
0088h
// HS[sptr][15:0] ← current PC + 1, sptr ← sptr + 2
ꢀ
// 1-word instructionꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
Wait: NOP
NOP
// Address at 0088h
NOP
NOP
NOP
RET
ꢑꢒꢕꢅꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢆꢊꢑꢑꢂꢀꢁꢀꢈꢉꢙꢙꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀ
Format:
CALLS imm:12
Operation:ꢀ
HS[sptr][15:0] ← current PC + 1, sptr ← sptr + 2 if the program size is less than 64K word.
HS[sptr][19:0] ← current PC + 1, sptr ← sptr + 2 if the program size is equal to or over 64K word.
PC[11:0] ← imm:12
CALLS unconditionally calls a subroutine residing at the address specified by imm:12.
Flags:
–
Example:ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CALLS
Waitꢀ
•ꢀ
•ꢀ
•ꢀ
Wait: NOP
NOP
NOP
RET
Because this is a 1-word instruction, the saved returning address on stack is (PC + 1).
ꢀ
ꢀ
ꢑꢒꢕꢓꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢆꢑꢋꢀꢁꢀ(ꢛꢉꢃꢀꢅꢗꢆꢛꢀꢈꢛꢝꢊꢛꢚꢏꢎꢎꢛꢊꢀ
Format:
CLD imm:8, <op>
<op>: GPR
Operation:ꢀ
(imm:8) ← <op>
CLD loads the value of <op> into (imm:8), where imm:8 is used to access the external
coprocessor's address space.
Flags:
–
Example:ꢀ
ꢀ
ꢀ
ꢀ
AH
AL
BH
BL
ꢀ
EQU 00h
EQU 01h
EQU 02h
EQU 03hꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
•ꢀ
ꢀ
ꢀ
ꢀ
CLD
CLD
AH, R0
// A[15:8] ← R0
// A[7:0] ← R1
AL, R1
CLD
CLD
BH, R2
BL, R3
// B[15:8] ← R2
// B[7:0] ← R3
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.
Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
ꢑꢒꢕꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢆꢑꢋꢀꢁ (ꢛꢉꢃꢀ)ꢊꢛꢜꢀꢈꢛꢝꢊꢛꢚꢏꢎꢎꢛꢊ
Format:
CLD <op>, imm:8
ꢀ
<op>: GPRꢀ
Operation:
<op> ← (imm:8)
ꢀ
CLD loads a value from the coprocessor, whose address is specified by imm:8.ꢀ
Flags:
Z: set if the loaded value in <op1> is zero. Reset if not.
ꢀ
ꢀ
ꢀ
N: set if the MSB of the loaded value in <op1> is 1. Reset if not. ꢀ
Example:ꢀ
ꢀ
ꢀ
ꢀ
AH
AL
BH
BL
ꢀ
EQU 00h
EQU 01h
EQU 02h
EQU 03hꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
•ꢀ
ꢀ
ꢀ
ꢀ
CLD
CLD
R0, AH
// R0 ← A[15:8]
// R1 ← A[7:0]
R1, AL
CLD
CLD
R2, BH
R3, BL
// R2 ← B[15:8]
// R3 ← B[7:0]
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.
Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
ꢀ
ꢀ
ꢑꢒꢕꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢆꢇꢏꢀꢁꢀ*+ꢎꢀꢛꢊꢀꢌꢅꢆꢍꢄꢅꢎꢏꢀꢈꢛꢜꢝꢙꢏꢜꢏꢗꢆꢀ
Format:
COM <op>
<op>: GPR
Operation:ꢀ
<op> ← ~<op>
COM takes the bit-wise complement operation on <op> and stores the result in <op>.
Flags:
Z: set if result is zero. Reset if not.
N: set if the MSB of result is 1. Reset if not.
Example:ꢀ
Given: R1 = 5Ah
ꢀ
COM
R1
// R1 ← A5h, N flag is set to ‘1’
ꢀ
ꢑꢒꢕꢕꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢆꢇꢏꢒꢀꢁꢀ,+ꢎꢀꢈꢛꢜꢝꢙꢏꢜꢏꢗꢆꢀ
Format:
Operation:ꢀ
Flags:
COM2 <op>
<op>: GPR
<op> ← ~<op> + 1
COM2 computes the 2's complement of <op> and stores the result in <op>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Example:ꢀ
Given: R0 = 00h, R1 = 5Ah
COM2
COM2
R0
R1
// R0 ← 00h, Z and C flags are set to ‘1’.
// R1 ← A6h, N flag is set to ‘1’.
ꢀ
ꢀ
ꢑꢒꢕꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢆꢇꢏꢆꢀꢁꢀꢌꢅꢆꢍꢄꢅꢎꢏꢀꢈꢛꢜꢝꢙꢏꢜꢏꢗꢆꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
Operation:ꢀ
Flags:
COMC <op>
<op>: GPR
<op> ← ~<op> + C
COMC takes the bit-wise complement of <op>, adds carry and stores the result in <op>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:ꢀ
If register pair R1:R0 is a 16-bit number, then the 2’s complement of R1:R0 can be obtained by
COM2 and COMC as following.
COM2
COMC
R0
R1
Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register pair
R1: R0 has value of FF01h, then 2’s complement of R1: R0 is made of 00FFh by COM2 and COMC.
At this time, by instruction COMC, zero (Z) flag is set to ‘1’ as if the result of 2’s complement for
16-bit number is zero. Therefore when programming 16-bit comparison, take care of the change of
Z flag.
ꢀ
ꢑꢒꢕꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢆꢇꢓꢀꢁꢀꢈꢛꢝꢊꢛꢚꢏꢎꢎꢛꢊꢀ
Format:
Operation:ꢀ
Flags:
COP #imm:12
COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals.
–ꢀ
Example:ꢀ
ꢀ
ꢀ
COP
COP
#0D01h
#0234h
// generate 1 word instruction code(FD01h)
// generate 1 word instruction code(F234h)
The above two instructions are equal to statement “ELD A, #1234h” for MAC816 operation. The
microcode of MAC instruction “ELD A, #1234h” is “FD01F234”, 2-word instruction. In this, code ‘F’
indicates ‘COP’ instruction.
ꢀ
ꢀ
ꢑꢒꢕꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢆꢓꢀꢁꢀꢈꢛꢜꢝꢉꢊꢏꢀ
Format:
Operation:ꢀ
Flags:
CP <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
<op1> + ~<op2> + 1
CP compares the values of <op1> and <op2> by subtracting <op2> from <op1>. Contents of <op1>
and <op2> are not changed.
C: set if carry is generated. Reset if not.
ꢀ
ꢀ
ꢀ
Z: set if result is zero (i.e., <op1> and <op2> are same). Reset if not.
V: set if overflow is generated. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
N: set if result is negative. Reset if not.
Example:ꢀ
Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1
CP
CP
CP
R0, 80h
R0, #73h
R0, R1
// C flag is set to ‘1’
// Z and C flags are set to ‘1’
// V flag is set to ‘1’
ꢀ
CP
CP
CP
CP
R1, @ID0
// Z and C flags are set to ‘1’
R1, @[ID0 – 5]
R2, @[ID0 + 7]!
R2, @[ID0 – 2]!
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
ꢀ
ꢀ
ꢀ
ꢑꢒꢕꢗꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢆꢓꢆꢈꢁꢀꢈꢛꢜꢝꢉꢊꢏꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
CPC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:ꢀ
<op1> ← <op1> + ~<op2> + C
ꢀ
CPC compares <op1> and <op2> by subtracting <op2> from <op1>. Unlike CP, however, CPC
adds (C - 1) to the result. Contents of <op1> and <op2> are not changed.
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
ꢀ
Example:
If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC
to compare two 16-bit numbers as follows.
ꢀ
CP
R0, R1
R2, R3
CPC
Because CPC considers C when comparing <op1> and <op2>, CP and CPC can be used in pair to
compare 16-bit operands. But note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit comparison, take care of the change of Z flag.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢕꢘꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢋꢉꢆꢀꢁꢀꢑꢏꢚꢊꢏꢜꢏꢗꢆꢀ
Format:
DEC <op>
<op>: GPR
Operation:ꢀ
<op> ← <op> + 0FFh
ꢀ
DEC decrease the value in <op> by adding 0FFh to <op>.
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
ꢀ
ꢀ
ꢀ
Example:ꢀ
Given: R0 = 80h, R1 = 00h
DEC
DEC
R0
R1
// R0 ← 7Fh, C, V and N flags are set to ‘1’
// R1 ← FFh, N flags is set to ‘1’
ꢑꢒꢆꢅꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢋꢉꢆꢆꢀꢁꢀꢑꢏꢚꢊꢏꢜꢏꢗꢆꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
DECC <op>
<op>: GPR
Operation:ꢀ
<op> ← <op> + 0FFh + C
ꢀ
DECC decrease the value in <op> when carry is not set. When there is a carry, there is no
change in the value of <op>.
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
ꢀ
ꢀ
ꢀ
Example:ꢀ
If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to
decrement 16-bit number as follows.
ꢀ
DEC
R0
R1
DECC
Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming
16-bit decrement, take care of the change of Z flag.
ꢀ
ꢀ
ꢑꢒꢆꢓꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢋꢀꢈꢁꢀꢑꢅꢎꢉ"ꢙꢏꢀ&ꢗꢆꢏꢊꢊ$ꢝꢆꢀ%ꢖꢎꢏ$ꢃꢛꢀ&ꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:
DI
Operation:ꢀ
Disables interrupt globally. It is same as “AND SR0, #0FDh” .
DI instruction sets bit1 (ie: global interrupt enable) of SR0 register to “0”
Flags:ꢀ ꢀ
–
Example:ꢀ
Given: SR0 = 03h
DI
// SR0 ← SR0 & 11111101b
DI instruction clears SR0[1] to ‘0’, disabling interrupt processing.
ꢀ
ꢀ
ꢀ
ꢑꢒꢆꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉꢀꢈꢁꢀ-ꢗꢉ"ꢙꢏꢀ&ꢗꢆꢏꢊꢊ$ꢝꢆꢀ%ꢖꢎꢏ$ꢃꢛꢀ&ꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:
EI
Operation:ꢀ
Enables interrupt globally. It is same as “OR SR0, #02h” .
EI instruction sets the bit1 (ie: global interrupt enable) of SR0 register to “1”
Flags:ꢀ ꢀ
–
ꢀ
Example:ꢀ
Given: SR0 = 01h
EI
// SR0 ← SR0 | 00000010b
The statement “EI” sets the SR0[1] to ‘1’, enabling all interrupts.
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢆꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢀꢋꢑꢉꢈꢁꢀ&ꢃꢙꢏꢀ.ꢝꢏꢊꢉꢆꢅꢛꢗꢀ%ꢖꢎꢏ$ꢃꢛꢀ&ꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:
IDLE
Operation:ꢀ
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue.
Idle mode can be released by an interrupt or reset operation.
The IDLE instruction is a pseudo instruction. It is assembled as “SYS #05H”, and this generates the
SYSCP[7-0] signals. Then these signals are decoded and the decoded signals execute the idle
operation.
Flags:ꢀ ꢀ
ꢋꢏꢌꢐꢔꢀ ꢀ
–
ꢙꢚꢔꢂꢅꢔꢒꢋꢂꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅꢂꢏ(ꢂ2ꢝ3?ꢂꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅꢂꢄꢊꢂꢔꢒꢔꢎꢍꢋꢔꢉꢞꢉꢊꢏꢉꢕꢈꢔꢇꢊꢔꢂꢍꢊꢔꢂꢋꢚꢔꢂ*ꢜ%ꢂꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅꢂꢇ(ꢋꢔꢌꢂꢋꢚꢔꢉ2ꢝ3?ꢂꢂ
ꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅꢐꢂ
Example:ꢀ
IDLE
NOP
NOP
NOP
•ꢀ
ꢂꢂ
ꢂꢂ
•ꢀ
•ꢀ
ꢀ
The IDLE instruction stops the CPU clock but not the system clock.
ꢀ
ꢑꢒꢆꢕꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢀꢁꢆꢀꢁꢀ&ꢗꢚꢊꢏꢜꢏꢗꢆꢀ
Format:
INC <op>
<op>: GPR
Operation:ꢀ
<op> ← <op> + 1
INC increase the value in <op>.
ꢀ
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:ꢀ
Given: R0 = 7Fh, R1 = FFh
INC
INC
R0
R1
// R0 ← 80h, V flag is set to ‘1’
// R1 ← 00h, Z and C flags are set to ‘1’
ꢀ
ꢀ
ꢀ
ꢑꢒꢆꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢀꢁꢆꢆꢀꢁꢀ&ꢗꢚꢊꢏꢜꢏꢗꢆꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
INCC <op>
<op>: GPR
Operation:ꢀ
<op> ← <op> + C
INCC increase the value of <op> only if there is carry. When there is no carry, the value of
<op> is not changed.
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment
16-bit number as following.
ꢀ
INC
R0
R1
INCC
Assume R1:R0 is 0010h, statement “INC R0” increase R0 by one without carry and statement
“INCC R1” set zero (Z) flag to ‘1’ as if the result of 16-bit increment is zero. Note that zero (Z) flag do
not exactly reflect result of 16-bit operation. Therefore when programming 16-bit increment, take
care of the change of Z flag.
ꢑꢒꢆꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢀꢄꢉꢃꢀꢁꢀꢓꢏꢆ$ꢊꢗꢀ)ꢊꢛꢜꢀ&ꢗꢆꢏꢊꢊ$ꢝꢆꢀ/ꢉꢗꢃꢙꢅꢗ0ꢀ
Format:
Operation:ꢀ
ꢀ
IRET
PC ← HS[sptr - 2], sptr ← sptr - 2
IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to
PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation.
Flags:
–
ꢋꢏꢌꢐꢔꢉ ꢉ
The program size (indicated by the nP64KW signal) determines which portion of PC is updated.
When the program size is less than 64K word, only the lower 16 bits of PC are updated
(i.e., PC[15:0] ← HS[sptr – 2]).
When the program size is 64K word or more, the action taken is PC[19:0] ← HS[sptr - 2].ꢀ
Example:ꢀꢀ
ꢀ
SF_EXCEP:
NOP
•ꢀ
// Stack full exception service routine
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ ꢀ
IRET
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢆꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢔꢁꢕꢋꢁꢀ1$ꢜꢝꢀꢐꢛꢆꢀ2ꢏꢊꢛꢀꢄꢅꢆꢇꢀꢑꢏꢙꢉꢋꢀꢎꢙꢛꢆꢀ
Format:
JNZD <op>, imm:8
<op>: GPR (bank 3’s GPR only)
imm:8 is an signed numberꢀ
PC ← PC[delay slot] - 2’s complement of imm:8
<op> ← <op> - 1
Operation:
JNZD performs a backward PC-relative jump if <op> evaluates to be non-zero. Furthermore, JNZD
decrease the value of <op>. The instruction immediately following JNZD (i.e., in delay slot) is
always executed, and this instruction must be 1 cycle instruction.ꢀ
Flags:
–ꢀ
ꢋꢏꢌꢐꢔꢉ ꢉ
Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however, that
the chosen instruction should be “dead” outside the loop for it executes even when the loop is exited
(i.e., JNZD is not taken).ꢀ
Example:ꢀ
Given: IDH = 03h, eid = 1
BANK
LD
#3
R0, #0FFh
R1, #0
// R0 is used to loop counter
LD
%1
LD
IDL0, R0
R0, %B1
@ID0, R1
ꢀ
ꢀ
JNZD
LD
// If R0 of bank3 is not zero, jump to %1.
// Clear register pointed by ID0ꢀ
•ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
ꢀ
ꢀ
ꢀ
This example can be used for RAM clear routine. The last instruction is executed even if the loop is
exited.
ꢀ
ꢀ
ꢀ
ꢑꢒꢆꢗꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢔꢓꢀꢁꢀꢈꢛꢗꢃꢅꢆꢅꢛꢗꢉꢙꢀ1$ꢜꢝꢀ%ꢖꢎꢏ$ꢃꢛꢀ&ꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:
JP cc:4 imm:20
JP cc:4 imm:9
Operation:ꢀ
If JR can access the target address, JP command is assembled to JR (1 word instruction) in linking
time, else the JP is assembled to LJP (2 word instruction) instruction.
There are 16 different conditions that can be used, as described in table 7-6.
Example:ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
%1
LD
•ꢀ
R0, #10h
// Assume address of label %1 is 020Dhꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
JP
Z, %B1
C, %F2
// Address at 0264h
// Address at 0265h
JP
•ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
•ꢀ
%2
LD
•ꢀ
R1, #20h
// Assume address of label %2 is 089Ch
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
In the above example, the statement “JP Z, %B1” is assembled to JR instruction. Assuming that
current PC is 0264h and condition is true, next PC is made by PC[11:0] ← PC[11:0] + offset, offset
value is “64h + A9h” without carry. ‘A9’ means 2’s complement of offset value to jump backward.
Therefore next PC is 020Dh. On the other hand, statement “JP C, %F2” is assembled to LJP
instruction because offset address exceeds the range of imm:9.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢆꢘꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢂ
ꢔꢄꢀꢁꢀꢈꢛꢗꢃꢅꢆꢅꢛꢗꢉꢙꢀ1$ꢜꢝꢀꢓꢏꢙꢉꢆꢅ3ꢏꢀ
Format:
JR cc:4 imm:9
cc:4: 4-bit condition code
Operation:ꢀ
PC[11:0] ← PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign-extended
to 12 bits when added to PC.
There are 16 different conditions that can be used, as described in table 7-6.
Flags:
–
ꢋꢏꢌꢐꢔꢉ ꢉ
Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to
compute the actual jump address, while LJP directly jumps to imm:20, the target.ꢀ
Example:ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
JR
•ꢀ
Z, %1
// Assume current PC = 1000h
// Address at 10A5h
ꢀ
ꢀ
•ꢀ
ꢀ
•ꢀ
%1
LD
•ꢀ
R0, R1
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to ‘1’. The range
of the relative address is from +255 to –256 because imm:9 is signed number.
ꢀ
ꢀ
ꢀ
ꢑꢒꢖꢅꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢆꢊꢑꢑꢀꢁꢀꢈꢛꢗꢃꢅꢆꢅꢛꢗꢉꢙꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀꢈꢉꢙꢙꢀ
Format:
LCALL cc:4, imm:20
Operation:ꢀ
HS[sptr][15:0] ← current PC + 2, sptr ← sptr + 2, PC[15:0] ← imm[15:0] if the condition holds
and the program size is less than 64K word.
HS[sptr][19:0] ← current PC + 2, sptr ← sptr + 2, PC[19:0] ← imm:20 if the condition holds and
the program size is equal to or over 64K word.
PC[11:0] ← PC[11:0] + 2 otherwise.
LCALL instruction is used to call a subroutine whose starting address is specified by imm:20.
Flags:
–
Example:ꢀ
ꢀ
ꢀ
LCALL
LCALL
L1
C, L2
Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word instruction,
the saved returning address on stack is (PC + 2).
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢖꢓꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢋꢈꢖꢗꢘꢙꢚꢀꢁꢀ(ꢛꢉꢃꢀꢅꢗꢆꢛꢀ4ꢏꢜꢛꢊꢋꢀ
Format:
LD adr:8, <op>
<op>: GPR
Operation:ꢀ
DM[00h:adr:8] ← <op> if eid = 0
DM[IDH:adr:8] ← <op> if eid = 1
LD adr:8 loads the value of <op> into a memory location. The memory location is determined by
the eid bit and adr:8.
Flags:
ꢀ
–
Example:ꢀ
Given: IDH = 01h
LD
80h, R0
If eid bit of SR0 is zero, the statement “LD 80h, R0” load value of R0 into DM[0080h], else eid bit
was set to ‘1’, the statement “LD 80h, R0” load value of R0 into DM[0180h]
ꢑꢒꢖꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢋꢈꢛꢜꢗꢝꢀꢁꢀ(ꢛꢉꢃꢀꢅꢗꢆꢛꢀ4ꢏꢜꢛꢊꢋꢀ&ꢗꢃꢏ5ꢏꢃꢀ
Format:
LD @idm, <op>
<op>: GPR
Operation:ꢀ
(@idm) ← <op>
LD @idm loads the value of <op> into the memory location determined by @idm. Details of the
@idm format and how the actual address is calculated can be found in chapter 2.
Flags:
–
Example:ꢀ
Given R0 = 5Ah, IDH:IDL0 = 8023h, eid = 1
LD
LD
LD
LD
LD
@ID0, R0
// DM[8023h] ← 5Ah
@ID0 + 3, R0
@[ID0-5], R0
@[ID0+4]!, R0
@[ID0-2]!, R0
// DM[8023h] ← 5Ah, IDL0 ← 26h
// DM[801Eh] ← 5Ah, IDL0 ← 1Eh
// DM[8027h] ← 5Ah, IDL0 ← 23h
// DM[8021h] ← 5Ah, IDL0 ← 23h
ꢀ
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢖꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢋꢀꢁꢀ(ꢛꢉꢃꢀꢓꢏ0ꢅꢎꢆꢏꢊꢀ
Format:
LD <op1>, <op2>
<op1>: GPR
<op2>: GPR, SPR, adr:8, @idm, #imm:8
<op1> ← <op2>
Operation:ꢀ
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
ꢀ
Example:ꢀ
Given: R0 = 5Ah, R1 = AAh, IDH:IDL0 = 8023h, eid = 1
LD
LD
LD
LD
R0, R1
// R0 ← AAh
R1, IDH
R2, 80h
R0, #11h
// R1 ← 80h
// R2 ← DM[8080h]
// R0 ← 11h
LD
LD
LD
LD
R0, @ID0+1
R1, @[ID0-2]
R2, @[ID0+3]!
R3, @[ID0-5]!
// R0 ← DM[8023h], IDL0 ← 24h
// R1 ← DM[8021h], IDL0 ← 21h
// R2 ← DM[8026h], IDL0 ← 23h
// R3 ← DM[801Eh], IDL0 ← 23h
ꢀ
ꢀ
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢖꢕꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢋꢀꢁꢀ(ꢛꢉꢃꢀꢕꢖꢓ6"ꢉꢗꢘꢃ7ꢀꢕꢖꢓ6"ꢉꢗꢘꢎꢀ
Format:
LD <op1>, <op2>
<op1>: GPR: bankd
<op2>: GPR: banks
Operation:ꢀ
<op1> ← <op2>
LD loads a value of a register in a specified bank (banks) into another register in a specified bank
(bankd).
Flags:
Z: set if result is zero. Reset if not.
ꢀ
N: exclusive OR of V and MSB of result.
ꢀ
Example:ꢀ
ꢀ
LD
LD
R2:1, R0:3
R0:0, R0:2
// Bank1’s R2 ← bank3’s R0
// Bank0’s R0 ← bank2’s R0
ꢀ
ꢀ
ꢑꢒꢖꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢋꢀꢁꢀ(ꢛꢉꢃꢀꢕꢖꢓ7ꢀꢞꢌ/#ꢞꢌ(ꢀ
Format:
LD <op1>, <op2>
<op1>: GPR
<op2>: TBH/TBL
Operation:ꢀ
<op1> ← <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
N: exclusive OR of V and MSB of result.
Example:
Given: register pair R1:R0 is 16-bit unsigned data.
LDCꢀ
LD
@IL
// TBH:TBL ← PM[ILX:ILH:ILL]ꢀ
// R1 ← TBH
ꢀ
R1, TBH
R0, TBL
LD
// R0 ← TBL
ꢑꢒꢖꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢋꢀꢁꢀ(ꢛꢉꢃꢀꢞꢌ/#ꢞꢌ(7ꢀꢕꢖꢓꢀ
Format:
LD <op1>, <op2>
<op1>: TBH/TBL
<op2>: GPR
Operation:ꢀ
<op1> ← <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
–ꢀ
Example:
Given: register pair R1:R0 is 16-bit unsigned data.
LD
LD
TBH, R1
TBL, R0
// TBH ← R1
// TBL ← R0
ꢀ
ꢀ
ꢑꢒꢖꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢋꢈꢂꢓꢄꢈꢁꢀ(ꢛꢉꢃꢀꢒꢖꢓꢀ
Format:
LD <op1>, <op2>
<op1>: SPR
<op2>: GPR
Operation:ꢀ
<op1> ← <op2>
LD SPR loads the value of a GPR into an SPR.
Refer to Table 3-1 for more detailed explanation about kind of SPR.
Flags:
–
Example:
Given: register pair R1:R0 = 1020h
LD
LD
ILH, R1
ILL, R0
// ILH ← 10h
// ILL ← 20h
ꢑꢒꢖꢗꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢋꢈꢂꢓꢄꢌꢀꢁꢀ(ꢛꢉꢃꢀꢒꢖꢓꢔꢀ&ꢜꢜꢏꢃꢅꢉꢆꢏꢀ
Format:
LD SPR0, #imm:8
Operation:ꢀ
SPR0 ← imm:8
LD SPR0 loads an 8-bit immediate value into SPR0.
–
Flags:
ꢀ
Example:
Given: eid = 1, idb = 0 (index register bank 0 selection)
ꢀ
LD
LD
LD
LD
IDH, #80h
IDL1, #44h
IDL0, #55h
SR0, #02h
// IDH point to page 80h
The last instruction set ie (global interrupt enable) bit to ‘1’.
Special register group 1 (SPR1) registers are not supported in this addressing mode.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢖꢘꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢋꢆꢈꢁꢀ(ꢛꢉꢃꢀꢈꢛꢃꢏꢀꢀ
Format:ꢀ
LDC <op1>
ꢀ
<op1>: @IL, @IL+
Operation:ꢀ
TBH:TBL ← PM[ILX:ILH:ILL]
ILL ← ILL + 1 (@IL+ only)
LDC loads a data item from program memory and stores it in the TBH:TBL register pair.
@IL+ increase the value of ILL, efficiently implementing table lookup operations.
Flags:
–
Example:ꢀ
ꢀ
LD
ILX, R1
ILH, R2
ILL, R3
@IL
LD
LD
LDC
// Loads value of PM[ILX:ILH:ILL] into TBH:TBL
LD
LD
R1, TBH
R0, TBL
// Move data in TBH:TBL to GPRs for further processing
The statement “LDC @IL” do not increase, but if you use statement “LDC @IL+”, ILL register is
increased by one after instruction execution.
ꢑꢒꢑꢅꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢔꢓꢀꢁꢀꢈꢛꢗꢃꢅꢆꢅꢛꢗꢉꢙꢀ1$ꢜꢝꢀ
Format:
LJP cc:4, imm:20
cc:4: 4-bit condition code
Operation:ꢀ
PC[15:0] ← imm[15:0] if condition is true and the program size is less than 64K word. If the program
is equal to or larger than 64K word, PC[19:0] ← imm[19:0] as long as the condition is true. There
are 16 different conditions that can be used, as described in table 7-6.
Flags:
–
ꢋꢏꢌꢐꢔꢉ ꢉ
LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address
of the jump.ꢀ
Example:ꢀ
ꢀ
LJP
•ꢀ
C, %1
// Assume current PC = 0812h
// Address at 10A5h
ꢀ
•ꢀ
ꢀ
•ꢀ
%1
LD
•ꢀ
R0, R1
ꢀ
ꢀ
•ꢀ
•ꢀ
After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢓꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢑꢁꢎꢀꢁꢀ(ꢅꢗꢘꢏꢃꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀꢈꢉꢙꢙꢀꢈꢛꢗꢃꢅꢆꢅꢛꢗꢉꢙꢀ
Format:
LLNK cc:4, imm:20
cc:4: 4-bit condition code
Operation:ꢀ
If condition is true, IL[19:0] ← {PC[19:12], PC[11:0] + 2}.
Further, when the program is equal to or larger than 64K word, PC[19:0] ← imm[19:0] as long as
the condition is true. If the program is smaller than 64K word, PC[15:0] ← imm[15:0].
There are 16 different conditions that can be used, as described in table 7-6.
Flags:
–
ꢋꢏꢌꢐꢔꢉ ꢉ
LLNK is used to conditionally to call a subroutine with the return address saved in the link register
(IL) withoutꢂꢊꢋꢇꢎ-ꢂꢏꢕꢔꢌꢇꢋꢄꢏꢅꢐ This is a 2-word instruction.ꢂꢀ
Example:ꢀ
ꢀ
LLNK
NOP
•ꢀ
Z, %1
// Address at 005Ch, ILX:ILH:ILL ← 00:00:5Eh
// Address at 005Eh
ꢀ
ꢀ
•ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
ꢀ
ꢀ
%1
ꢀ
LD
•ꢀ
R0, R1ꢀ
ꢀ
•ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
ꢀ
LRET
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢁꢎꢀꢁꢀ(ꢅꢗꢘꢏꢃꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀꢈꢉꢙꢙꢀ%ꢖꢎꢏ$ꢃꢛꢀ&ꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:
LNK cc:4, imm:20
LNK imm:12
Operation:ꢀ
If LNKS can access the target address and there is no conditional code (cc:4), LNK command is
assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2
word instruction).
Example:ꢀ
ꢀ
LNK
LNK
NOP
•ꢀ
Z, Link1
Link2
// Equal to “LLNK Z, Link1”
// Equal to “LNKS Link2”
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
•ꢀ
Link2: NOP
•ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
ꢀ
•ꢀ
LRETꢀ
ꢀ
Subroutinesꢀ
section CODE, ABS 0A00h
Subroutinesꢀ
ꢀ
Link1:ꢀ NOP
•ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
LRET
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢑꢁꢎꢂꢀꢁꢀ(ꢅꢗꢘꢏꢃꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀꢈꢉꢙꢙꢀ
Format:
LNKS imm:12
Operation:ꢀ
IL[19:0] ← {PC[19:12], PC[11:0] + 1} and PC[11:0] ← imm:12
LNKS saves the current PC in the link register and jumps to the address specified by imm:12.
Flags:
–
ꢋꢏꢌꢐꢔꢉ ꢉ
LNKS is used to call a subroutine with the return address saved in the link register (IL) withoutꢂꢊꢋꢇꢎ-ꢂ
ꢏꢕꢔꢌꢇꢋꢄꢏꢅꢐꢂ
Example:ꢀ
ꢀ
LNKS
NOP
•ꢀ
Link1ꢀ
// Address at 005Ch, ILX:ILH:ILL ← 00:00:5Dh
// Address at 005Dhꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
• ꢀ
ꢀ
Link1: NOP
•ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
LRETꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢕꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢑꢄꢉꢃꢀꢁꢀꢓꢏꢆ$ꢊꢗꢀ)ꢊꢛꢜꢀ(ꢅꢗꢘꢏꢃꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀꢈꢉꢙꢙꢀ
Format:
LRET
Operation:ꢀ
PC ← IL[19:0]
LRET returns from a subroutine by assigning the saved return address in IL to PC.
Flags:
–
Example:ꢀ
ꢀ
ꢀ
ꢀ
LNK
Link1
Link1: NOP
•ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
•ꢀ
•ꢀ
LRET
;
PC[19:0] ← ILX:ILH:ILLꢀꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢁꢇꢓꢀꢁꢀꢐꢛꢀ.ꢝꢏꢊꢉꢆꢅꢛꢗꢀ
Format:
NOP
Operation:ꢀ
No operation.
When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction
time is delayed by approximately one machine cycle per each NOP instruction encountered.
Flags:
–
Example:ꢀ
ꢀ
NOP
ꢑꢒꢑꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢇꢄꢀꢁꢀꢌꢅꢆꢍꢄꢅꢎꢏꢀ.ꢓꢀ
Format:
OR <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:ꢀ
<op1> ← <op1> | <op2>
OR performs the bit-wise OR operation on <op1> and <op2> and stores the result in <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
ꢀ
Example:ꢀ
Given: IDH:IDL0 = 031Eh, eid = 1
OR
OR
OR
R0, 80h
R1, #40h
R1, R0
// R0 ← R0 | DM[0380h]
// Mask bit6 of R1
// R1 ← R1 | R0
OR
OR
OR
OR
R0, @ID0
// R0 ← R0 | DM[031Eh], IDL0 ← 1Eh
// R1 ← R1 | DM[031Dh], IDL0 ← 1Dh
// R2 ← R2 | DM[031Fh], IDL0 ← 1Eh
// R3 ← R3 | DM[031Dh], IDL0 ← 1Eh
R1, @[ID0-1]
R2, @[ID0+1]!
R3, @[ID0-1]!
ꢀ
ꢀ
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢇꢄꢈꢂꢄꢌꢀꢁꢀꢌꢅꢆꢍꢄꢅꢎꢏꢀ.ꢓꢀꢄꢅꢆꢇꢀꢒꢓꢔꢀ
Format:
OR SR0, #imm:8
Operation:ꢀ
SR0 ← SR0 | imm:8
OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0.
–
Flags:
Example:ꢀ
Given: SR0 = 00000000b
EID
IE
EQU
EQU
EQU
EQU
EQU
01h
02h
04h
40h
80h
IDB1
IE0
IE1
OR
OR
SR0, #IE | IE0 | IE1
SR0, #00000010b
In the first example, the statement “OR SR0, #EID|IE|IE0” set global interrupt(ie), interrupt 0(ie0)
and interrupt 1(ie1) to ‘1’ in SR0. On the contrary, enabled bits can be cleared with instruction “AND
SR0, #imm:8”. Refer to instruction AND SR0 for more detailed explanation about disabling bit.
In the second example, the statement “OR SR0, #00000010b” is equal to instruction EI, which is
enabling interrupt globally.
ꢑꢒꢑꢗꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢓꢇꢓꢀꢁꢀꢖ.ꢖꢀ
Format:
POP
sptr ← sptr – 2
Operation:ꢀ
POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated.
–
Flags:
Example:ꢀ
Given: sptr[5:0] = 001010b
ꢀ
POP
This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b.
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢑꢘꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢓꢇꢓꢀꢁꢀꢖ.ꢖꢀꢆꢛꢀꢓꢏ0ꢅꢎꢆꢏꢊꢀ
Format:
POP <op>
<op>: GPR, SPR
Operation:ꢀ
<op> ← HS[sptr - 1], sptr ← sptr - 1
ꢀ
POP copies the value on top of the stack to <op> and decrease sptr by 1.
Flags:
Z: set if the value copied to <op> is zero. Reset if not.
N: set if the value copied to <op> is negative. Reset if not.
When <op> is SPR, no flags are affected, including Z and N.
ꢀ
Example:ꢀ
ꢀ
POP
POP
R0
// R0 ← HS[sptr-1], sptr ← sptr-1
// IDH ← HS[sptr-1], sptr ← sptr-1
ꢀ
IDH
ꢀ
In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction “POP IDH” load
value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about POP
operations for hardware stack.
ꢀ
ꢑꢒꢗꢅꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢓꢅꢂꢞꢀꢁꢀꢖ$ꢎꢇꢀꢓꢏ0ꢅꢎꢆꢏꢊꢀ
Format:
PUSH <op>
<op>: GPR, SPR
Operation:ꢀ
HS[sptr] ← <op>, sptr ← sptr + 1
PUSH stores the value of <op> on top of the stack and increase sptr by 1.
–
Flags:
Example:ꢀ
ꢀ
PUSH
PUSH
R0
// HS[sptr] ← R0, sptr ← sptr + 1
// HS[sptr] ← IDH, sptr ← sptr + 1
IDH
ꢀ
In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction “PUSH
IDH” load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0] be emptied.
Refer to chapter 5 for more detailed explanation about PUSH operations for hardware stack.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢗꢓꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢄꢉꢃꢀꢁꢀꢓꢏꢆ$ꢊꢗꢀ)ꢊꢛꢜꢀꢒ$"ꢊꢛ$ꢆꢅꢗꢏꢀ
Format:
RET
Operation:ꢀ
PC ← HS[sptr - 2], sptr ← sptr – 2
RET pops an address on the hardware stack into PC so that control returns to the subroutine call
site.
Flags:
–
Example:ꢀ
Given: sptr[5:0] = 001010b
CALLS
Wait
// Address at 00120h
// Address at 01000h
•ꢀ
•ꢀ
•ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Wait: NOP
NOP
NOP
NOP
ꢀ
NOP
RET
After the first instruction CALLS execution, “PC+1”, 0121h is loaded to HS[5] and hardware stack
pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value
0121h on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became
001010b.
ꢀ
ꢀ
ꢑꢒꢗꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢄꢑꢀꢁꢀꢓꢛꢆꢉꢆꢏꢀ(ꢏ)ꢆꢀ
Format:
RL <op>
<op>: GPR
Operation:ꢀ
C ← <op>[7], <op> ← {<op>[6:0], <op>[7]}
RL rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C).
Flags:
ꢀ
C: set if the MSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:ꢀ
Given: R0 = 01001010b, R1 = 10100101b
RL
RL
R0
R1
// N flag is set to ‘1’, R0 ← 10010100b
// C flag is set to ‘1’, R1 ← 01001011b
ꢀ
ꢀ
ꢑꢒꢗꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢄꢑꢆꢀꢁꢀꢓꢛꢆꢉꢆꢏꢀ(ꢏ)ꢆꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
RLC <op>
<op>: GPR
Operation:ꢀ
C ← <op>[7], <op> ← {<op>[6:0], C}
RLC rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C), and the original C bit is copied into <op>[0].
Flags:
ꢀ
C: set if the MSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:ꢀ
Given: R2 = A5h, if C = 0
ꢀ
RLC
R2
// R2 ← 4Ah, C flag is set to ‘1’
RL
R0
R1
RLC
In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are
used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
ꢀ
ꢑꢒꢗꢕꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢄꢄꢀꢁꢀꢓꢛꢆꢉꢆꢏꢀꢓꢅ0ꢇꢆꢀ
Format:
RR <op>
<op>: GPR
Operation:ꢀ
C ← <op>[0], <op> ← {<op>[0], <op>[7:1]}
RR rotates the value of <op> to the right and stores the result back into <op>. The original LSB of
<op> is copied into carry (C).
Flags:
ꢀ
C: set if the LSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:ꢀ
Given: R0 = 01011010b, R1 = 10100101b
RR
RR
R0
R1
// No change of flag, R0 ← 00101101b
// C and N flags are set to ‘1’, R1 ← 11010010b
ꢀ
ꢀ
ꢑꢒꢗꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢄꢄꢆꢀꢁꢀꢓꢛꢆꢉꢆꢏꢀꢓꢅ0ꢇꢆꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
RRC <op>
<op>: GPR
Operation:ꢀ
C ← <op>[0], <op> ← {C, <op>[7:1]}
RRC rotates the value of <op> to the right and stores the result back into <op>. The original LSB of
<op> is copied into carry (C), and C is copied to the MSB.
Flags:
ꢀ
C: set if the LSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:ꢀ
Given: R2 = A5h, if C = 0
ꢀ
RRC
R2
// R2 ← 52h, C flag is set to ‘1’
RR
R0
R1
RRC
In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC are
used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
ꢑꢒꢗꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢂꢍꢆꢀꢁꢀꢒ$"ꢆꢊꢉꢚꢆꢀꢄꢅꢆꢇꢀꢈꢉꢊꢊꢋꢀ
Format:
SBC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:ꢀ
<op1> ← <op1> + ~<op2> + C
ꢀ
SBC computes (<op1> - <op2>) when there is carry and (<op1> - <op2> - 1) when there is no
carry.
Flags:
ꢀ
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
N: set if result is negative. Reset if not.
Example:
ꢀ
SBC
R0, 80h
R0, R1
// If eid = 0, R0 ← R0 + ~DM[0080h] + C
// If eid = 1, R0 ← R0 + ~DM[IDH:80h] + C
SBC
// R0 ← R0 + ~R1 + C
SUB
SBC
R0, R2
R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of “ADD R0, R2” is not zero, zero (Z) flag can be set to ‘1’ if the
result of “SBC R1,R3” is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit addition, take care of the change of Z flag.
ꢀ
ꢀ
ꢑꢒꢗꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢂꢑꢀꢁꢀꢒꢇꢅ)ꢆꢀ(ꢏ)ꢆꢀꢀ
Format:
SL <op>
<op>: GPR
Operation:ꢀ
C ← <op>[7], <op> ← {<op>[6:0], 0}
ꢀ
SL shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).
Flags:
ꢀ
C: set if the MSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = 01001010b, R1 = 10100101b
SL
SL
R0
R1
// N flag is set to ‘1’, R0 ← 10010100b
// C flag is set to ‘1’, R1 ← 01001010b
ꢀ
ꢀ
ꢀ
ꢑꢒꢗꢗꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢂꢑꢊꢀꢁꢀꢒꢇꢅ)ꢆꢀ(ꢏ)ꢆꢀꢂꢊꢅꢆꢇꢜꢏꢆꢅꢚꢀ
Format:
SLA <op>
ꢀ
<op>: GPR
Operation:ꢀ
C ← <op>[7], <op> ← {<op>[6:0], 0}
ꢀ
SLA shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).
Flags:
ꢀ
C: set if the MSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
V: set if the MSB of the result is different from C. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
ꢀ
ꢀ
ꢀ
Example:
Given: R0 = AAh
ꢀ
SLA
R0
// C, V, N flags are set to ‘1’, R0 ← 54h
ꢀ
ꢀ
ꢀ
ꢑꢒꢗꢘꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢂꢄꢀꢁꢀꢒꢇꢅ)ꢆꢀꢓꢅ0ꢇꢆꢀ
Format:
ꢀ
SR <op>
<op>: GPR
Operation:ꢀ
C ← <op>[0], <op> ← {0, <op>[7:1]}
SR shifts <op> to the right by 1 bit. The LSB of the original <op> (i.e., <op>[0]) is copied into carry
(C).
Flags:
C: set if the LSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = 01011010b, R1 = 10100101b
SR
SR
R0
R1
// No change of flags, R0 ← 00101101b
// C flag is set to ‘1’, R1 ← 01010010b
ꢀ
ꢀ
ꢑꢒꢘꢅꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢂꢄꢊꢀꢁꢀꢒꢇꢅ)ꢆꢀꢓꢅ0ꢇꢆꢀꢂꢊꢅꢆꢇꢜꢏꢆꢅꢚꢀ
Format:
ꢀ
SRA <op>
<op>: GPR
Operation:ꢀ
C ← <op>[0], <op> ← {<op>[7], <op>[7:1]}
SRA shifts <op> to the right by 1 bit while keeping the sign of <op>. The LSB of the original <op>
(i.e., <op>[0]) is copied into carry (C).
Flags:
C: set if the LSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
ꢀ
ꢀ
ꢀ
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
ꢋꢏꢌꢐꢔꢀ ꢀ
@&Gꢂ-ꢔꢔꢕꢊꢂꢋꢚꢔꢂꢊꢄ/ꢅꢂꢖꢄꢋꢂꢏꢌꢂꢋꢚꢔꢂꢛ@,ꢂ#HꢏꢕI6 9'ꢂꢄꢅꢂꢄꢋꢊꢂꢏꢌꢄ/ꢄꢅꢇꢈꢂꢕꢏꢊꢄꢋꢄꢏꢅꢐꢂ2(ꢂ@&GꢂꢄꢊꢂꢔꢒꢔꢎꢍꢋꢔꢉꢂJ*.ꢂꢋꢄꢓꢔꢊꢞꢂ*ꢂꢂ
ꢊꢄ/ꢅꢄ(ꢄꢎꢇꢅꢋꢂꢖꢄꢋꢊꢂAꢄꢈꢈꢂꢖꢔꢂꢊꢔꢋꢞꢂ(ꢏꢈꢈꢏAꢔꢉꢂꢖ1ꢂꢋꢚꢔꢂꢊꢚꢄ(ꢋꢔꢉꢂꢖꢄꢋꢊꢐꢂ
ꢂ
ꢂ
ꢂ
Example:
Given: R0 = 10100101b
ꢀ
SRA
SRA
SRA
SRA
R0
R0
R0
R0
// C, N flags are set to ‘1’, R0 ← 11010010b
// N flag is set to ‘1’, R0 ← 11101001b
// C, N flags are set to ‘1’, R0 ← 11110100b
// N flags are set to ‘1’, R0 ← 11111010b
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢘꢓꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢂꢃꢇꢓꢀꢁꢀꢒꢆꢛꢝꢀ.ꢝꢏꢊꢉꢆꢅꢛꢗꢀ%ꢝꢎꢏ$ꢃꢛꢀꢅꢗꢎꢆꢊ$ꢚꢆꢅꢛꢗ'ꢀ
Format:ꢀ
STOP
Operation: ꢀ The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter the STOP mode. In the STOP mode, the contents of the on-chip CPU
registers, peripheral registers, and I/O port control and data register are retained. A reset operation
or external or internal interrupts can release stop mode. The STOP instruction is a pseudo
instruction. It is assembled as “SYS #0Ah”, which generates the SYSCP[7-0] signals. These signals
are decoded and stop the operation.
ꢋꢏꢌꢐꢔꢀ ꢀ
The next instruction of STOP instruction is executed, so please use the NOP instruction after the
STOP instruction.ꢀ
Example:
STOP
NOP
NOP
NOP
•ꢀ
•ꢀ
•ꢀ
In this example, the NOP instructions provide the necessary timing delay for oscillation stabilization
before the next instruction in the program sequence is executed. Refer to the timing diagrams of
oscillation stabilization, as described in Figure 15-4, 15-5ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑꢒꢘꢄꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢂꢅꢍꢀꢁꢀꢒ$"ꢆꢊꢉꢚꢆꢀ
Format:
SUB <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:ꢀ
<op1> ← <op1> + ~<op2> + 1
ꢀ
SUB adds the value of <op1> with the 2's complement of <op2> to perform subtraction on
<op1> and <op2>
Flags:
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 0150h, DM[0143h] = 26h, R0 = 52h, R1 = 14h, eid = 1
SUB
SUB
SUB
R0, 43h
R1, #16h
R0, R1
// R0 ← R0 + ~DM[0143h] + 1 = 2Ch
// R1 ← FEh, N flag is set to ‘1’
// R0 ← R0 + ~R1 + 1 = 3Eh
ꢀ
SUB
SUB
SUB
SUB
R0, @ID0+1
R0, @[ID0-2]
R0, @[ID0+3]!
R0, @[ID0-2]!
// R0 ← R0 + ~DM[0150h] + 1, IDL0 ← 51h
// R0 ← R0 + ~DM[014Eh] + 1, IDL0 ← 4Eh
// R0 ← R0 + ~DM[0153h] + 1, IDL0 ← 50h
// R0 ← R0 + ~DM[014Eh] + 1, IDL0 ← 50h
ꢀ
ꢀ
ꢀ
2ꢅꢂꢋꢚꢔꢂꢈꢇꢊꢋꢂꢋAꢏꢂꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅꢊꢞꢂꢋꢚꢔꢂꢆꢇꢈꢍꢔꢂꢏ(ꢂ2ꢝ472ꢝ3<ꢂꢄꢊꢂꢅꢏꢋꢂꢎꢚꢇꢅ/ꢔꢉꢐꢂ&ꢔ(ꢔꢌꢂꢋꢏꢂꢙꢇꢖꢈꢔꢂ ꢃ8ꢂ(ꢏꢌꢂꢓꢏꢌꢔꢂꢉꢔꢋꢇꢄꢈꢔꢉꢂ
ꢔꢒꢕꢈꢇꢅꢇꢋꢄꢏꢅꢂꢇꢖꢏꢍꢋꢂꢋꢚꢄꢊꢂꢇꢉꢉꢌꢔꢊꢊꢄꢅ/ꢂꢓꢏꢉꢔꢐꢂꢂThe example in the SBC description shows how SUB and
SBC can be used in pair to subtract a 16-bit number from another.ꢀ
ꢄꢉꢓꢂKꢂ2ꢝꢒ>ꢏ((ꢊꢔꢋ78ꢞꢂ62ꢝꢒꢃꢏ((ꢊꢔꢋ789ꢞꢂ62ꢝꢒ>ꢏ((ꢊꢔꢋ789:ꢞꢂ62ꢝꢒꢃꢏ((ꢊꢔꢋ789:ꢂ#2ꢝꢒꢂKꢂ2ꢝ<ꢂꢏꢌꢂ2ꢝꢗ'ꢂ
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ꢑꢒꢘꢁꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢂ ꢊꢓꢀꢁꢀꢒꢄꢉꢝꢀ
Format:
SWAP <op1>, <op2>
<op1>: GPR
<op2>: SPR
Operation:ꢀ
<op1> ← <op2>, <op2> ← <op1>
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SWAP swaps the values of the two operands.
–
Flags:
ꢋꢏꢌꢐꢔꢀ ꢀ
Among the SPRs, SR0 and SR1 can not be used as <op2>.ꢀ
Example:
Given: IDH:IDL0 = 8023h, R0 = 56h, R1 = 01h
ꢀ
SWAP
SWAP
R1, IDH
// R1 ← 80h, IDH ← 01h
// R0 ← 23h, IDL0 ← 56h
R0, IDL0
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After execution of instructions, index registers IDH:IDL0 (ID0) have address 0156h.
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ꢑꢒꢘꢕꢀ
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ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢂ!ꢂꢀꢁꢀꢒꢋꢎꢆꢏꢜꢀ
Format:
SYS #imm:8
Operation:ꢀ
Flags:
SYS generates SYSCP[7:0] and nSYSID signals.
–
ꢋꢏꢌꢐꢔꢀ ꢀ
Mainly used for system peripheral interfacing.ꢀ
Example:
SYS
SYS
#0Ah
#05h
In the first example, statement “SYS #0Ah” is equal to STOP instruction and second example “SYS
#05h” is equal to IDLE instruction. This instruction does nothing but increase PC by one and
generates SYSCP[7:0] and nSYSID signals.
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ꢑꢒꢘꢆꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢃꢏꢀꢁꢀꢞꢏꢎꢆꢀ4$ꢙꢆꢅꢝꢙꢏꢀꢌꢅꢆꢎꢀ
Format:
TM <op>, #imm:8
<op>: GPR
Operation:ꢀ
TM performs the bit-wise AND operation on <op> and imm:8 and sets the flags. The content of
<op> is not changed.
Flags:
Z: set if result is zero. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: R0 = 01001101b
ꢀ
TM
R0, #00100010b
// Z flag is set to ‘1’
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ꢑꢒꢘꢖꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢉ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
"ꢇꢄꢀꢁꢀ-5ꢚꢙ$ꢎꢅ3ꢏꢀ.ꢓꢀ
Format:
XOR <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:ꢀ
<op1> ← <op1> ^ <op2>
ꢀ
XOR performs the bit-wise exclusive-OR operation on <op1> and <op2> and stores the result in
<op1>.
Flags:
Z: set if result is zero. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 8080h, DM[8043h] = 26h, R0 = 52h, R1 = 14h, eid = 1
ꢀ
ꢀ
XOR
XOR
XOR
R0, 43h
R1, #00101100b
R0, R1
// R0 ← 74h
// R1 ← 38h
// R0 ← 46h
XOR
XOR
XOR
XOR
R0, @ID0
// R0 ← R0 ^ DM[8080h], IDL0 ← 81h
// R0 ← R0 ^ DM[807Eh], IDL0 ← 7Eh
// R0 ← R0 ^ DM[8083h], IDL0 ← 80h
// R0 ← R0 ^ DM[807Bh], IDL0 ← 80h
R0, @[ID0-2]
R0, @[ID0+3]!
R0, @[ID0-5]!
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2ꢅꢂꢋꢚꢔꢂꢈꢇꢊꢋꢂꢋAꢏꢂꢄꢅꢊꢋꢌꢍꢎꢋꢄꢏꢅꢊꢞꢂꢋꢚꢔꢂꢆꢇꢈꢍꢔꢂꢏ(ꢂ2ꢝ472ꢝ3<ꢂꢄꢊꢂꢅꢏꢋꢂꢎꢚꢇꢅ/ꢔꢉꢐꢂ&ꢔ(ꢔꢌꢂꢋꢏꢂꢙꢇꢖꢈꢔꢂ ꢃ8ꢂ(ꢏꢌꢂꢓꢏꢌꢔꢂꢉꢔꢋꢇꢄꢈꢔꢉꢂ
ꢔꢒꢕꢈꢇꢅꢇꢋꢄꢏꢅꢂꢇꢖꢏꢍꢋꢂꢋꢚꢄꢊꢂꢇꢉꢉꢌꢔꢊꢊꢄꢅ/ꢂꢓꢏꢉꢔꢐꢂꢂ
ꢄꢉꢓꢂKꢂ2ꢝꢒ>ꢏ((ꢊꢔꢋ78ꢞꢂ62ꢝꢒꢃꢏ((ꢊꢔꢋ789ꢞꢂ62ꢝꢒ>ꢏ((ꢊꢔꢋ789:ꢞꢂ62ꢝꢒꢃꢏ((ꢊꢔꢋ789:ꢂ#2ꢝꢒꢂKꢂ2ꢝ<ꢂꢏꢌꢂ2ꢝꢗ'ꢂ
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ꢑꢒꢘꢑꢀ
ꢊꢋꢀꢌꢍꢎꢂꢌꢊꢏꢋꢉꢀꢐꢌꢉ
ꢉ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢄꢅꢆꢉ
ꢐ.ꢞ-ꢒꢀ
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ꢑꢒꢘꢗꢀ
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相关型号：
S3CB519XX-QX
RISC Microcontroller, 8-Bit, MROM, 10.24MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100
SAMSUNG
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