S3CB519 [SAMSUNG]
8-Bit CMOS Microcontroller; 8位CMOS微控制器
| 型号： | S3CB519 |
| 厂家： | 
SAMSUNG |
| 描述： | 8-Bit CMOS Microcontroller |
| 文件： | 总302页 (文件大小：933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
22-S3-CB519-032004
USER'S MANUAL
S3CB519
8-Bit CMOS
Microcontroller
Revision 2
S3CB519
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 2
Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims,
costs, damages, expenses, and reasonable attorney
fees arising out of, either directly or indirectly, any
claim of personal injury or death that may be
associated with such unintended or unauthorized use,
even if such claim alleges that Samsung was
negligent regarding the design or manufacture of said
product.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of any
product or circuit and specifically disclaims any and
all liability, including without limitation any
consequential or incidental damages.
S3CB519 8-Bit CMOS Microcontrollers
User's Manual, Revision 2
Publication Number: 22-S3-CB519-042004
© 2004 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any
form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written
consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are
designed and manufactured in accordance with the highest quality standards and
objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup
Yongin-City, Kyunggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
TEL: (82)-(331)-209-1907
FAX: (82)-(331)-209-1899
Home-Page URL: Http://www.samsungsemi.com
Printed in the Republic of Korea
Preface
The S3CB519 Microcontroller User's Manual is designed for application designers and programmers who are using
the S3CB519 microcontroller for application development. It is organized in two main parts:
Part I Programming Model
Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture, programming
model, instruction set, and interrupt structure. It has nine chapters:
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Product Overview
Address Spaces
Registers
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Hardware Stack
Exceptions
Coprocessor Interface
Instruction Set
Memory Map
Chapter 1, "Product Overview," is a high-level introduction to S3CB519 with general product descriptions, as well as
detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," describes program and data memory spaces. Chapter 2 also describes ROM code
option.
Chapter 3, "Register," describes the special registers.
Chapter 4, "Memory Map," describes the internal register file.
Chapter 5, "Hardware Stack," describes the S3CB519 hardware stack structure in detail.
Chapter 6, "Exceptions," describes the S3CB519 exception structure in detail.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part
II. If you are not yet familiar with the S3CB-series microcontroller family and are reading this manual for the first time,
we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed information in Chapters
4, 5, 6, 7, 8, and 9. Later, you can reference the information in Part I as necessary.
Part II "Hardware descriptions," has detailed information about specific hardware components of the S3CB519
microcontroller. Also included in Part II are electrical, mechanical. It has 16 chapters:
Chapter 9
Clock Circuit
nRESET and Power-Down
I/O Ports
Basic Timer/Watchdog Timer
Watch Timer
16-Bit Timer (8-Bit Timer A & B)
8-Bit Timer (Timer 0)
Serial I/O Interface
Battery Level Detector
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23
Chapter 24
LCD Controller/Driver
A/D Converter
D/A Converter
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
Chapter 16
Chapter 17
MAC 816
Electrical Data
Mechanical Data
Development Tools
Chapter 21, “MAC816” describes the MAC816 structure in detail, as well as instructions.
Two order forms are included at the back of this manual to facilitate customer order for S3CB519 microcontrollers:
the Mask ROM Order Form, and the Mask Option Selection Form.
You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.
S3CB519 MICROCONTROLLER
iii
Table of Contents
Part I — Programming Model
Chapter 1
Product Overview
Overview.............................................................................................................................................1-1
Features.............................................................................................................................................1-5
Pin Assignment...................................................................................................................................1-7
I/O Pin Description ..............................................................................................................................1-8
Pin Circuit Diagrams............................................................................................................................1-10
Chapter 2
Address Spaces
Overview.............................................................................................................................................2-1
Program Memory (ROM)......................................................................................................................2-2
ROM Code Option (RCOD_OPT)...........................................................................................................2-5
Data Memory Organization...................................................................................................................2-7
Chapter 3
Registers
Overview.............................................................................................................................................3-1
Index Registers: IDH, IDL0 and IDL1..............................................................................................3-2
Link Registers: ILX, ILH and ILL ....................................................................................................3-2
Status Register 0: SR0................................................................................................................3-3
Status Register 1: SR1................................................................................................................3-4
Chapter 4
Memory Map
Overview.............................................................................................................................................4-1
Chapter 5
Hardware Stack
Overview.............................................................................................................................................5-1
S3CB519 MICROCONTROLLER
v
Table of Contents (Continued)
Chapter 6
Exceptions
Overview.............................................................................................................................................6-1
Hardware Reset...........................................................................................................................6-1
NMI Exception (Edge Sensitive)....................................................................................................6-2
IRQ[0] Exception (Level-Sensitive).................................................................................................6-2
IRQ[1] Exception (Level-Sensitive).................................................................................................6-2
Hardware Stack Full Exception.....................................................................................................6-2
Break Exception..........................................................................................................................6-2
Exceptions (or Interrupts).............................................................................................................6-3
Interrupt Mask Registers ..............................................................................................................6-5
Interrupt Priority Register..............................................................................................................6-6
Chapter 7
Coprocessor Interface
Overview.............................................................................................................................................7-1
Chapter 8
Instruction Set
Overview.............................................................................................................................................8-1
Glossary.....................................................................................................................................8-1
Instruction Set Map .............................................................................................................................8-2
Quick Reference..................................................................................................................................8-9
Instruction Group Summary..................................................................................................................8-12
ALU Instructions..........................................................................................................................8-12
Shift/Rotate Instructions...............................................................................................................8-16
Load Instructions.........................................................................................................................8-18
Branch Instructions......................................................................................................................8-21
Bit Manipulation Instructions.........................................................................................................8-25
Miscellaneous Instruction.............................................................................................................8-26
Pseudo Instructions.............................................................................................................................8-29
vi
S3CB519 MICROCONTROLLER
Table of Contents (Continued)
Part II Hardware Descriptions
Chapter 9
Clock Circuit
Overview.............................................................................................................................................9-1
System Clock Circuit...................................................................................................................9-1
Chapter 10
nRESET and Power-Down
Overview.............................................................................................................................................10-1
Chapter 11
I/O Ports
Overview.............................................................................................................................................11-1
Port 0.........................................................................................................................................11-1
Port 1.........................................................................................................................................11-4
Port 2.........................................................................................................................................11-5
Port 3.........................................................................................................................................11-5
Port 4.........................................................................................................................................11-6
Port 5.........................................................................................................................................11-7
Chapter 12
Basic Timer
Overview.............................................................................................................................................12-1
Block Diagram ....................................................................................................................................12-2
Chapter 13
Watch Timer
Overview.............................................................................................................................................13-1
Watch Timer Circuit Diagram........................................................................................................13-2
Chapter 14
16-Bit Timer (8-Bit Timer A & B)
Overview.............................................................................................................................................14-1
Interval timer function...................................................................................................................14-1
S3CB519 MICROCONTROLLER
vii
Table of Contents (Continued)
Chapter 15
8-Bit Timer (Timer 0)
Overview.........................................................................................................................................15-1
Function Description........................................................................................................................15-2
Timer 0 Control Register (T0CON).....................................................................................................15-3
Block Diagram ................................................................................................................................15-4
Chapter 16
Serial I/O Interface
Overview.............................................................................................................................................16-1
Programming Procedure...............................................................................................................16-1
SIO Control Register (SIOCON) ....................................................................................................16-2
SIO Pre-Scaler Register (SIOPS)..................................................................................................16-3
Block Diagram ....................................................................................................................................16-3
Serial I/O Timing Diagrams...........................................................................................................16-4
Chapter 17
Battery Level Detector
Overview.............................................................................................................................................17-1
Chapter 18
LCD Controller/Driver
Overview.............................................................................................................................................18-1
LCD RAM Address Area ..............................................................................................................18-1
LCD RAM (RAM Bank 12)............................................................................................................18-1
LCD Control Register (LCON) .......................................................................................................18-2
LCD Voltage Dividing Resistors.....................................................................................................18-2
LCD Mode Register (LMOD).........................................................................................................18-3
LCD Contrast Control Register (LCNST).........................................................................................18-4
LCD Key Scan............................................................................................................................18-8
Chapter 19
A/D Converter
Overview.............................................................................................................................................19-1
Features.............................................................................................................................................19-1
A/D Converter Control Register (ADCON).......................................................................................19-2
Chapter 20
D/A Converter
Overview.............................................................................................................................................20-1
D/A Converter Data Register (DADATA).........................................................................................20-3
D/A Converter Control Register (DACON).......................................................................................20-3
viii
S3CB519 MICROCONTROLLER
Table of Contents (Concluded)
Chapter 21
MAC816
MAC816 Architecture Overview.............................................................................................................21-1
Programmer’s Model............................................................................................................................21-3
Data Memory Accesses...............................................................................................................21-3
Computation Unit.........................................................................................................................21-7
Status Registers .........................................................................................................................21-9
Host Interface..............................................................................................................................21-11
Instruction Set.....................................................................................................................................21-14
Glossary.....................................................................................................................................21-14
Instruction Encoding....................................................................................................................21-20
Quick Reference..........................................................................................................................21-22
MAC816 Instruction Description....................................................................................................21-25
Chapter 22
Electrical Data
Overview............................................................................................................................................22-1
Chapter 23
Mechanical Data
Overview.............................................................................................................................................23-1
Chapter 24
Development Tools
Overview.............................................................................................................................................24-1
CALMSHINE: IDE(Integrated Development Environment).....................................................................24-1
Invisible MDS: In-Circuit Emulator .....................................................................................................24-1
CALMRISC8 C-Compiler: CALM8CC.................................................................................................24-1
CALMRISC8 Relocatable Assembler: CALM8ASM.............................................................................24-1
CALMRISC8 Linker: CALM8LINK......................................................................................................24-1
Emulation Probe Board Configuration ....................................................................................................24-2
External Event Input Headers (JP4)...................................................................................................24-3
Event Match Output Headers (JP9) ...................................................................................................24-3
External Break Input Headers (TP4) ..................................................................................................24-3
A/D Converter Function Block...............................................................................................................24-4
Communication Selection.................................................................................................................24-5
Use Clock Setting for External Clock Mode........................................................................................24-5
Sub Clock Setting ...........................................................................................................................24-5
CN1, CN2 Pin Assignment ...............................................................................................................24-6
S3CB519 MICROCONTROLLER
ix
List of Figures
Figure
Title
Page
Number
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
Top Block Diagram..............................................................................................1-2
CalmRISC Pipeline Diagram.................................................................................1-3
CalmRISC Pipeline Stream Diagram......................................................................1-4
S3CB519 Block Diagram......................................................................................1-6
S3CB519 Pin Assignment Diagram (100-QFP).......................................................1-7
S3CB519 Pin Assignment Diagram (100-TQFP).....................................................1-8
Pin Circuit Type B ...............................................................................................1-11
Pin Circuit Type C...............................................................................................1-11
Pin Circuit Type E-2.............................................................................................1-11
Pin Circuit Type D-2.............................................................................................1-11
Pin Circuit Type H-29...........................................................................................1-12
Pin Circuit Type H-35...........................................................................................1-12
Pin Circuit Type H-34...........................................................................................1-12
Pin Circuit Type F-10...........................................................................................1-12
1-9
1-10
1-11
1-12
1-13
1-14
2-1
2-2
2-3
2-4
2-5
2-6
Program Memory Address Space.........................................................................2-2
Relative Jump Around Page Boundary ...................................................................2-3
Program Memory Layout......................................................................................2-4
ROM Code Option (RCOD_OPT)...........................................................................2-6
Data Memory Map...............................................................................................2-7
S3CB519 Data Memory Map................................................................................2-8
3-1
4-1
Bank Selection by Setting of GRB Bits and IDB Bit................................................3-3
Control Register Area...........................................................................................4-1
5-1
5-2
5-3
5-4
5-5
Hardware Stack...................................................................................................5-1
Even and Odd Bank Selection Example.................................................................5-2
Stack Operation with PC [19:0].............................................................................5-3
Stack Operation with Registers.............................................................................5-4
Stack Overflow....................................................................................................5-5
S3CB519 MICROCONTROLLER
xi
List of Figures (Continued)
Figure
Title
Page
Number
Number
6-1
6-2
6-3
6-4
Interrupt Structure................................................................................................6-3
Interrupt Structure................................................................................................6-4
Interrupt Mask Register........................................................................................6-5
Interrupt Priority Register......................................................................................6-6
7-1
7-2
Coprocessor Interface Diagram.............................................................................7-1
Coprocessor Instruction Pipeline...........................................................................7-3
9-1
9-2
9-3
System Clock Circuit Diagram..............................................................................9-2
Power Control Register (PCON)............................................................................9-3
Oscillator Control Register (OSCCON)...................................................................9-3
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
Port 0 Low-byte Control Register (P0CONL)...........................................................11-1
Port 0 High-byte Control Register (P0CONH)..........................................................11-2
Port 0 Interrupt Control Register (P0INT) ................................................................11-2
Port 0 Interrupt Edge Control Register (P0EDGE)...................................................11-3
Port 1 Control Register (P1CON)...........................................................................11-4
Port 1 Interrupt Control Register (P1INT) ................................................................11-4
Port 2 Control Register (P2CON)...........................................................................11-5
Port 3 Control Register (P3CON)...........................................................................11-5
Port 4 Control Register (P4CON)...........................................................................11-6
Port 5 Control Register (P5CON)...........................................................................11-7
12-1
12-2
Watchdog Timer Control Register (WDTCON) ........................................................12-1
Basic Timer & Watchdog Timer Functional Block Diagram......................................12-2
13-1
Watch Timer Circuit Diagram................................................................................13-2
14-1
14-2
14-3
Timer A Control Register (TACON)........................................................................14-1
Timer B Control Register (TBCON)........................................................................14-2
Timer A, B Function Block Diagram ......................................................................14-3
15-1
15-2
Timer 0 Control Register (T0CON).........................................................................15-3
Timer 0 Functional Block Diagram.........................................................................15-4
16-1
16-2
16-3
16-4
16-5
Serial I/O Control Register (SIOCON) ....................................................................16-2
SIO Pre-scaler Register (SIOPS)..........................................................................16-3
SIO Functional Block Diagram..............................................................................16-3
Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0).................16-4
Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) .................16-4
17-1
17-2
Voltage Level Detection Circuit .............................................................................17-1
Battery Level Detector Control Register (BLDCON).................................................17-2
xii
S3CB519 MICROCONTROLLER
List of Figures (Concluded)
Figure
Title
Page
Number
Number
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
LCD Display Data RAM Organization ....................................................................18-1
LCD Control Register (LCON) ...............................................................................18-2
Internal Voltage Dividing Resistor Connection.........................................................18-2
LCD Mode Register (LMOD).................................................................................18-3
LCD Contrast Register (LCNST)............................................................................18-4
LCD Signal Waveforms (1/16 Duty, 1/5 Bias) .........................................................18-5
LCD Signal Waveforms (1/8 Duty, 1/4 Bias)...........................................................18-7
LCD Waveform when Key Strobe Signal is Active ...................................................18-9
19-1
19-2
19-3
A/DC Control Register (ADCON)...........................................................................19-2
A/D Converter Block Diagram ...............................................................................19-3
Application Example............................................................................................19-4
20-1
20-2
20-3
D/A Converter Circuit Diagram ..............................................................................20-1
D/A Converter Timing Diagram..............................................................................20-2
D/A Control Register (DACON) .............................................................................20-3
21-1
21-2
21-3
21-4
21-5
21-6
Top Block Diagram..............................................................................................21-1
Data Memory Organization...................................................................................21-3
RPU (RAM Pointer Unit) Block Diagram ................................................................21-4
Computation Unit Block Diagram ..........................................................................21-7
Coprocessor Interface Diagram.............................................................................21-11
Coprocessor Instruction Pipeline...........................................................................21-13
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
Input Timing for External Interrupts (Port 0, Port 1)..................................................22-4
Input Timing for nRESET......................................................................................22-4
Stop Mode Release Timing When Initiated by a nRESET........................................22-5
Stop Mode(Main) Release Timing Initiated by Interrupts ..........................................22-6
Stop Mode(Sub) Release Timing Initiated by Interrupts............................................22-6
Serial Data Transfer Timing...................................................................................22-7
Clock Timing Measurement at XIN .........................................................................22-11
Operating Voltage Range .....................................................................................22-12
23-1
23-2
100-QFP-1420C Package Dimensions...................................................................23-2
100-TQFP-1414 Package Dimensions ...................................................................23-3
24-1
24-2
Emulation Probe Board Configuration ....................................................................24-2
A/D converter Function Block Diagram ..................................................................24-4
S3CB519 MICROCONTROLLER
xiii
List of Tables
Table
Title
Page
Number
Number
1-1
S3CB519 Pin Descriptions ...................................................................................1-9
3-1
3-2
3-3
General and Special Purpose Registers.................................................................3-1
Status Register 0 Configuration.............................................................................3-3
Status Register 1: SR1........................................................................................3-4
4-1
Control Registers.................................................................................................4-2
6-1
7-1
Exceptions .........................................................................................................6-1
Coprocessor instructions......................................................................................7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
Instruction Notation Conventions ...........................................................................8-1
Overall Instruction Set Map...................................................................................8-2
Instruction Encoding............................................................................................8-4
Index Code Information (“idx”) ...............................................................................8-7
Index Modification Code Information (“mod”)...........................................................8-7
Condition Code Information (“cc”) ..........................................................................8-7
“ALUop1” Code Information...................................................................................8-8
“ALUop2” Code Information...................................................................................8-8
“MODop1” Code Information..................................................................................8-8
13-1
Watch Timer Control Register (WTCON): 8-Bit R/W................................................13-1
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
RPU(RAM Pointer Unit) Registers.........................................................................21-4
RPi register bit information ...................................................................................21-5
Coprocessor instructions......................................................................................21-12
Notation and Convention.......................................................................................21-14
MAC816 Registers ..............................................................................................21-15
Data Transfer Registers........................................................................................21-16
Memory Access Mode Information........................................................................21-17
Condition Code Information...................................................................................21-18
Control Bit Code Information.................................................................................21-18
AU operation code information..............................................................................21-19
Others................................................................................................................21-19
Instruction Encoding............................................................................................21-20
Quick Reference..................................................................................................21-22
S3CB519 MICROCONTROLLER
xv
List of Tables (Continued)
Table
Title
Page
Number
Number
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
Absolute Maximum Ratings..................................................................................22-1
D.C. Electrical Characteristics..............................................................................22-1
A.C. Electrical Characteristics..............................................................................22-4
Data Retention Supply Voltage in Stop Mode.........................................................22-5
Synchronous SIO Electrical Characteristics...........................................................22-7
BLD Electrical Characteristics..............................................................................22-8
ADC Electrical Characteristics..............................................................................22-8
DAC Electrical Characteristics..............................................................................22-9
Main Oscillator Frequency (f
).........................................................................22-10
OSC1
22-10
22-11
22-12
Main Oscillator Clock Stabilization Time (T ) ......................................................22-10
ST1
Sub Oscillator Frequency (f
)..........................................................................22-11
OSC2
Sub Oscillator(Crystal) Start up Time (t
)............................................................22-11
ST2
xvi
S3CB519 MICROCONTROLLER
List of Programming Tips
Description
Chapter 2:
Page
Number
Address Space
Using the Page Pointer for RAM clear (Page 0, Page 1)......................................................................2-5
Setting the Register Pointers............................................................................................................2-9
Using the RPs to Calculate the Sum of a Series of Registers ..............................................................2-10
Addressing the Common Working Register Area................................................................................2-14
Standard Stack Operations Using PUSH and POP.............................................................................2-19
Chapter 6:
Exceptions
Interrupt Programming Tip 1..............................................................................................................6-7
Interrupt Programming Tip 2..............................................................................................................6-8
S3CB519 MICROCONTROLLER
xvii
List of Instruction Descriptions
Instruction
Mnemonic
Full Register Name
Page
Number
ADC
Add with Carry ....................................................................................................8-30
Add....................................................................................................................8-31
Bit-wise AND ......................................................................................................8-32
Bit-wise AND with SR0Call Procedure...................................................................8-33
Bank Selection....................................................................................................8-34
Bit Complement ..................................................................................................8-35
Bit Reset ............................................................................................................8-36
Bit Set................................................................................................................8-37
Bit Test ..............................................................................................................8-38
TF bit clear/set....................................................................................................8-39
Conditional subroutine call (Pseudo Instruction) .....................................................8-40
Call Subroutine....................................................................................................8-41
Load into Coprocessor.........................................................................................8-42
Load from Coprocessor........................................................................................8-43
1's or Bit-wise Complement ..................................................................................8-44
2's Complement ..................................................................................................8-45
Bit-wise Complement with Carry ...........................................................................8-46
Coprocessor .......................................................................................................8-47
Compare.............................................................................................................8-48
Compare with Carry .............................................................................................8-49
Decrement..........................................................................................................8-50
Decrement with Carry ..........................................................................................8-51
Disable Interrupt (Pseudo Instruction)....................................................................8-52
Enable Interrupt (Pseudo Instruction) ....................................................................8-53
Idle Operation (Pseudo Instruction) .......................................................................8-54
Increment ...........................................................................................................8-55
Increment with Carry............................................................................................8-56
Return from Interrupt Handling...............................................................................8-57
Jump Not Zero with Delay Slot..............................................................................8-58
Conditional Jump (Pseudo Instruction) ..................................................................8-59
Conditional Jump Relative.....................................................................................8-60
Conditional Subroutine Call...................................................................................8-61
Load into Memory................................................................................................8-62
ADD
AND
AND SR0
BANK
BITC
BITR
BITS
BITT
BMC/BMS
CALL
CALLS
CLD
CLD
COM
COM2
COMC
COP
CP
CPC
DEC
DECC
DI
EI
IDLE
INC
INCC
IRET
JNZD
JP
JR
LCALL
LD adr:8
S3CB519 MICROCONTROLLER
xix
List of Instruction Descriptions (Continued)
Instruction
Mnemonic
Full Instruction Name
Page
Number
LD @idm
LD
Load into Memory Indexed ...................................................................................8-63
Load Register......................................................................................................8-64
Load GPR:bankd, GPR:banks..............................................................................8-65
Load GPR, TBH/TBL............................................................................................8-66
Load TBH/TBL, GPR............................................................................................8-67
Load SPR...........................................................................................................8-68
Load SPR0 Immediate.........................................................................................8-69
Load Code..........................................................................................................8-70
Conditional Jump.................................................................................................8-71
Linked Subroutine Call Conditional........................................................................8-72
Linked Subroutine Call (Pseudo Instruction) ..........................................................8-73
Linked Subroutine Call.........................................................................................8-74
Return from Linked Subroutine Call .......................................................................8-75
No Operation.......................................................................................................8-76
Bit-wise OR ........................................................................................................8-77
Bit-wise OR with SR0 ..........................................................................................8-78
POP...................................................................................................................8-79
POP to Register..................................................................................................8-80
Push Register.....................................................................................................8-81
Return from Subroutine ........................................................................................8-82
Rotate Left..........................................................................................................8-83
Rotate Left with Carry ..........................................................................................8-84
Rotate Right........................................................................................................8-85
Rotate Right with Carry ........................................................................................8-86
Subtract with Carry..............................................................................................8-87
Shift Left.............................................................................................................8-88
Shift Left Arithmetic.............................................................................................8-89
Shift Right...........................................................................................................8-90
Shift Right Arithmetic...........................................................................................8-91
Stop Operation (Pseudo Instruction) .....................................................................8-92
Subtract .............................................................................................................8-93
Swap..................................................................................................................8-94
System ..............................................................................................................8-95
Test Multiple Bits ................................................................................................8-96
Exclusive OR......................................................................................................8-97
LD
LD
LD
LD SPR
LD SPR0
LDC
LJP
LLNK
LNK
LNKS
LRET
NOP
OR
OR SR0
POP
POP
PUSH
RET
RL
RLC
RR
RRC
SBC
SL
SLA
SR
SRA
STOP
SUB
SWAP
SYS
TM
XOR
xx
S3CB519 MICROCONTROLLER
S3CB519
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3CB519 single-chip CMOS microcontroller is designed for high performance using Samsung’s new
8-bit CPU core, CalmRISC.
CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has
separate program memory and data memory. Both instruction and data can be fetched simultaneously without
causing a stall, using separate paths for memory access. Represented below is the top block diagram of the
CalmRISC microcontroller.
1-1
PRODUCT OVERVIEW
S3CB519
20
PA[19:0]
PD[15:0]
Program Memory Address
Generation Unit
PC[19:0]
20
8
8
HS[0]
Hardware
Stack
HS[15]
TBH TBL
DO[7:0]
ABUS[7:0]
BBUS[7:0]
DI[7:0]
R0
R1
R2
R3
ALUL
ALUR
Flag
ALU
GPR
RBUS
SR1
ILH
SR0
ILL
ILX
IDL0
IDL1
Data Memory
Address
Generation Unit
DA[15:0]
IDH
SPR
Figure 1-1. Top Block Diagram
1-2
S3CB519
PRODUCT OVERVIEW
The CalmRISC building blocks consist of:
— An 8-bit ALU
— 16 general purpose registers (GPR)
— 11 special purpose registers (SPR)
— 16-level hardware stack
— Program memory address generation unit
— Data memory address generation unit
Sixteen GPRs are grouped into four banks (Bank0 to Bank3), and each bank has four 8-bit registers (R0, R1, R2,
and R3). SPRs, designed for special purposes, include status registers, link registers for branch-link instructions,
and data memory index registers. The data memory address generation unit provides the data memory address
(denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are
accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address
generation unit contains a program counter, PC[19:0], and supplies the program memory address through PA[19:0]
and fetches the corresponding instruction through PD[15:0] as the result of the program memory access. CalmRISC
has a 16-level hardware stack for low power stack operations as well as a temporary storage area.
Instruction Decode/
Data Memory Access
Instruction Fetch
(IF)
Execution/Writeback
(EXE/WB)
(ID/MEM)
Figure 1-2. CalmRISC Pipeline Diagram
CalmRISC has a 3-stage pipeline as described below:
As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data
memory where R is a GPR can be one operand of an ALU instruction as shown below:
The first stage (or cycle) is the Instruction fetch stage (IF for short), where the instruction pointed by the program
counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is the Instruction Decode
and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data
memory access is performed, if necessary. The final stage is the Execute and Write-back stage (EXE/WB), where
the required ALU operation is executed and the result is written back into the destination registers.
Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction is
completely finished but is performed immediately after completing the current instruction fetch. The pipeline stream
of instructions is illustrated in the following diagram.
1-3
PRODUCT OVERVIEW
S3CB519
/ 1
IF
/ 2
ID/MEM EXE/WB
IF ID/MEM EXE/WB
/ 3 IF ID/MEM EXE/WB
/ 4 IF IF
/ 5
ID/MEM EXE/WB
IF ID/MEM EXE/WB
/ 6 IF ID/MEM EXE/WB
Figure 1-3. CalmRISC Pipeline Stream Diagram
Most CalmRISC instructions are 1-word instructions, while same branch instructions such as long “call” and “jp”
instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction, and it takes two
clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction (CPI)
is 1 except for long branches, which take 2 clock cycles per instruction.
1-4
S3CB519
PRODUCT OVERVIEW
FEATURES
CPU
·
·
·
8, 12 and 16 COM selectable
16-level contrast control
·
8-bit CalmRISC
Key strobe output function
Coprocessor
Battery Level Detector
·
·
·
MAC 816
·
·
2.4, 2.7, 3.0, 3.3, 4.0, 4.5 V detectable
Internal level and/or external level selectable
8 ´ 16, 16 ´ 16 multiply and accumulation
Arithmetic operation
8-Bit Serial I/O Interface
Memory
·
·
·
8-bit transmit/receive mode
·
·
ROM: 16K-word
RAM: 3K-byte
2048 (X-memory)
1024 (Y-memory)
8-bit receive mode
LSB-first or MSB-first transmission selectable
A/D Converter
I/O Pins
·
·
·
·
Sigma delta ADC
·
·
11 I/O: not include COM/SEG
35 I/O: include COM/SEG
Linear 14-bit data (16-bit format)
256X over sampling
Power-Down
Operation voltage: V = 3.0 V–5.5 V
DD
·
·
·
Idle mode: only CPU clock stops
D/A Converter
Stop mode: main system oscillator stops
Sub-system clock stop mode
·
·
·
8-bit resolution
Regulated output voltage
ROM Option
Operation voltage: V = 2.4 V–5.5 V
DD
·
Basic timer counter clock source selection reset
Oscillation Sources
value
·
Watchdog timer enable/disable selection
·
·
·
·
Crystal, ceramic, RC for main system clock
Crystal or external oscillator for subsystem clock
Main system clock frequency: Max 8.2 MHz
Subsystem clock frequency: 32.768 kHz
8-Bit Basic Timer
·
·
Programmable interval timer
8 kinds of clock source
Operating Voltage
2.2 V to 5.5 V
Watchdog Timer
System reset
·
·
Operating Temperature Range
– 25 °C to 85 °C
Watch Timer
·
·
·
Real time clock or interval time measurement
Buzzer function (0.5/1/2/4 kHz at 4.19 MHz OSC)
Package Type
100-QFP-1420C, 100-TQFP-1414
Timer/Counters
·
·
·
One 8-bit timer with PWM/Capture
One 16-bit general-purpose timer/counter
LCD Controller/Driver
56 SEG ´ 16 COM terminals
·
1-5
PRODUCT OVERVIEW
S3CB519
X
IN
X
OUT
XTIN XTOUT
SUB OSC
Basic
Timer
Main OSC
WDT
SI
SIO
S0
SCK
Port 5
P5.0-P5.15
P4.0-P4.7
P3.0-P3.7
P2.0-P2.7
P1.0-P1.3
P0.0-P0.6
CalmRISC
CPU
T0/T0CAP/
T0PWM
T0CK
Timer 0
Port 4
Port 3
Port 2
Port 1
Port 0
Timer A
Timer B
TACK
TB
Watch
Timer
BUZ
BLD
X-Memory
2048 Bytes
Y-Memory
1024 Bytes
Control
Register
128 Bytes
BLD
AVDD
AVSS
MAC
816
ADINP
ADINN
ADGAIN
DAOUT
AVREFOUT
REFH
CODEC
REFL
COM0-COM15
SEG0-SEG55
LCD Driver/Controller
Figure 1-4. S3CB519 Block Diagram
1-6
S3CB519
PRODUCT OVERVIEW
PIN ASSIGNMENT
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
COM9/P4.1
COM10/P4.2
COM11/P4.3
COM12/P4.4
COM13/P4.5
COM14/P4.6
COM15/P4.7
P0.0/INT0/TB
1
2
3
4
5
6
7
8
P0.1/INT1/T0/T0CAP/T0PWM
P0.2/INT2/T0CK/BUZ
P0.3/INT3/TACK/BLD
P0.4/INT4/nSCK
P0.5/INT5/SO
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG23
SEG24/P5.15
SEG25/P5.14
SEG26/P5.13
SEG27/P5.12
SEG28/P5.11
SEG29/P5.10
SEG30/P5.9
SEG31/P5.8
SEG32/P5.7
SEG33/P5.6
SEG34/P5.5
SEG35/P5.4
SEG36/P5.3
SEG37/P5.2
SEG38/P5.1
SEG39/P5.0
SEG40/P3.7
P0.6/INT6/SI
V
DD
SS
OUT
IN
V
X
X
TEST
XTIN
XTOUT
nRESET
DAOUT
AVDD
AVSS
ADINP
ADINN
ADGAIN
AVREFOUT
REFH
Figure 1-5. S3CB519 Pin Assignment Diagram (100-QFP)
1-7
PRODUCT OVERVIEW
S3CB519
COM11/P4.3
COM12/P4.4
COM13/P4.5
COM14/P4.6
COM15/P4.7
P0.0/INT0/TB
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P5.15
SEG25/P5.14
SEG26/P5.13
SEG27/P5.12
SEG28/P5.11
SEG29/P5.10
SEG30/P5.9
SEG31/P5.8
SEG32/P5.7
SEG33/P5.6
SEG34/P5.5
SEG35/P5.4
SEG36/P5.3
SEG37/P5.2
SEG38/P5.1
P0.1/INT1/T0/T0CAP/T0PWM
P0.2/INT2/T0CK/BUZ
P0.3/INT3/TACK/BLD
P0.4/INT4/nSCK
P0.5/INT5/SO
P0.6/INT6/SI
VDD
9
10
11
(SDAT)
S3FB519
(100-TQFP-1414)
12 (SCLK)
13
14
15
16
17
18
19
20
21
22
23
24
VSS
XOUT
XIN
TEST
XTIN
XTOUT
nRESET
DAOUT
AVDD
AVSS
ADINP
ADINN
25
Figure 1-6. S3CB519 Pin Assignment Diagram (100-TQFP)
1-8
S3CB519
PRODUCT OVERVIEW
I/O PIN DESCRIPTION
Table 1-1. S3CB519 Pin Descriptions
Pin Description
Pin
Name
Pin
Type
Circuit
Type
Share
Pins
P0.0
P0.1
I/O
I/O port with bit programmable pins; Input and output modes
can be selected by software; Software assignable pull-up.
Alternately, P0.0–P0.6 can be used as INT0–INT6, TB, T0,
T0CAP, T0PWM, T0CK, BUZ, TACK, BLD, nSCK, SO, SI.
D-2
D-2
INT0/TB
INT1/T0/T0CAP/T
0PWM
INT2/T0CK/BUZ
INT3/TACK/BLD
INT4/nSCK
INT5/SO
P0.2
P0.3
P0.4
P0.5
P0.6
D-2
F-10
D-2
D-2
D-2
INT6/SI
P1.0–P1.3
I/O
I/O
I/O port with bit programmable pins; Input and output modes
can be selected by software; Software assignable pull-up.
Alternately, P1.0–P1.3 can be used as KS0–KS3.
D-2
KS0–KS3
P2.0–P2.7
I/O port with 4-bit programmable pins; Input and output
modes can be selected by software; Software assignable pull-
up.
H-35
SEG55–SEG48
Alternately, P2.0–P2.7 can be used as SEG55–SEG48.
P3.0–P3.7
P4.0–P4.7
P5.0–P5.15
I/O
I/O
O
I/O port with 4-bit programmable pins; Input and output
modes can be selected by software; Software assignable pull-
up.
H-35
H-35
H-34
SEG47–SEG40
COM8–COM15
SEG39–SEG24
Alternately, P3.0–P3.7 can be used as SEG47–SEG40.
I/O port with 4-bit programmable pins; Input and output
modes can be selected by software; Software assignable pull-
up.
Alternately, P4.0–P4.7 can be used as COM8–COM15.
Key strobe output port with 4-bit programmable pins. Push-pull
and open-drain modes can be selected by software.
Alternately, P5.0–P5.15 can be used as SEG39–SEG24.
SEG0–
SEG23
O
O
LCD segment signal output.
H-29
H-34
H-35
H-29
H-35
–
SEG24–
SEG39
P5.0–P5.15
SEG40–
SEG55
I/O
O
P3.0–P3.7
P2.0–P2.7
COM0–
COM7
LCD common signal output.
–
P4.0–P4.7
P1.0–P1.3
COM8–
COM15
O
KS0–KS3
I/O
I/O
Key interrupt and/or external interrupt inputs.
External interrupt input.
D-2
D-2
INT0–INT2,
INT4–INT6
P0.0–P0.2,
P0.4–P0.6
INT3
I/O
F-10
P0.3
1-9
PRODUCT OVERVIEW
S3CB519
Table 1-1. S3CB519 Pin Descriptions (Continued)
Pin Description
Pin
Name
Pin
Type
Circuit
Type
Share
Pins
TB
T0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Timer B clock output.
D-2
D-2
D-2
D-2
D-2
D-2
F-10
F-10
D-2
D-2
D-2
–
P0.0
P0.1
P0.1
P0.1
P0.2
P0.2
P0.3
P0.3
P0.4
P0.5
P0.6
Timer 0 clock output.
Timer 0 capture input.
Timer 0 PWM output.
Timer 0 clock input.
Buzzer output.
T0CAP
T0PWM
T0CK
BUZ
TACK
BLD
Timer A clock input.
Battery level detector input.
Serial I/O interface clock signal.
Serial data output.
nSCK
SO
SI
Serial data input.
DAOUT
DAC analog output.
Analog power.
–
–
AV
–
–
DD
AV
–
Analog ground.
–
–
SS
ADINP
I
I
Analog input positive.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADINN
Analog input negative.
ADGAIN
AVREFOUT
REFH
–
O
–
–
–
Analog input gain control.
Analog reference voltage output.
Analog reference power.
Analog reference ground.
Main power supply.
REFL
V
DD
V
–
–
–
I
Ground
–
–
–
–
–
–
–
–
SS
X , X
Crystal, Ceramic or RC oscillator pins for system clock.
Crystal oscillator pins for subsystem clock.
IN OUT
XT , XT
IN
OUT
TEST
Chip test input pin.
Hold GND with the device is operating.
nRESET
I
Reset signal
B
–
1-10
S3CB519
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
V
DD
Pull-up
Enable
Pull-Up
Resistor
Open drain
Enable
In
Data
Output
Figure 1-9. Pin Circuit Type E-2
Figure 1-7. Pin Circuit Type B
V
DD
V
DD
Pull-up
Enable
Data
Data
Pin Circuit
Type C
I/O
Out
Output
Disable
Output
Disable
Ext. INT
Input
Noise
Filter
Figure 1-10. Pin Circuit Type D-2
Figure 1-8. Pin Circuit Type C
1-11
PRODUCT OVERVIEW
S3CB519
VLC1
VDD
Open drain
enable
VLC2/VLC3
Output disable
Data
Output
Out
VLC4/VLC5
Pin Circuit
Type H-29
COM/SEG
VSS
Figure 1-11. Pin Circuit Type H-29
Figure 1-13. Pin Circuit Type H-34
V
DD
VDD
Pull-up
Enable
Data
Pin Circuit
Type E-2
Output
Data
Pin Circuit
Type C
Disable
I/O
Output
COM/SEG
Pin Circuit
Type H-29
Disable
I/O
Ext. INT
Noise
Filter
Input
Input
Analog
(BLD)
Figure 1-14. Pin Circuit Type F-10
Figure 1-12. Pin Circuit Type H-35
1-12
S3CB519
ADDRESS SPACE
2
ADDRESS SPACE
OVERVIEW
CalmRISC has 20-bit program address lines, PA[19:0], which support up to 1 Mwords of program memory.
The 1 Mword program memory space is divided into 256 pages, and each page is 4 Kwords long as shown on the
next page. The upper 8 bits of the program counter, PC[19:12], points to a specific page, and the lower 12 bits,
PC[11:0], specify the offset address of the page.
CalmRISC also has 16-bit data memory address lines, DA[15:0], which support up to 64K-byte of data memory. The
64K-byte data memory space is divided into 256 pages, and each page has 256 bytes. The upper 8 bits of the data
address, DA[15:8], points to a specific page, and the lower 8 bits, DA[7:0], specify the offset address of the page.
2-1
ADDRESS SPACE
S3CB519
PROGRAM MEMORY (ROM)
FFFH
1 Mword
FFFH
00H
4 Kword
256 page
00H
Figure 2-1. Program Memory Organization
For example, if PC[19:0] = 5F79AH, the page index pointed to by PC is 5FH, and the offset in the page is 79AH. If
the current PC[19:0] = 5EFFFH and the instruction pointed to by the current PC (i.e., the instruction at the address
5EFFFH is not a branch instruction), the next PC becomes 5E000H, not 5F000H. In other words, the instruction
sequence wraps around at the page boundary, unless the instruction at the boundary (in the above example, at
5EFFFH) is a long branch instruction. The only way to change the program page is by long branches (CALL, LNK,
and JP), where the absolute branch target address is specified. For example, if the current PC[19:0] = 047ACH (the
page index is 04H and the offset is 7ACH) and the instruction pointed to by the current PC (i.e., the instruction at the
address 047ACH), is “JP A507FH” (jump to the program address A507FH) , then the next PC[19:0] = A507FH,
which means that the page and the offset are changed to A5H and 07FH, respectively. On the other hand, the short
branch instructions cannot change the page indices.
2-2
S3CB519
ADDRESS SPACE
Suppose the current PC is 6FFFEH and its instruction is “JR 5H” (jump to the program address PC + 5H), then the
next instruction address is 6F003H, not 70003H. In other words, the branch target address calculation also wraps
around with respect to a page boundary. This situation is illustrated below:
Page 6FH
000H
001H
002H
003H
004H
005H
FFEH
FFFH
JR 5H
Figure 2-2. Relative Jump Around Page Boundary
Programmers do not have to manually calculate the offset and insert extra instructions for a jump instruction across
page boundaries. The compiler and the assembler for CalmRISC are in charge of producing appropriate codes for
them.
2-3
ADDRESS SPACE
S3CB519
FFFFFH
Program Memory Area
(1M-word)
~
~
~
~
4000H
3FFFH
16K-word
00020H
0001FH
Vector and
Option Area
00000H
NOTE: S3CB519 has totally 16K-word (32K-byte) program memory area.
Figure 2-3. Program Memory Layout
From 00000H to 00004H addresses are used for vector addresses of exceptions, and 0001EH and 0001FH are used
for only the option. Aside from these addresses others are reserved in the vector and option area. Program memory
area from the address 00020H to FFFFFH can be used for normal programs.
Because the S3CB519’s program memory is 16 Kword (32K-byte), the block of addresses from 00020H to 3FFFH is
the program memory area.
2-4
S3CB519
ADDRESS SPACE
ROM CODE OPTION (RCOD_OPT)
Just after power on, the ROM data located at 0001EH and 0001FH is used as the ROM code option.
S3CB519 has ROM code options like the Reset value of Basic timer and Watchdog timer enable.
For example, if you program as below:
opt_sec
section
opt_sec
dw
CODE, abs 0001FH
3FFH
— fxx/32 is used as Reset value of basic timer (by bit.14, 13, 12)
— Watch-dog timer is enabled (by bit.11)
If you don’t program any values in these option areas, then the default value is “1”.
In these cases, the address 0001EH would be the value of “FFFFH”.
2-5
ADDRESS SPACE
S3CB519
ROM_Code Option (RCOD_OPT)
ROM Address: 0001FH
MSB .15
.14
.13
.12
.11
.10
.9
.8
LSB
Not used
Reset value of basic timer
clock selection bits
(WDTCON.6, .5, .4):
000 = fxx/2
Not used
001 = fxx/4
010 = fxx/16
011 = fxx/32
Watchdog timer enable selection bit:
0 = Disable WDT
1 = Enable WDT
100 = fxx/128
101 = fxx/256
110 = fxx/1024
111 = fxx/2048
Not used (Watchdog timer clock input is basic timer overflow)
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Not used
ROM Address: 0001EH
.15
.7
.14
.6
.13
.12
.11
.10
.9
.1
.8
.0
MSB
MSB
LSB
LSB
Not used
.4 .3
.5
.2
Not used
Figure 2-4. ROM Code Option (RCOD_OPT)
2-6
S3CB519
ADDRESS SPACE
DATA MEMORY ORGANIZATION
The total data memory address space is 64K-byte, addressed by DA[15:0], and divided into 256 pages, Each page
consists of 256 bytes as shown below.
FFH
64 KByte
FFH
00H
256 Byte
256 page
00H
12 page
Figure 2-5. Data Memory Map
The data memory page is indexed by SPR and IDH. In data memory index addressing mode, 16-bit data memory
address is composed of two 8-bit SPRs, IDH[7:0] and IDL0[7:0] (or IDH[7:0] and IDL1[7:0]). IDH[7:0] points to a page
index, and IDL0[7:0] (or IDL1[7:0]) represents the page offset. In data memory direct addressing mode, an 8-bit direct
address, adr[7:0], specifies the offset of the page pointed to by IDH[7:0] (See the details for direct addressing mode
in the instruction sections). Unlike the program memory organization, data memory address does not wrap around.
In other words, data memory index addressing with modification performs an addition or a subtraction operation on
the whole 16-bit address of IDH[7:0] and IDL0[7:0] (or IDL1[7:0]) and updates IDH[7:0] and IDL0[7:0] (or IDL1[7:0])
accordingly. Suppose IDH[7:0] is 0FH and IDL0[7:0] is FCH and the modification on the index registers, IDH[7:0] and
IDL0[7:0], is increment by 5H, then, after the modification (i.e., 0FFCH + 5 = 1001H), IDH[7:0] and IDL0[7:0]
become 10H and 01H, respectively.
As for the MAC816 coprocessor, the data memory is a word unit (16-bit wide) and is divided to X-memory and Y-
memory for DSP instruction.
The address 0080H in CalmRISC, for example, is viewed as 0040H by MAC816.
2-7
ADDRESS SPACE
S3CB519
The S3CB519 has a total of 3072 bytes of data register address from 0080H to 0C7FH.
The area from 0000H to 007FH is for peripheral control, and LCD RAM area is from 0C80H to 0CEFH.
The MAC816 views the peripheral control register area as being from 0000H to 003FH, and X-memory from 0040H to
043FH, and Y-memory from 0440H to 063FH.
In the point of CalmRISC
In the point of MAC816
EFH in Byte
Page 12
Page 11
FFH
in Byte
063FH in word
(0C7FH in Byte)
Page 0
LCD RAM
Y-memory
(1 KBytes)
Data Memory
80H
7FH
0440H in word
(0880H in Byte)
80H
7FH
043FH in word
(087FH in Byte)
X-memory
(2 KBytes)
Control Register
00H
0040H in word
(0080H in Byte)
00H
8 Bits
16 Bits
Figure 2-6. S3CB519 Data Memory Map
2-8
S3CB519
REGISTERS
3
REGISTERS
OVERVIEW
The registers of CalmRISC are grouped into 2 types: general purpose registers and special purpose registers.
Table 3-1. General and Special Purpose Registers
Registers
Mnemonics
R0
Description
General Register 0
Reset Value
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
00H
General Purpose
Registers (GPR)
R1
General Register 1
R2
General Register 2
R3
General Register 3
Special Purpose
Registers (SPR)
Group 0 (SPR0)
Group 1 (SPR1)
IDL0
IDL1
IDH
Lower Byte of Index Register 0
Lower Byte of Index Register 1
Higher Byte of Index Register
Status Register 0
SR0
ILX
Instruction Pointer Link Register for
Extended Byte
Unknown
ILH
ILL
Instruction Pointer Link Register for
Higher Byte
Unknown
Unknown
Unknown
Instruction Pointer Link Register for
Lower Byte
SR1
Status Register 1
GPRs can be used in most instructions such as ALU instructions, stack instructions, load instructions, etc .(See
the instruction set sections). From the programming standpoint, they have almost no restriction whatsoever.
CalmRISC has 4 banks of GPRs, and each bank has 4 registers, R0, R1, R2, and R3. Hence, 16 GPRs in total are
available. The GPR bank can be switched by setting an appropriate value in SR0[4:3] (See SR0 for details). The ALU
operations between GPRs from different banks are not allowed.
SPRs are designed for their own dedicated purposes. They have some restrictions in terms of instructions that can
access them. For example, direct ALU operations cannot be performed on SPRs. However, data transfers between a
GPR and an SPR are allowed, and stack operations with SPRs are also possible (See the instruction sections for
details).
3-1
REGISTERS
S3CB519
INDEX REGISTERS: IDH, IDL0 AND IDL1
IDH in concatenation with IDL0 (or IDL1) forms a 16-bit data memory address. Note that CalmRISC’s data memory
address space is 64 Kbyte (addressable by 16-bit addresses). Basically, IDH points to a page index, and IDL0 (or
IDL1) corresponds to an offset of the page. Like GPRs, the index registers are 2-way banked. There are 2 banks in
total, each of which has its own index registers, IDH, IDL0 and IDL1. The banks of index registers can be switched
by setting an appropriate value in SR0[2] (See SR0 for details). Normally, programmers can reserve an index register
pair, IDH and IDL0 (or IDL1), for software stack operations.
LINK REGISTERS: ILX, ILH AND ILL
The link registers are specially designed for link-and-branch instructions (See LNK and LRET instructions in the
instruction sections for details). When an LNK instruction is executed, the current PC[19:0] is saved into ILX, ILH
and ILL registers (i.e., PC[19:16] into ILX[3:0], PC[15:8] into ILH [7:0]) and PC[7:0] into ILL[7:0], respectively. When
an LRET instruction is executed, the PC value returned is recovered from ILX, ILH, and ILL (i.e., ILX[3:0] into
PC[19:16], ILH[7:0] into PC[15:8] and ILL[7:0] into PC[7:0], respectively). These registers are used to access
program memory by LDC instructions. When an LDC instruction is executed, the (code) data residing at the program
address specified by ILX:ILH:ILL will be read into TBH:TBL.
There is a special core input pin signal, nP64KW, which is reserved for indicating that the program memory address
space is only 64 Kword. By grounding the signal pin to zero, the upper 4 bits of PC, PC[19:16], is deactivated and
therefore its program memory address signals from CalmRISC core are also deactivated. This, in turn, totally
eliminates the power consumption due to manipulating the upper 4 bits of PC (See the core pin description section
for details). From the programmer’s standpoint, when nP64KW is tied to the ground level, then PC[19:16] is not
saved into ILX for LNK instructions and ILX is not read back into PC[19:16] for LRET instructions. Therefore, ILX is
totally unused in LNK and LRET instructions when nP64KW = 0.
3-2
S3CB519
REGISTERS
STATUS REGISTER 0: SR0
SR0 is mainly reserved for system control functions, and each bit of SR0 has its own dedicated function.
Table 3-2. Status Register 0 Configuration
Flag Name
Bit
0
Description
Data memory page selection in direct addressing
Global interrupt enable
eid
ie
1
idb
2
Index register banking selection
GPR bank selection
grb[1:0]
exe
ie0
4,3
5
Stack overflow/underflow exception enable
Interrupt 0 enable
6
ie1
7
Interrupt 1 enable
SR0[0] (or eid) selects which page index is to be used in direct addressing. If eid = 0, then page 0 (page index = 0)
is used. Otherwise (eid = 1), IDH of the current index register bank is used for the page index. SR0[1] (or ie) is the
global interrupt enable flag. As explained in the interrupt/exception section, CalmRISC has 3 interrupt sources (non-
maskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. Both interrupt 0 and interrupt 1 are masked by
setting SR0[1] to 0 (i.e., ie = 0). When an interrupt is serviced, the global interrupt enable flag ie is automatically
cleared. The execution of an IRET instruction (return from an interrupt service routine) automatically sets ie = 1.
SR0[2] (or idb) and SR0[4:3] (or grb[1:0]) selects an appropriate bank for index registers and GPRs, respectively, as
shown below:
R3
R3
R2
R1
R0
grb [1:0]
idb
R3
R2
R1
R0
R2
R1
R0
R3
R2
R1
R0
11
1
0
Bank 3
Bank 2
Bank 1
Bank 0
IDH
IDL0
IDL1
10
01
00
IDH
IDL0
IDL1
Figure 3-1. Bank Selection by Setting of GRB Bits and IDB Bit
SR0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. If exe = 0, the stack
exception is disabled. The stack exception can be used for program debugging in the software development stage.
SR0[6] (or ie0) and SR0[7] (or ie1) are enabled, by setting them to 1. Even though ie0 or ie1 are enabled, the
interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0.
3-3
REGISTERS
S3CB519
STATUS REGISTER 1: SR1
SR1 is the register for status flags such as ALU execution flag and stack full flag.
Table 3-3. Status Register 1: SR1
Flag Name
Bit
Description
C
V
0
Carry flag
1
Overflow flag
Zero flag
Z
2
N
3
4
Negative flag
Stack Full flag
Reserved
SF
–
5, 6, 7
SR1[0] (or C) is the carry flag of ALU executions. SR1[1] (or V) is the overflow flag of ALU executions. It is set to 1 if
and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th bit
position. SR1[2] (or Z) is the zero flag, which is set to 1 if and only if the ALU result is zero. SR1[3] (or N) is the
negative flag. Basically, the most significant bit (MSB) of ALU results becomes the N flag. Note, a load instruction
into a GPR is considered an ALU instruction. However, if an ALU instruction touches the overflow flag (V) like ADD,
SUB, CP, etc, N flag is updated as exclusive-OR of V and the MSB of the ALU result. This implies that even if an
ALU operation results in an overflow, N flag is still valid. SR1[4] (or SF) is the stack overflow flag. It is set when the
hardware stack is overflowed or underflowed. Programmers can check if the hardware stack has any abnormalities
through the stack exception or testing if SF is set (See the hardware stack section for more details).
NOTE
When an interrupt occurs, the hardware does not save SR0 and SR1, so the software must save the SR1
register values.
3-4
S3CB519
MEMORY MAP
4
MEMORY MAP
OVERVIEW
To support the control of peripheral hardware, the addresses of peripheral control registers are memory-mapped to
page 0 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction at a specific
memory location.
In this section, detailed descriptions of the S3CB519 control registers are presented in an easy-to-read format.
You can use this section as a quick-reference source when writing application programs.
This memory area can be accessed with the whole method of data memory access.
— If SR0 bit 0 is “0” then the accessed register area is always page 0.
— If SR0 bit 0 is “1” then the accessed register page is controlled by the proper value of the IDH register.
So if you want to access the memory map area, clear the SR0.0 and use the direct addressing mode.
This method is used for most cases.
The control register is divided into five areas. Here, the system control register area is same in every device.
Control Register
7FH
Peripheral Control Register ( 1 x 16 or 2 x 8)
70H
6FH
Peripheral Control Register (4 x 8)
40H
3FH
Port Control Register Area (4 x 8)
20H
1FH
Port Data Register Area
10H
0FH
Standard exhortative area
System Control Register Area
00H
Standard area
Figure 4-1. Control Register Area
4-1
MEMORY MAP
S3CB519
R/W
Table 4-1. Control Registers
Register Name
Mnemonic
Decimal
Hex
Reset
Location 16H–1FH is not mapped
Port 5 data register
Port 4 data register
Port 3 data register
Port 2 data register
Port 1 data register
Port 0 data register
P5
P4
P3
P2
P1
P0
21
15H
14H
13H
12H
11H
10H
0FH
00H
00H
00H
00H
00H
R
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
Locations 0EH and 0FH are not mapped
Watchdog timer control register
Basic timer counter
WDTCON
BTCNT
IIR1
13
12
11
10
9
0DH
0CH
0BH
0AH
09H
08H
07H
06H
05H
04H
03H
02H
X0H
00H
–
R/W
R
Interrupt ID register 1
R/W
R/W
R/W
R
Interrupt priority register 1
Interrupt mask register 1
Interrupt request register 1
Interrupt ID register 00
IPR1
–
IMR1
00H
–
IRQ1
8
IIR00
7
–
R/W
R/W
R/W
R
Interrupt priority register 00
Interrupt mask register 00
Interrupt request register 00
Oscillator control register
Power control register
IPR00
IMR00
IRQ00
OSCCON
PCON
6
–
5
00H
–
4
3
00H
04H
R/W
R/W
2
Locations 00H and 01H are not mapped
NOTES
1. All the unused and unmapped registers and bits read “0”.
2. “–“ means undefined.
4-2
S3CB519
MEMORY MAP
Table 4-1. Control Registers (Continued)
Mnemonic Decimal
Locations 35H–3FH are not mapped
P5CON 52
Locations 31H–33H are not mapped
P4CON 48
Locations 2DH–2FH are not mapped
P3CON 44
Locations 29H–2BH are not mapped
P2CON 40
Locations 26H–27H are not mapped
Register Name
Hex
34H
30H
2CH
28H
Reset
00H
R/W
R/W
R/W
R/W
R/W
Port 5 control register
Port 4 control register
Port 3 control register
Port 2 control register
00H
00H
00H
Port 1 interrupt control register
Port 1 control register
P1INT
P1CON
P0EDGE
P0INT
37
36
35
34
33
32
25H
24H
23H
22H
21H
20H
00H
00H
00H
00H
00H
00H
R/W
R/W
R/W
R/W
R/W
R/W
Port 0 interrupt edge control register
Port 0 interrupt control register
Port 0 control register low
P0CONL
P0CONH
Port 0 control register high
NOTE: All unused and unmapped registers and bits read “0”.
4-3
MEMORY MAP
S3CB519
R/W
Table 4-1. Control Registers (Concluded)
Mnemonic Decimal
Locations 74H–7FH are not mapped
Register Name
Hex
Reset
D/A converter data register
D/A converter control register
Battery level detector register
Watch timer control register
DADATA
DACON
BLDCON
WTCON
115
73H
72H
71H
70H
00H
00H
40H
00H
R/W
R/W
R/W
R/W
114
113
112
Locations 5FH–6FH are not mapped
LCD contrast register
LCD mode register
LCNST
LMOD
LCON
IIR01
94
93
92
91
90
89
88
5EH
5DH
5CH
5BH
5AH
59H
58H
00H
00H
00H
–
R/W
R/W
R/W
R/W
R/W
R/W
R
LCD control register
Interrupt ID register 01
Interrupt priority register 01
Interrupt mask register 01
Interrupt request register 01
IPR01
IMR01
IRQ01
–
00H
–
Locations 53H–57H are not mapped
Timer 0 counter
T0CNT
T0DATA
82
81
80
52H
51H
50H
–
R
Timer 0 data register
Timer 0 control register
FFH
00H
R/W
R/W
T0CON
Location 4FH is not mapped
ADDATAL
A/D Converter data register, Low byte
A/D Converter data register, High byte
A/D Converter control register
78
77
76
4EH
4DH
4CH
00H
00H
00H
R
R
ADDATAH
ADCON
R/W
Location 4BH is not mapped
SIODATA
Serial I/O data register
74
73
72
4AH
49H
48H
00H
00H
00H
R/W
R/W
R/W
Serial I/O pre-scale register
Serial I/O control register
SIOPS
SIOCON
Location 47H is not mapped
TBCNT
Timer B counter
70
69
68
46H
45H
44H
–
R
Timer B data register
Timer B control register
TBDATA
FFH
00H
R/W
R/W
TBCON
Location 43H is not mapped
TACNT
Timer A counter
66
65
64
42H
41H
40H
–
R
Timer A data register
Timer A control register
TADATA
FFH
00H
R/W
R/W
TACON
NOTES
1. All unused and unmapped registers and bits read “0”.
2. “–“ means undefined.
4-4
S3CB519
HARDWARE STACK
5
HARDWARE STACK
OVERVIEW
The hardware stack in CalmRISC has two usages:
— To save and restore the return PC[19:0] on CALL, CALLS, RET, and IRET instructions.
— Temporary storage space for registers on PUSH and POP instructions.
When PC[19:0] is saved into or restored from the hardware stack, the access should be 20 bits wide. On the other
hand, when a register is pushed into or popped from the hardware stack, the access should be 8 bits wide. Hence,
to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank
(XSTACK, 4-bits wide), the odd bank (8-bits wide), and the even bank (8-bits wide).
Stack Pointer
Hardware Stack
SPTR [5:0]
5
1
0
3
0
7
0
7
0
Level 0
Level 1
Level 2
Stack Level
Pointer
Odd or Even
Bank Selector
Level 14
Level 15
XSTACK
Odd Bank
Even Bank
Figure 5-1. Hardware Stack
5-1
HARDWARE STACK
S3CB519
The top of the stack (TOS) is pointed to by a stack pointer, called sptr[5:0]. The upper 5 bits of the stack pointer,
sptr[5:1], points to the stack level into which either PC[19:0] or a register is saved. For example, if sptr[5:1] is 5H or
TOS is 5, then level 5 of XSTACK is empty and either level 5 of the odd bank or level 5 of the even bank is empty. In
fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. If sptr[0] = 0, both level 5 of the even and
the odd banks are empty. On the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but level 5 of the even
bank is occupied. This situation is well illustrated in the figure below.
Level 0
Level 1
Level 2
Level 3
SPTR [5:0]
5
0
1
0
0
0
1 0 1
Stack Level
Pointer
Level 4
Level 5
Bank Selector
Level 15
XSTACK Odd Bank Even Bank
Level 0
Level 1
Level 2
Level 3
SPTR [5:0]
5
1
1
0
1
0
0 1 0
Stack Level
Pointer
Level 4
Level 5
Bank Selector
Level 15
XSTACK Odd Bank Even Bank
Figure 5-2. Even and Odd Bank Selection Example
As can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when PC[19:0] is pushed or
popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. Note that XSTACK is used
only for storing and retrieving PC[19:16]. Let us consider the cases where PC[19:0] is pushed into the hardware
stack (by executing CALL/CALLS instructions or by interrupts/exceptions being served) or is retrieved from the
hardware stack (by executing RET/IRET instructions). Regardless of the stack bank selection bit (sptr[0]), TOS of
the even bank and the odd bank stores or returns PC[7:0] or PC[15:8], respectively. This is illustrated in the following
figures.
5-2
S3CB519
HARDWARE STACK
Level 0
SPTR [5:0]
1 0
Level 0
SPTR [5:0]
5 1 0
5
0 0 1 0 1 0
0 0 1 0 1 1
Stack Level
Stack Level
Pointer
Pointer
Level 5
Level 6
Level 5
Level 6
Bank Selector
Bank Selector
Level 15
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
by Executing CALL, CALLS
or Interrupts/Exceptions
by Executing CALL, CALLS
or Interrupts/Exceptions
by Executing RET, IRET
by Executing RET, IRET
Level 0
Level 0
SPTR [5:0]
SPTR [5:0]
5
1 0
5
1 0
0 0 1 1 0 0
0 0 1 1 0 1
Stack Level
Pointer
Stack Level
Pointer
Level 5 PC[19:16]
PC[15:8]
PC[7:0]
Level 5 PC[19:16]
PC[7:0]
Bank Selector
Level 6
Level 6
PC[15:8]
Bank Selector
Level 15
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
Figure 5-3. Stack Operation with PC [19:0]
As can be seen in the figures, when stack operations with PC[19:0] are performed, the stack level pointer sptr[5:1]
(not sptr[5:0]) is either incremented by 1 (when PC[19:0] is pushed into the stack) or decremented by 1 (when
PC[19:0] is popped from the stack). The stack bank selection bit (sptr[0]) is unchanged. If a CalmRISC core input
signal nP64KW is 0, which signifies that only PC[15:0] is meaningful, then any access to XSTACK is totally
deactivated from the stack operations with PC. Therefore, XSTACK has no meaning when the input pin signal,
nP64KW, is tied to 0. In that case, XSTACK doesn’t have to even exist. As a matter of fact, XSTACK is not included
in CalmRISC core itself and it is interfaced through some specially reserved core pin signals (nPUSH, nSTACK,
XHSI[3:0], XSHO[3:0]), if the program address space is more than 64K words (See the core pin signal section for
details).
With regards to stack operations with registers, a similar argument can be made.The only difference is that the data
written into or read from the stack are a byte. Hence, the even bank and the odd bank are accessed alternately as
shown below.
5-3
HARDWARE STACK
S3CB519
Level 0
SPTR [5:0]
1 0
Level 0
SPTR [5:0]
5 1 0
5
0 0 1 0 1 0
0 0 1 0 1 1
Stack Level
Stack Level
Pointer
Pointer
Level 5
Level 6
Level 5
Level 6
Bank Selector
Bank Selector
Level 15
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
POP Register
PUSH Register
POP Register
PUSH Register
Level 0
Level 0
SPTR [5:0]
1 0
SPTR [5:0]
5
5
1 0
0 0 1 0 1 1
0 0 1 1 0 0
Stack Level
Pointer
Stack Level
Pointer
Level 5
Level 6
Register
Level 5
Level 6
Register
Bank Selector
Bank Selector
Level 15
Level 15
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
Figure 5-4. Stack Operation with Registers
When the bank selection bit (sptr[0]) is 0, then the register is pushed into the even bank and the bank selection bit is
set to 1. In this case, the stack level pointer is unchanged. When the bank selection bit (sptr[0]) is 1, then the
register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is incremented by
1. Unlike the push operations of PC[19:0], any data are not written into XSTACK in the register push operations. This
is illustrated in the example figures. When a register is pushed into the stack, sptr[5:0] is incremented by 1 (not the
stack level pointer sptr[5:1]). The register pop operations are the reverse processes of the register push operations.
When a register is popped out of the stack, sptr[5:0] is decremented by 1 (not the stack level pointer sptr[5:1]).
Hardware stack overflow/underflow happens when the MSB of the stack level pointer, sptr[5], is 1. This is obvious
from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level pointer
in a normal case.
Suppose the stack level pointer sptr[5:1] = 15 (or 01111B in binary format) and the bank selection bit sptr[0] = 1.
Here if either PC[19:0] or a register is pushed, the stack level pointer is incremented by 1. Therefore, sptr[5:1] = 16
(or 10000B in binary format) and sptr[5] = 1, which implies that the stack is overflowed. The situation is depicted in
the following figure.
5-4
S3CB519
HARDWARE STACK
SPTR [5:0]
1 0
0 1 1 1 1 1
5
Level 0
Level 1
Level 14
Level 15
XSTACK Odd Bank Even Bank
SPTR [5:0]
1 0
1 0 0 0 0 0
SPTR [5:0]
1 0
1 0 0 0 0 1
PUSH Register
PUSH PC [19:0]
5
5
Level 0
Level 0
Level 1
PC[7:0]
Level 1
Level 14
Level 15
Level 14
Register
Level 15 PC[19:16]
PC[15:8]
XSTACK Odd Bank Even Bank
XSTACK Odd Bank Even Bank
Figure 5-5. Stack Overflow
The first overflow happens due to a register push operation. As explained earlier, a register push operation
increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. As indicated by sptr[5]
= 1, an overflow happens. Note that this overflow doesn’t overwrite any data in the stack. On the other hand, when
PC[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow results. Unlike
the first overflow, PC[7:0] is pushed into level 0 of the even bank and the data that has been there before the push
operation is overwritten. A similar argument can be made about stack underflows. Note that any stack operation,
which causes the stack to overflow or underflow, doesn’t necessarily mean that any data in the stack are lost, as is
observed in the first example.
In SR1, there is a status flag, SF (Stack Full Flag), which is exactly the same as sptr[5]. In other words, the value of
sptr[5] can be checked by reading SF (or SR1[4]). SF is not a sticky flag in the sense that if there was a stack
overflow/underflow but any following stack access instructions clear sptr[5] to 0, then SF = 0 and programmers
cannot tell whether there was a stack overflow/underflow by reading SF. For example, if a program pushes a register
64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. Therefore, special attention
should be paid.
Another mechanism to detect a stack overflow/underflow is through a stack exception. A stack exception happens
only when the execution of any stack access instruction results in SF = 1 (or sptr[5] = 1). Suppose a register push
operation makes SF = 1 (the SF value before the push operation doesn’t matter). Then the stack exception due to
the push operation is immediately generated and served If the stack exception enable flag (exe of SR0) is 1. If the
stack exception enable flag is 0, then the generated interrupt is not served but pending. Sometime later when the
stack exception enable flag is set to 1, the pending exception request is served even if SF = 0. More details are
available in the stack exception section.
5-5
HARDWARE STACK
S3CB519
NOTES
5-6
S3CB519
EXCEPTIONS
6
EXCEPTIONS
OVERVIEW
Exceptions in CalmRISC are listed in the table below. Exception handling routines, residing at the given addresses
in the table, are invoked when the corresponding exception occurs. The starting address of each exception routine is
specified by concatenating 0H (leading 4 bits of 0) and the 16-bit data in the exception vector listed in the table. For
example, the interrupt service routine for NMI starts from 0H:PM[00001H]. Note that “:” means concatenation and
PM[*] stands for the 16-bit content at the address * of the program memory. Aside from the exception due to reset
release, the current PC is pushed in the stack on an exception. When an exception is executed due to
NMI/IRQ[1:0]/IEXP, the global interrupt enable flag, ie bit (SR0[1]), is set to 0, whereas ie is set to 1 when IRET or
an instruction that explicitly sets ie is executed.
Table 6-1. Exceptions
Name
Reset
Address
00000H
00001H
00002H
00003H
00004H
00005H
00006H
00007H
Priority
1 st
2 nd
4 th
5 th
3 rd
–
Description
Exception due to rest release.
NMI
IRQ[0]
IRQ[1]
IEXP
–
Exception due to nNMI signal. Non-maskable. Not used.
Exception due to nIRQ[0] signal. Maskable by setting ie/ie0.
Exception due to nIRQ[1] signal. Maskable by setting ie/ie1.
Exception due to stack full. Maskable by setting exe.
Reserved.
–
–
Reserved.
–
–
Reserved.
NOTE: Break mode due to BKREQ has a higher priority than all the exceptions above. That is, when BKREQ is active,
even the exception due to reset release is not executed.
HARDWARE RESET
When Hardware Reset is active (the reset input signal pin nRES = 0), the control pins in the CalmRISC core are
initialized to be disabled, and SR0 and sptr (the hardware stack pointer) are initialized to be 0. Additionally, the
interrupt sensing block is cleared. When Hardware Reset is released (nRES = 1), the reset exception is executed
by loading the JP instruction in IR (Instruction Register) and 0h:0000h in PC. Therefore, when Hardware Reset is
released, the “JP {0h:PM[00000h]}” instruction is executed. When the reset exception is executed, a core output
signal nEXPACK is generated to acknowledge the exception.
6-1
EXCEPTIONS
S3CB519
NMI EXCEPTION (EDGE SENSITIVE)
On the falling edge of a core input signal nNMI, the NMI exception is executed by loading the CALL instruction in IR
and 0h:0001h in PC. Therefore, when NMI exception is activated, the “CALL {0h:PM[00001h]}” instruction is
executed. When the NMI exception is executed, the ie bit (SR0[1]) becomes 0 and a core output signal nEXPACK
is generated to acknowledge the exception.
IRQ[0] EXCEPTION (LEVEL-SENSITIVE)
When a core input signal nIRQ[0] is low, SR0[6] (ie0) is high, and SR0[1] (ie) is high, IRQ[0] exception is generated,
and this will load the CALL instruction in IR (Instruction Register) and 0h:0002h in PC. Therefore, on an IRQ[0]
exception, the “CALL {0h:PM[00002h]}” instruction is executed. When the IRQ[0] exception is executed, SR0[1] (ie)
is set to 0 and a core output signal nEXPACK is generated to acknowledge the exception.
IRQ[1] EXCEPTION (LEVEL-SENSITIVE)
When a core input signal nIRQ[1] is low, SR0[7] (ie1) is high, and SR0[1] (ie) is high, IRQ[1] exception is generated,
and this will load the CALL instruction in IR (Instruction Register) and 0h:0003h in PC. Therefore, on an IRQ[1]
exception, the “CALL {0h:PM[00003h]}” instruction is executed. When the IRQ[1] exception is executed, SR0[1] (ie)
is set to 0 and a core output signal nEXPACK is generated to acknowledge the exception.
HARDWARE STACK FULL EXCEPTION
A Stack Full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5]
(SF) is set to 1. If the stack exception enable bit, exe (SR0[5]), is 1, the Stack Full exception is served. One
exception to this rule is when nNMI causes a stack operation that sets sptr[5] (SF), since it has higher priority.
Handling a Stack Full exception may cause another Stack Full exception. In this case, the new exception is
ignored. On a Stack Full exception, the CALL instruction is loaded in IR (Instruction Register) and 0h:0004h in PC.
Therefore, when the Stack Full exception is activated, the “CALL {0h:PM[00004h]}” instruction is executed. When
the exception is executed, SR0[1] (ie) is set to 0, and a core output signal nEXPACK is generated to acknowledge
the exception.
BREAK EXCEPTION
Break exception is reserved only for an in-circuit debugger. When a core input signal, BKREQ, is high, the
CalmRISC core is halted or in the break mode, until BKREQ is deactivated. Another way to drive the CalmRISC core
into the break mode is by executing a break instruction, BREAK. When BREAK is fetched, it is decoded in the fetch
cycle (IF stage) and the CalmRISC core output signal nBKACK is generated in the second cycle (ID/MEM stage).
An in-circuit debugger generates BKREQ active by monitoring nBKACK to be active. BREAK instruction is exactly
the same as the NOP (no operation) instruction except that it does not increase the program counter and activates
nBKACK in the second cycle (or ID/MEM stage of the pipeline). There, once BREAK is encountered in the program
execution, it falls into a deadlock. BREAK instruction is reserved for in-circuit debuggers only, so it should not be
used in user programs.
6-2
S3CB519
EXCEPTIONS
EXCEPTIONS (or INTERRUPTS)
LEVEL
VECTOR
SOURCE
RESET (CLEAR)
0001H
Not used
H/W
NMI
AD/DA interrupt
Timer A match
Timer B match
SIO
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
IVEC0
0002H
External interrupt
INT0
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
INT1
INT2
INT3
INT4
INT5
INT6
Basic timer overflow
Watch timer
H/W, S/W
IVEC1
0003H
Timer 0 match
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
H/W, S/W
Timer 0 overflow
KS0
KS1
KS2
KS3
SF_EXCEP
0004H
Stack full INT
H/W
NOTES:
1. There are two interrupt vectors, and the one interrupt vector have several interrupt sources.
The priority of the sources is controlled by setting the IPR register.
2. IMR00, IPR00, IRQ00, is responsible for AD/DA interrupt, Timer A, Timer B, SIO, External,
Basic timer, Watch timer interrupt. IMR01, IPR01, IRQ01 is responsible for INT0-INT6 interrupt.
IMR1, IPR1, IRQ1 is responsible for Timer 0 Match, Timer 0 Overflow, Key scan interrupts.
3. External interrupts are triggered by a rising or falling edge, depending on the corresponding control
register setting.
4. The NMI has the most higher priority in the interrupt levels. And the priority of SF_EXCEP is next
but higher then IVEC0, IVEC1's priority is the last.
5. When system reset occurs, IPR register value is undefined.
After reset, the interrupt priority can be changed by setting of IPR register.
6. The pending bit is cleared by Hardware when CPU reads the IIR register value.
7. If you write "LD IIRx, #8H", all bits of IRQx are cleared. (Where x is 1, 00, 01)
Figure 6-1. Interrupt Structure
6-3
EXCEPTIONS
S3CB519
Clear (when writing clear bit value to bit.2. 1. 0)
ex) LD IIR1, #x5H
IRQ1.5 is cleared
IIR1
Timer 0 Match
IRQ1.0
IRQ1.1
IRQ1.2
IRQ1.3
IRQ1.4
IRQ1.5
IRQ1.6
IRQ1.7
P1INT.0
Timer 0 Overflow
IMR1
Logic
IPR1
Logic
KS0
KS1
KS2
KS3
P1INT.1
P1INT.2
P1INT.3
IVEC1
Not used
Not used
IMR1
IPR1
STOP & IDLE
Release
CPU
AD/DA Interrupt
Timer A match
Timer B match
SIO
IRQ00.0
IRQ00.1
IRQ00.2
IRQ00.3
IRQ00.4
IRQ00.5
IRQ00.6
IRQ00.7
IMR00
IPR00
IVEC0
External Interrupt
Basic Timer
Watch Timer
Not used
IMR00
Logic
IPR00
Logic
IIR00
Clear (when writing clear bit value to bit.2. 1. 0)
ex) LD IIR00, #x5H IRQ00.5 is cleared
INT0
INT1
INT2
INT3
INT4
INT5
INT6
IRQ01.0
IMR01/
IPR01
Logic
IRQ01.1
IRQ01.2
IRQ01.3
IRQ01.4
IRQ01.5
IRQ01.6
IIR01
Clear (when writing clear bit value to bit.2. 1. 0)
ex) LD IIR01, #x3H
IRQ01.3 is cleared
Figure 6-2. Interrupt Structure
6-4
S3CB519
EXCEPTIONS
INTERRUPT MASK REGISTERS
Interrupt Mask Register00 (IMR00)
05H, R/W
.7
.6
.5
.4
.3
.2
.1
.0
IRQ00.4
IRQ00.0
IRQ00.5
IRQ00.1
IRQ00.6
IRQ00.2
IRQ00.7
IRQ00.3
Interrupt Mask Register01 (IMR01)
59H, R/W
.7
.6
.5
.4
.3
.2
.1
.0
IRQ01.4
IRQ01.0
IRQ01.5
IRQ01.1
IRQ01.6
IRQ01.2
IRQ01.7
IRQ01.3
Interrupt Mask Register1 (IMR1)
09H, R/W
.7
.6
.5
.4
.3
.2
.1
.0
IRQ1.4
IRQ1.0
IRQ1.5
IRQ1.1
IRQ1.6
IRQ1.2
IRQ1.7
IRQ1.3
Interrupt request enable bits:
0 = Disable interrupt request
1 = Enable interrupt request
NOTE:
If you want to change the value of the IMR register, then you first
make disable global INT by DI instruction, and change the value of the IMR register.
Figure 6-3. Interrupt Mask Register
6-5
EXCEPTIONS
S3CB519
INTERRUPT PRIORITY REGISTER
IPR
IPR
IPR
Group A
Group B
Group C
(note)
IRQx.0
IRQx.1
IRQx.2 IRQx.3 IRQx.4
Interrupt Priority Registers
IRQx.5 IRQx.6 IRQx.7
(IPR00:06H, IPR01:5AH, IPR1:0AH, R/W )
.7
.6
.5
.4
.3
.2
.1
.0
Group priority:
Group A
.7 .4 .1
0 = IRQx.0 > IRQx.1
1 = IRQx.1 > IRQx.0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Not used
B>C>A
A>B>C
B>A>C
C>A>B
C>B>A
A>C>B
Not used
Group B
0 = IRQx.2 > (IRQx.3,IRQx.4)
1 = (IRQx.3,IRQx.4) > IRQx.2
Subgroup B
0 = IRQx.3 > IRQx.4
1 = IRQx.4 > IRQx.3
Group C
0 = IRQx.5 > (IRQx.6,IRQx.7)
1 = (IRQx.6,IRQx.7) > IRQx.5
Subgroup C
0 = IRQx.6 > IRQx.7
1 = IRQx.7 > IRQx.6
NOTE:
If you want to change the value of the IPR register, then you first make disable
global INT by DI instruction, and change the value of the IPR register.
Figure 6-4. Interrupt Priority Register
6-6
S3CB519
EXCEPTIONS
F
PROGRAMMING TIP — Interrupt Programming Tip 1
Jumped from vector 2
PUSH
PUSH
LD
SR1
R0
R0, IIR00
CP
R0, #03h
JR
CP
ULE, LTE03
R0, #05h
JR
CP
ULE, LTE05
R0, #06h
JP
JP
EQ, IRQ6_srv
T, IRQ7_srv
R0, #04
EQ, IRQ4_srv
T, IRQ5_srv
R0, #01
ULE, LTE01
R0, #02
EQ, IRQ2_srv
T, IRQ3_srv
R0, #00h
LTE05
LTE03
CP
JP
JP
CP
JR
CP
JP
JP
CP
JP
JP
LTE01
EQ, IRQ0_srv
T, IRQ1_srv
IRQ0_srv
; ® service for IRQ0
; ® service for IRQ1
·
POP
POP
IRET
R0
SR1
IRQ1_srv
IRQ7_srv
·
·
POP
POP
IRET
·
·
R0
SR1
; ® service for IRQ7
·
·
POP
POP
IRET
R0
SR1
NOTE: If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and popped in
the interrupt service routine.
6-7
EXCEPTIONS
S3CB519
F
PROGRAMMING TIP — Interrupt Programming Tip 2
Jumped from vector 2
PUSH
PUSH
PUSH
LD
SR1
R0
R1
R0, IIR00
R0
SL
LD
ADD
LD
R1, < TBL_INTx
R0, > TBL_INTx
ILH, R1
ILL, R0
LD
LRET
TBL_INTx
LJP
LJP
LJP
LJP
LJP
LJP
LJP
LJP
IRQ0_svr
IRQ1_svr
IRQ2_svr
IRQ3_svr
IRQ4_svr
IRQ5_svr
IRQ6_svr
IRQ7_svr
IRQ0_srv
IRQ1_srv
; ® service for IRQ0
·
·
POP
POP
POP
IRET
R1
R0
SR1
; ® service for IRQ1
·
·
POP
POP
POP
IRET
R1
R0
SR1
·
·
IRQ7_srv
; ® service for IRQ7
·
·
POP
POP
POP
IRET
R1
R0
SR1
NOTES:
1. If the SR0 register is changed in the interrupt service routine, then the SR0 register must be pushed and popped in the
interrupt service routine.
2. Above example is assumed that ROM size is less than 64K-word and all the LJP instructions in the jump table
(TBL_INTx) is in the same page.
6-8
S3CB519
COPROCESSOR INTERFACE
7
COPROCESSOR INTERFACE
OVERVIEW
CalmRISC supports an efficient and seamless interface with coprocessors. By integrating a MAC (multiply and
accumulate) DSP coprocessor engine with the CalmRISC core, not only the microcontroller functions but also
complex digital signal processing algorithms can be implemented in a single development platform (or MDS).
CalmRISC has a set of dedicated signal pins, through which data/command/status are exchanged to and from a
coprocessor. Depicted below are the coprocessor signal pins and the interface between two processors.
Program
ROM
Data
RAM
Data Bus [7:0]
SYSCP [11:0]
nCOPID
nCLDID
CalmRISC
Coprocessor
CLDWR
EC[2:0]
Figure 7-1. Coprocessor Interface Diagram
7-1
COPROCESSOR INTERFACE
S3CB519
As shown in the coprocessor interface diagram above, the coprocessor interface signals of CalmRISC are:
SYSCP[11:0], nCOPID, nCLDID, nCLDWR, and EC[2:0]. The data are exchanged through data buses, DI[7:0] and
DO[7:0]. A command is issued from CalmRISC to a coprocessor through SYSCP[11:0] in COP instructions. The
status of a coprocessor can be sent back to CalmRISC through EC[2:0] and these flags can be checked in the
condition codes of branch instructions. The coprocessor instructions are listed in the following table
Table 7-1. Coprocessor instructions
Mnemonic
COP
Op 1
#imm:12
GPR
Op 2
Description
–
Coprocessor operation
CLD
imm:8
GPR
label
Data transfer from coprocessor into GPR
Data transfer of GPR to coprocessor
CLD
imm:8
JP(or JR)
CALL
LNK
EC2–EC0
Conditional branch with coprocessor status flags
The coprocessor of CalmRISC does not have its own program memory (i.e., it is a passive coprocessor) as shown in
Figure 7 -1. In fact, the coprocessor instructions are fetched and decoded by CalmRISC, and CalmRISC issues the
command to the coprocessor through the interface signals. For example, if “COP #imm:12” instruction is fetched,
then the 12-bit immediate value (imm:12) is loaded on SYSCP[11:0] signal with nCOPID active in ID/MEM stage, to
request the coprocessor to perform the designated operation. The interpretation of the 12-bit immediate value is
totally up to the coprocessor. By arranging the 12-bit immediate field, the instruction set of the coprocessor is
determined. In other words, CalmRISC only provides a set of generic coprocessor instructions, and its installation to
a specific coprocessor instruction set can differ from one coprocessor to another. CLD Write instructions (“CLD
imm:8, GPR”) put the content of a GPR register of CalmRISC on the data bus (DO[7:0] ) and issue the
address(imm:8) of the coprocessor internal register on SYSCP[7:0] with nCLDID active and CLDWR active. CLD
Read instructions (“CLD GPR, imm:8” in Table 7-1) work similarly, except that the content of the coprocessor
internal register addressed by the 8-bit immediate value is read into a GPR register through DI[7:0] with nCLDID
active and CLDWR deactivated.
The timing diagram given below is a coprocessor instruction pipeline and shows when the coprocessor performs the
required operations. Suppose I2 is a coprocessor instruction. First, it is fetched and decoded by CalmRISC (at t = T(i-
1)). Once it is identified as a coprocessor instruction, CalmRISC indicates to the coprocessor the appropriate
command through the coprocessor interface signals (at t = T(i)). Then the coprocessor performs the designated
tasks at t = T(i) and t = T(i+1). Hence IF from CalmRISC and then ID/MEM and EX from the coprocessor constitute
the pipeline for I2. Similarly, if I3 is a coprocessor instruction, the coprocessor’s ID/MEM and EX stages replace the
corresponding stages of CalmRISC.
7-2
S3CB519
COPROCESSOR INTERFACE
CalmRISC
T (i -1)
T (i)
T (i +1)
IF
ID/MEM
IF
EX
ID/MEM
IF
I
I
I
1
2
3
: Normal Instruction
EX
: Coprocessor Instruction
: Coprocessor Instruction
ID/MEM
EX
Coprocessor
Interface Signals
For I
2
For I
3
Coprocessor
ID/MEM
EX
I2:
ID/MEM
EX
I3:
Figure 7-2. Coprocessor Instruction Pipeline
In a multi-processor system, the data transfer between processors is an important factor to determine the efficiency
of the overall system. Suppose an input data stream is accepted by a processor, in order for the data to be shared
by another processors. There should be some efficient mechanism to transfer the data to the processors. In
CalmRISC, data transfers are accomplished through a single shared data memory. The shared data memory in a
multi-processor has some inherent problems such as data hazards and deadlocks. However, the coprocessor in
CalmRISC accesses the shared data memory only at the designated time by CalmRISC at which time CalmRISC is
guaranteed not to access the data memory, and therefore there is no contention over the shared data memory.
Another advantage of the scheme is that the coprocessor can access the data memory in its own bandwidth.
7-3
COPROCESSOR INTERFACE
S3CB519
NOTES
7-4
S3CB519
INSTRUCTION SET
8
INSTRUCTION SET
OVERVIEW
GLOSSARY
This chapter describes the CalmRISC instruction set and the details of each instruction are listed in alphabetical
order. The following notations are used for the description.
Table 8-1. Instruction Notation Conventions
Notation
Interpretation
<opN>
Operand N. N can be omitted if there is only one operand. Typically, <op1> is the
destination (and source) operand and <op2> is a source operand.
GPR
SPR
adr:N
@idm
(adr:N)
cc:4
imm:N
&
General Purpose Register
Special Purpose Register (IDL0, IDL1, IDH, SR0, ILX, ILH, ILL, SR1)
N-bit address specifier
Content of memory location pointed by ID0 or ID1
Content of memory location specified by adr:N
4-bit condition code. Table 8-6 describes cc:4.
N-bit immediate number
Bit-wise AND
|
Bit-wise OR
~
Bit-wise NOT
^
Bit-wise XOR
N**M
(N)M
Mth power of N
M-based number N
As additional note, only the affected flags are described in the tables in this section. That is, if a flag is not affected
by an operation, it is NOT specified.
8-1
INSTRUCTION SET
S3CB519
INSTRUCTION SET MAP
Table 8-2.Overall Instruction Set Map
IR
[12:10]000
001
010
011
100
101
110
OR GPR, XOR GPR,
#imm:8 #imm:8
111
[15:13,7:2]
000 xxxxxx
ADD GPR,
#imm:8
SUB
GPR,
#imm:8
CP GPR,
#imm8
LD GPR,
#imm:8
TM GPR,
#imm:8
AND
GPR,
#imm:8
001 xxxxxx
010 xxxxxx
011 xxxxxx
100 000000
100 000001
ADD GPR,
@idm
SUB
GPR,
@idm
CP GPR,
@idm
LD GPR, LD @idm,
AND
GPR,
@idm
OR GPR, XOR GPR,
@idm @idm
@idm
GPR
ADD GPR,
adr:8
SUB
GPR,
adr:8
CP GPR,
adr:8
LD GPR,
adr:8
BITT adr:8.bs
BITS adr:8.bs
ADC GPR,
adr:8
SBC
GPR,
adr:8
CPC
GPR,
adr:8
LD adr:8,
GPR
BITR adr:8.bs
BITC adr:8.bs
ADD GPR,
GPR
SUB
GPR,
GPR
CP GPR, BMS/BMC LD SPR0,
GPR
AND
GPR,
adr:8
OR GPR, XOR GPR,
#imm:8
adr:8
adr:8
ADC GPR,
GPR
SBC
GPR,
GPR
CPC
GPR,
GPR
invalid
100 000010
100 000011
invalid
invalid
invalid
invalid
invalid
AND GPR, OR GPR,
XOR
GPR,
GPR
GPR
GPR
100 00010x
SLA/SL/
RLC/RL/
SRA/SR/
RRC/RR/
GPR
INC/INCC/
DEC/
DECC/
COM/
COM2/
COMC
GPR
invalid
invalid
100 00011x
LD SPR,
GPR
LD GPR,
SPR
SWAP
GPR,
SPR
LD
TBH/TBL,
GPR
100 00100x
100 001010
PUSH SPR POP SPR
invalid
invalid
PUSH GPR POP GPR LD GPR,
GPR
LD GPR,
TBH/TBL
8-2
S3CB519
INSTRUCTION SET
Table 8-2. Overall Instruction Set Map (Continued)
IR
[12:10]000
001
010
011
100
101
110
111
100 001011
POP
invalid
LDC
invalid
LD SPR0,
#imm:8
AND
GPR,
adr:8
OR GPR,
adr:8
XOR
GPR,
adr:8
100 00110x
RET/LRET/I
RET/NOP/
BREAK
invalid
invalid
invalid
invalid
invalid
invalid
100 00111x
100 01xxxx
invalid
LD
AND SR0, OR SR0,
BANK
GPR:bank,
GPR:bank
#imm:8
#imm:8
#imm:2
100 100000
100 110011
100 1101xx
100 1110xx
100 1111xx
invalid
invalid
invalid
invalid
LCALL cc:4, imm:20 (2-word instruction)
LLNK cc:4, imm:20 (2-word instruction)
LJP cc:4, imm:20 (2-word instruction)
[15:10]
JR cc:4, imm:9
101 xxx
110 0xx
110 1xx
111 xxx
CALLS imm:12
LNKS imm:12
CLD GPR, imm:8 / CLD imm:8, GPR / JNZD GPR, imm:8 / SYS #imm:8 / COP #imm:12
NOTE: “invalid” - invalid instruction.
8-3
INSTRUCTION SET
S3CB519
Table 8-3. Instruction Encoding
Instruction
ADD GPR, #imm:8
SUB GPR, #imm:8
CP GPR, #imm:8
LD GPR, #imm:8
TM GPR, #imm:8
AND GPR, #imm:8
OR GPR, #imm:8
XOR GPR, #imm:8
ADD GPR, @idm
SUB GPR, @idm
CP GPR, @idm
LD GPR, @idm
LD @idm, GPR
AND GPR, @idm
OR GPR, @idm
XOR GPR, @idm
ADD GPR, adr:8
SUB GPR, adr:8
CP GPR, adr:8
LD GPR, adr:8
15 14 13 12 11 10
000
9
8
7
6
5
4
3
2
1
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
GPR
imm[7:0]
001
GPR
idx
mod
offset[4:0]
010
GPR
adr[7:0]
BITT adr:8.bs
10
11
000
bs
BITS adr:8.bs
ADC GPR, adr:8
SBC GPR, adr:8
CPC GPR, adr:8
LD adr:8, GPR
011
GPR
adr[7:0]
001
010
011
BITR adr:8.bs
10
11
bs
BITC adr:8.bs
8-4
S3CB519
INSTRUCTION SET
Table 8-3. Instruction Encoding (Continued)
15 14 13 12 11 10
100
Instruction
9
8
7
6
5
4
3
2
1
0
ADD GPRd, GPRs
SUB GPRd, GPRs
CP GPRd, GPRs
BMS/BMC
000
001
010
011
000
001
010
011
ddd
000
001
010
011
000
001
010–011
000
001
010
011
GPRd
000000
GPRs
ADC GPRd, GPRs
SBC GPRd, GPRs
CPC GPRd, GPRs
invalid
000001
invalid
000010
000011
AND GPRd, GPRs
OR GPRd, GPRs
XOR GPRd, GPRs
invalid
ALUop1
GPR
GPR
xx
00010
ALUop1
ALUop2
xxx
ALUop2
invalid
LD SPR, GPR
LD GPR, SPR
SWAP GPR, SPR
LD TBL, GPR
LD TBH, GPR
PUSH SPR
POP SPR
GPR
GPR
GPR
GPR
00011
00100
SPR
SPR
SPR
0
x
x
x
x
1
000
001
xx
xx
SPR
SPR
xxx
invalid
010–011
000
xx
PUSH GPR
POP GPR
GPR
GPR
GPRd
GPR
001010
GPR
001
GPR
LD GPRd, GPRs
LD GPR, TBL
LD GPR, TBH
POP
010
GPRs
011
0
x
x
1
000
010
xx
001011
xx
xx
LDC @IL
0
1
x
x
LDC @IL+
Invalid
001, 011
NOTE: "x" means not applicable.
8-5
INSTRUCTION SET
S3CB519
Table 8-3. Instruction Encoding (Concluded)
nd
Instruction
15-13 12 11 10
9
8
7
6
5
4
3
2
1
0
2
word
MODop1
100
000
001–011
000
xx
xx
xx
00110
MODop1
xxx
–
Invalid
Invalid
01
xxxxxx
AND SR0, #imm:8
OR SR0, #imm:8
BANK #imm:2
001
imm[7:6]
imm[7:6]
xx
imm[5:0]
010
011
x
imm
[1:0]
10000000-11001111
1101 imm[19:16]
xxx
Invalid
0
1
xxxx
cc
LCALL cc, imm:20
LLNK cc, imm:20
LJP cc, imm:20
LD SPR0, #imm:8
AND GPR, adr:8
OR GPR, adr:8
XOR GPR, adr:8
JR cc, imm:9
imm[15:0]
00
01
10
11
SPR0
GPR
IMM[7:0]
ADR[7:0]
–
101
110
111
imm
[8]
0
cc
imm[7:0]
imm[7:0]
CALLS imm:12
LNKS imm:12
imm[11:0]
1
CLD GPR, imm:8
CLD imm:8, GPR
JNZD GPR, imm:8
SYS #imm:8
0
00
01
10
11
GPR
GPR
GPR
xx
COP #imm:12
1
imm[11:0]
NOTES:
1. "x" means not applicable.
2. There are several MODop1 codes that can be used, as described in table 8-9.
3. The operand 1(GPR) of the instruction JNZD is Bank 3’s register.
8-6
S3CB519
INSTRUCTION SET
Table 8-4. Index Code Information (“idx”)
Symbol
ID0
Code
Description
0
1
Index 0 IDH:IDL0
Index 1 IDH:IDL1
ID1
Table 8-5. Index Modification Code Information (“mod”)
Symbol
Code
00
Function
DM[IDx], IDx ¬ IDx + offset
@IDx + offset:5
@[IDx - offset:5]
01
DM[IDx + (2’s complement of offset:5)],
IDx ¬ IDx + (2’s complement of offset:5)
DM[IDx + offset], IDx ¬ IDx
@[IDx + offset:5]!
@[IDx - offset:5]!
10
11
DM[IDx + (2’s complement of offset:5)], IDx ¬ IDx
NOTE: Carry from IDL is propagated to IDH. In case of @[IDx - offset:5] or @[IDx - offset:5]!, the assembler should convert
offset:5 to the 2’s complement format to fill the operand field (offset[4:0]).
Furthermore, @[IDx - 0] and @[IDx - 0]! are converted to @[IDx + 0] and @[IDx + 0]!, respectively.
Table 8-6. Condition Code Information (“cc”)
Symbol (cc:4)
Blank
Code
0000
Function
always
NC or ULT
C or UGE
Z or EQ
NZ or NE
OV
0001
C = 0, unsigned less than
C = 1, unsigned greater than or equal to
Z = 1, equal to
0010
0011
0100
Z = 0, not equal to
0101
V = 1, overflow - signed value
~C | Z, unsigned less than or equal to
C & ~Z, unsigned greater than
N = 0, signed zero or positive
N = 1, signed negative
ULE
0110
UGT
0111
ZP
1000
MI
1001
PL
1010
~N & ~Z, signed positive
Z | N, signed zero or negative
Stack Full
ZN
1011
SF
1100
EC0-EC2
1101-1111
EC[0] = 1/EC[1] = 1/EC[2] = 1
NOTE: EC[2:0] is an external input (CalmRISC core’s point of view) and used as a condition.
8-7
INSTRUCTION SET
S3CB519
Table 8-7. “ALUop1” Code Information
Function
Symbol
Code
000
001
010
011
100
101
110
111
SLA
SL
arithmetic shift left
shift left
RLC
RL
rotate left with carry
rotate left
SRA
SR
arithmetic shift right
shift right
RRC
RR
rotate right with carry
rotate right
Table 8-8. “ALUop2” Code Information
Symbol
INC
Code
000
001
010
011
100
101
110
111
Function
increment
INCC
increment with carry
decrement
DEC
DECC
COM
decrement with carry
1’s complement
2’s complement
1’s complement with carry
reserved
COM2
COMC
–
Table 8-9. “MODop1” Code Information
Symbol
Code
000
001
010
011
100
101
110
111
Function
LRET
RET
IRET
NOP
BREAK
–
return by IL
return by HS
return from interrupt (by HS)
no operation
reserved for debugger use only
reserved
–
reserved
–
reserved
8-8
S3CB519
INSTRUCTION SET
QUICK REFERENCE
Operation
AND
op1
op2
Function
Flag
z,n
# of word / cycle
GPR
adr:8
op1 ¬ op1 & op2
1W1C
OR
#imm:8 op1 ¬ op1 | op2
z,n
XOR
GPR
op1 ¬ op1 ^ op2
op1 ¬ op1 + op2
z,n
ADD
@idm
c,z,v,n
c,z,v,n
c,z,v,n
c,z,v,n
c,z,v,n
c,z,v,n
z,n
SUB
op1 ¬ op1 + ~op2 + 1
op1 + ~op2 + 1
CP
ADC
GPR
GPR
adr:8
op1 ¬ op1 + op2 + c
op1 ¬ op1 + ~op2 + c
op1 + ~op2 + c
SBC
CPC
TM
GPR
R3
#imm:8 op1 & op2
adr:8.bs op1 ¬ (op2[bit] ¬ 1)
op1 ¬ (op2[bit] ¬ 0)
op1 ¬ ~(op2[bit])
BITS
z
BITR
z
BITC
z
BITT
z ¬ ~(op2[bit])
z
BMS/BMC
PUSH
POP
PUSH
POP
POP
–
–
–
TF ¬ 1 / 0
–
GPR
HS[sptr] ¬ GPR, (sptr ¬ sptr + 1)
GPR ¬ HS[sptr - 1], (sptr ¬ sptr - 1)
HS[sptr] ¬ SPR, (sptr ¬ sptr + 1)
SPR ¬ HS[sptr - 1], (sptr ¬ sptr - 1)
sptr ¬ sptr – 2
–
z,n
SPR
–
–
–
–
–
8-9
INSTRUCTION SET
S3CB519
SLA
SL
GPR
–
c ¬ op1[7], op1 ¬ {op1[6:0], 0}
c ¬ op1[7], op1 ¬ {op1[6:0], 0}
c ¬ op1[7], op1 ¬ {op1[6:0], c}
c ¬ op[7], op1 ¬ {op1[6:0], op1[7]}
c ¬ op[0], op1 ¬ {op1[7],op1[7:1]}
c ¬ op1[0], op1 ¬ {0, op1[7:1]}
c ¬ op1[0], op1 ¬ {c, op1[7:1]}
c ¬ op1[0], op1 ¬ {op1[0], op1[7:1]}
op1 ¬ op1 + 1
c,z,v,n
c,z,n
RLC
RL
c,z,n
c,z,n
SRA
SR
c,z,n
c,z,n
RRC
RR
c,z,n
c,z,n
INC
c,z,v,n
c,z,v,n
c,z,v,n
c,z,v,n
z,n
INCC
DEC
DECC
COM
COM2
COMC
op1 ¬ op1 + c
op1 ¬ op1 + 0FFh
op1 ¬ op1 + 0FFh + c
op1 ¬ ~op1
op1 ¬ ~op1 + 1
c,z,v,n
c,z,v,n
op1 ¬ ~op1 + c
8-10
S3CB519
INSTRUCTION SET
QUICK REFERENCE (Continued)
Operation
op1
op2
Function
Flag
# of word / cycle
LD
GPR
:bank
GPR
:bank
op1 ¬ op2
z,n
1W1C
LD
LD
SPR0
GPR
#imm:8 op1 ¬ op2
–
GPR
SPR
op1 ¬ op2
z,n
adr:8
@idm
#imm:8
TBH/TBL
LD
SPR
GPR
op1 ¬ op2
–
TBH/TBL
LD
adr:8
@idm
GPR
GPR
–
op1 ¬ op2
op1 ¬ op2
–
–
–
LD
LDC
@IL @IL+
(TBH:TBL) ¬ PM[(ILX:ILH:ILL)],
1W2C
1W1C
ILL++ if @IL+
AND
SR0
#imm:8 SR0 ¬ SR0 & op2
SR0 ¬ SR0 | op2
–
OR
BANK
SWAP
LCALL cc
#imm:2
GPR
–
SPR
–
SR0[4:3] ¬ op2
–
–
–
op1 ¬ op2, op2 ¬ op1 (excluding SR0/SR1)
imm:20
If branch taken, push XSTACK,
HS[15:0] ¬ {PC[15:12],PC[11:0] + 2} and
PC ¬ op1
2W2C
1W2C
else PC[11:0] ¬ PC[11:0] + 2
LLNK cc
imm:20
–
If branch taken, IL[19:0] ¬ {PC[19:12],
PC[11:0] + 2} and PC ¬ op1
else PC[11:0] ¬ PC[11:0] + 2
–
CALLS
LNKS
JNZD
imm:12
imm:12
Rn
–
–
push XSTACK, HS[15:0] ¬ {PC[15:12],
PC[11:0] + 1} and PC[11:0] ¬ op1
–
–
–
IL[19:0] ¬ {PC[19:12], PC[11:0] + 1} and
PC[11:0] ¬ op1
imm:8
if (Rn == 0) PC ¬ PC[delay slot] - 2’s
complement of imm:8, Rn--
else PC ¬ PC[delay slot]++, Rn--
LJP cc
JR cc
imm:20
imm:9
–
–
If branch taken, PC ¬ op1
–
–
2W2C
1W2C
else PC[11:0] < PC[11:0] + 2
If branch taken, PC[11:0] ¬ PC[11:0] + op1
else PC[11:0] ¬ PC[11:0] + 1
NOTE: op1 - operand1, op2 - operand2, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word 2-Cycle instruction, 2W2C -
2-Word 2-Cycle instruction. The Rn of instruction JNZD is Bank 3’s GPR.
8-11
INSTRUCTION SET
S3CB519
QUICK REFERENCE (Concluded)
Operation
LRET
RET
op1
op2
Function
Flag
# of word / cycle
1W2C
–
–
PC ¬ IL[19:0]
–
PC ¬ HS[sptr - 2], (sptr ¬ sptr - 2)
PC ¬ HS[sptr - 2], (sptr ¬ sptr - 2)
no operation
1W2C
IRET
1W2C
NOP
1W1C
BREAK
SYS
no operation and hold PC
1W1C
#imm:8
imm:8
–
no operation but generates SYSCP[7:0] and
nSYSID
–
–
1W1C
CLD
CLD
GPR
op1 ¬ op2, generates SYSCP[7:0], nCLDID,
and CLDWR
GPR
imm:8 op1 ¬ op2, generates SYSCP[7:0], nCLDID,
z,n
–
and CLDWR
COP
#imm:12
–
generates SYSCP[11:0] and nCOPID
NOTES:
1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1W1C - 1-Word 1-Cycle instruction, 1W2C - 1-Word
2-Cycle instruction
2. Pseudo instructions
—
—
—
—
SCF/RCF
Carry flag set or reset instruction
STOP/IDLE
MCU power saving instructions
EI/DI
Exception enable and disable instructions
JP/LNK/CALL
If JR/LNKS/CALLS commands (1 word instructions) can access the target address, there is no conditional code
in the case of CALL/LNK, and the JP/LNK/CALL commands are assembled to JR/LNKS/CALLS in linking time,
or
else the JP/LNK/CALL commands are assembled to LJP/LLNK/LCALL (2 word instructions) instructions.
8-12
S3CB519
INSTRUCTION SET
INSTRUCTION GROUP SUMMARY
ALU INSTRUCTIONS
“ALU instructions” refer to the operations that use ALU to generate results. ALU instructions update the values in
Status Register 1 (SR1), namely carry (C), zero (Z), overflow (V), and negative (N), depending on the operation type
and the result.
ALUop GPR, adr:8
Performs an ALU operation on the value in GPR and the value in DM[adr:8] and stores the result into GPR.
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPR+(not DM[adr:8])+1 is performed.
adr:8 is the offset in a specific data memory page.
The data memory page is 0 or the value of IDH (Index of Data Memory Higher Byte Register), depending on the value
of eid in Status Register 0 (SR0).
Operation
GPR ¬ GPR ALUop DM[00h:adr:8] if eid = 0
GPR ¬ GPR ALUop DM[IDH:adr8] if eid = 1
Note that this is an 8-bit operation.
Example
ADD R0, 80h
// Assume eid = 1 and IDH = 01H
// R0 ¬ R0 + DM[0180h]
ALUop GPR, #imm:8
Stores the result of an ALU operation on GPR and an 8-bit immediate value into GPR.
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPR+(not #imm:8)+1 is performed.
#imm:8 is an 8-bit immediate value.
Operation
GPR ¬ GPR ALUop #imm:8
Example
ADD R0, #7Ah
// R0 ¬ R0 + 7Ah
8-13
INSTRUCTION SET
S3CB519
ALUop GPRd, GPRs
Store the result of ALUop on GPRs and GPRd into GPRd.
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPRd + (not GPRs) + 1 is performed.
GPRs and GPRd need not be distinct.
Operation
GPRd ¬ GPRd ALUop GPRs
GPRd - GPRs when ALUop = CP (comparison only)
Example
ADD R0, R1
ALUop GPR, @idm
// R0 ¬ R0 + R1
Performs ALUop on the value in GPR and DM[ID] and stores the result into GPR. Index register ID is IDH:IDL
(IDH:IDL0 or IDH:IDL1).
ALUop = ADD, SUB, CP, AND, OR, XOR
For SUB and CP, GPR+(not DM[idm])+1 is performed.
idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]!
(IDx = ID0 or ID1)
Operation
GPR - DM[idm] when ALUop = CP (comparison only)
GPR ¬ GPR ALUop DM[IDx], IDx ¬ IDx + offset:5 when idm = IDx + offset:5
GPR ¬ GPR ALUop DM[IDx - offset:5], IDx ¬ IDx - offset:5 when idm = [IDx - offset:5]
GPR ¬ GPR ALUop DM[IDx + offset:5] when idm = [IDx + offset:5]!
GPR ¬ GPR ALUop DM[IDx - offset:5] when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH.
Example
ADD R0, @ID0+2
ADD R0, @[ID0-2]
ADD R0, @[ID1+2]!
ADD R0, @[ID1-2]!
// assume ID0 = 02FFh
// R0 ¬ R0 + DM[02FFh], IDH ¬ 03h and IDL0 ¬ 01h
// assume ID0 = 0201h
// R0 ¬ R0 + DM[01FFh], IDH ¬ 01h and IDL0 ¬ FFh
// assume ID1 = 02FFh
// R0 ¬ R0 + DM[0301], IDH ¬ 02h and IDL1 ¬ FFh
// assume ID1 = 0200h
// R0 ¬ R0 + DM[01FEh], IDH ¬ 02h and IDL1 ¬ 00h
8-14
S3CB519
INSTRUCTION SET
ALUopc GPRd, GPRs
Performs ALUop with carry on GPRd and GPRs and stores the result into GPRd.
ALUopc = ADC, SBC, CPC
GPRd and GPRs need not be distinct.
Operation
GPRd ¬ GPRd + GPRs + C when ALUopc = ADC
GPRd ¬ GPRd + (not GPRs) + C when ALUopc = SBC
GPRd + (not GPRs) + C when ALUopc = CPC (comparison only)
Example
ADD R0, R2
ADC R1, R3
// assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers.
// to add two 16-bit numbers, use ADD and ADC.
SUB R0, R2
SBC R1, R3
// assume R1:R0 and R3:R2 are 16-bit signed or unsigned numbers.
// to subtract two 16-bit numbers, use SUB and SBC.
CP R0, R2
CPC R1, R3
// assume both R1:R0 and R3:R2 are 16-bit unsigned numbers.
// to compare two 16-bit unsigned numbers, use CP and CPC.
ALUopc GPR, adr:8
Performs ALUop with carry on GPR and DM[adr:8].
Operation
GPR ¬ GPR + DM[adr:8] + C when ALUopc = ADC
GPR ¬ GPR + (not DM[adr:8]) + C when ALUopc = SBC
GPR + (not DM[adr:8]) + C when ALUopc = CPC (comparison only)
CPLop GPR (Complement Operations)
CPLop = COM, COM2, COMC
Operation
COM GPR
COM2 GPR
COMC GPR
not GPR (logical complement)
not GPR + 1 (2’s complement of GPR)
not GPR + C (logical complement of GPR with carry)
Example
COM2 R0
COMC R1
// assume R1:R0 is a 16-bit signed number.
// COM2 and COMC can be used to get the 2’s complement of it.
8-15
INSTRUCTION SET
S3CB519
IncDec GPR (Increment/Decrement Operations)
IncDec = INC, INCC, DEC, DECC
Operation
INC GPR
Increase GPR, i.e., GPR ¬ GPR + 1
INCC GPR
Increase GPR if carry = 1, i.e., GPR ¬ GPR + C
DEC GPR
Decrease GPR, i.e., GPR ¬ GPR + FFh
DECC GPR
Decrease GPR if carry = 0, i.e., GPR ¬ GPR + FFh + C
Example
INC R0
// assume R1:R0 is a 16-bit number
INCC R1
// to increase R1:R0, use INC and INCC.
DEC R0
// assume R1:R0 is a 16-bit number
DECC R1
// to decrease R1:R0, use DEC and DECC.
8-16
S3CB519
INSTRUCTION SET
SHIFT/ROTATE INSTRUCTIONS
Shift (Rotate) instructions shift (rotate) the given operand by 1 bit. Depending on the operation performed, a number
of Status Register 1 (SR1) bits, namely Carry (C), Zero (Z), Overflow (V), and Negative (N), are set.
SL GPR
Operation
7
0
C
0
GPR
Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
SLA GPR
Operation
7
0
C
0
GPR
Carry (C) is the MSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) will be 1 if the MSB of the result is different from C. Z will be 1 if the result is 0.
RL GPR
Operation
7
0
C
GPR
Carry (C) is the MSB of GPR before rotating. Negative (N) is the MSB of GPR after rotatin/g.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
RLC GPR
Operation
7
0
GPR
C
Carry (C) is the MSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
8-17
INSTRUCTION SET
S3CB519
SR GPR
Operation
7
0
0
C
GPR
Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
SRA GPR
Operation
7
0
C
GPR
Carry (C) is the LSB of GPR before shifting, Negative (N) is the MSB of GPR after shifting.
Overflow (V) is not affected. Z will be 1 if the result is 0.
RR GPR
Operation
7
0
C
GPR
Carry (C) is the LSB of GPR before rotating. Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
RRC GPR
Operation
7
0
GPR
C
Carry (C) is the LSB of GPR before rotating, Negative (N) is the MSB of GPR after rotating.
Overflow (V) is not affected. Zero (Z) will be 1 if the result is 0.
8-18
S3CB519
INSTRUCTION SET
LOAD INSTRUCTIONS
Load instructions transfer data from data memory to a register or from a register to data memory, or assigns an
immediate value into a register. As a side effect, a load instruction placing a value into a register sets the Zero (Z)
and Negative (N) bits in Status Register 1 (SR1), if the placed data is 00h and the MSB of the data is 1, respectively.
LD GPR, adr:8
Loads the value of DM[adr:8] into GPR. Adr:8 is offset in the page specified by the value of eid in Status Register 0
(SR0).
Operation
GPR ¬ DM[00h:adr:8] if eid = 0
GPR ¬ DM[IDH:adr:8] if eid = 1
Note that this is an 8-bit operation.
Example
LD R0, 80h
// assume eid = 1 and IDH= 01H
// R0 ¬ DM[0180h]
LD GPR, @idm
Loads a value from the data memory location specified by @idm into GPR.
idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]!
(IDx = ID0 or ID1)
Operation
GPR ¬ DM[IDx], IDx ¬ IDx + offset:5 when idm = IDx + offset:5
GPR ¬ DM[IDx - offset:5], IDx ¬ IDx - offset:5 when idm = [IDx - offset:5]
GPR ¬ DM[IDx + offset:5] when idm = [IDx + offset:5]!
GPR ¬ DM[IDx - offset:5] when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH.
Example
LD R0, @[ID0 + 03h]!
// assume IDH:IDL0 = 0270h
// R0 ¬ DM[0273h], IDH:IDL0 ¬ 0270h
8-19
INSTRUCTION SET
LD REG, #imm:8
S3CB519
Loads an 8-bit immediate value into REG. REG can be either GPR or an SPR0 group register - IDH (Index of Data
Memory Higher Byte Register), IDL0 (Index of Data Memory Lower Byte Register)/ IDL1, and Status Register 0
(SR0). #imm:8 is an 8-bit immediate value.
Operation
REG ¬ #imm:8
Example
LD R0 #7Ah
LD IDH, #03h
// R0 ¬ 7Ah
// IDH ¬ 03h
LD GPR:bs:2, GPR:bs:2
Loads a value of a register from a specified bank into another register in a specified bank.
Example
LD R0:1, R2:3
LD GPR, TBH/TBL
// R0 in bank 1, R2 in bank 3
Loads the value of TBH or TBL into GPR. TBH and TBL are 8-bit long registers used exclusively for LDC instructions
that access program memory. Therefore, after an LDC instruction, LD GPR, TBH/TBL instruction will usually move
the data into GPRs, to be used for other operations.
Operation
GPR ¬ TBH (or TBL)
Example
LDC @IL
// gets a program memory item residing @ ILX:ILH:ILL
LD R0, TBH
LD R1, TBL
LD TBH/TBL, GPR
Loads the value of GPR into TBH or TBL. These instructions are used in pair in interrupt service routines to save and
restore the values in TBH/TBL as needed.
Operation
TBH (or TBL) ¬ GPR
LD GPR, SPR
Loads the value of SPR into GPR.
Operation
GPR ¬ SPR
Example
LD R0, IDH
// R0 ¬ IDH
8-20
S3CB519
INSTRUCTION SET
LD SPR, GPR
Loads the value of GPR into SPR.
Operation
SPR ¬ GPR
Example
LD IDH, R0
// IDH ¬ R0
LD adr:8, GPR
Stores the value of GPR into data memory (DM). adr:8 is offset in the page specified by the value of eid in Status
Register 0 (SR0).
Operation
DM[00h:adr:8] ¬ GPR if eid = 0
DM[IDH:adr:8] ¬ GPR if eid = 1
Note that this is an 8-bit operation.
Example
LD 7Ah, R0
// assume eid = 1 and IDH = 02h.
// DM[027Ah] ¬ R0
LD @idm, GPR
Loads a value into the data memory location specified by @idm from GPR.
idm = IDx+off:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]!
(IDx = ID0 or ID1)
Operation
DM[IDx] ¬ GPR, IDx ¬ IDx + offset:5 when idm = IDx + offset:5
DM[IDx - offset:5] ¬ GPR, IDx ¬ IDx - offset:5 when idm = [IDx - offset:5]
DM[IDx + offset:5] ¬ GPR when idm = [IDx + offset:5]!
DM[IDx - offset:5] ¬ GPR when idm = [IDx - offset:5]!
When carry is generated from IDL (on a post-increment or pre-decrement), it is propagated to IDH.
Example
LD @[ID0 + 03h]!, R0
// assume IDH:IDL0 = 0170h
// DM[0173h] ¬ R0, IDH:IDL0 ¬ 0170h
8-21
INSTRUCTION SET
S3CB519
BRANCH INSTRUCTIONS
Branch instructions can be categorized into jump instruction, link instruction, and call instruction. A jump instruction
does not save the current PC, whereas a call instruction saves (“pushes”) the current PC onto the stack and a link
instruction saves the PC in the link register IL. Status registers are not affected. Each instruction type has a 2-word
format that supports a 20-bit long jump.
JR cc:4, imm:9
imm:9 is a signed number (2’s complement), an offset to be added to the current PC to compute the target
(PC[19:12]:(PC[11:0] + imm:9)).
Operation
PC[11:0] ¬ PC[11:0] + imm:9
PC[11:0] ¬ PC[11:0] + 1
if branch taken (i.e., cc:4 resolves to be true)
otherwise
Example
L18411:
// assume current PC = 18411h.
JR Z, 107h
// next PC is 18518 (18411h + 107h) if Zero (Z) bit is set.
LJP cc:4, imm:20
Jumps to the program address specified by imm:20. If program size is less than 64K word, PC[19:16] is not
affected.
Operation
PC[15:0] ¬ imm[15:0] if branch taken and program size is less than 64K word
PC[19:0] ¬ imm[19:0] if branch taken and program size is equal to 64K word or more
PC [11:0] ¬ PC[11:0] + 1 otherwise
Example
L18411:
// assume current PC = 18411h.
LJP Z, 10107h
// next instruction’s PC is 10107h If Zero (Z) bit is set
JNZD Rn, imm:8
Jumps to the program address specified by imm:8 if the value of the bank 3 register Rn is not zero. JNZD performs
only backward jumps, with the value of Rn automatically decreased. There is one delay slot following the JNZD
instruction that is always executed, regardless of whether JNZD is taken or not.
Operation
If (Rn == 0) PC ¬ PC[delay slot] (-) 2’s complement of imm:8, Rn ¬ Rn - 1
else PC ¬ PC[delay slot] + 1, Rn ¬ Rn - 1.
8-22
S3CB519
INSTRUCTION SET
Example
LOOP_A:
// start of loop body
·
·
·
JNZD R0, LOOP_A
ADD R1, #2
// jump back to LOOP_A if R0 is not zero
// delay slot, always executed (you must use one cycle instruction only)
CALLS imm:12
Saves the current PC on the stack (“pushes” PC) and jumps to the program address specified by imm:12. The
current page number PC[19:12] is not changed. Since this is a 1-word instruction, the return address pushed onto
the stack is (PC + 1). If nP64KW is low when PC is saved, PC[19:16] is not saved in the stack.
Operation
HS[sptr][15:0] ¬ current PC + 1 and sptr ¬ sptr + 2 (push stack)
HS[sptr][19:0] ¬ current PC + 1 and sptr ¬ sptr + 2 (push stack)
PC[11:0] ¬ imm:12
if nP64KW = 0
if nP64KW = 1
Example
L18411:
// assume current PC = 18411h.
CALLS 107h
// call the subroutine at 18107h, with the current PC pushed
// onto the stack (HS ¬ 18412h) if nP64KW = 1.
LCALL cc:4, imm:20
Saves the current PC onto the stack (pushes PC) and jumps to the program address specified by imm:20. Since
this is a 2-word instruction, the return address saved in the stack is (PC + 2). If nP64KW, a core input signal is low
when PC is saved, 0000111111PC[19:16] is not saved in the stack and PC[19:16] is not set to imm[19:16].
Operation
HS[sptr][15:0] ¬ current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 0
HS[sptr][19:0] ¬ current PC + 2 and sptr + 2 (push stack) if branch taken and nP64KW = 1
PC[15:0] ¬ imm[15:0] if branch taken and nP64KW = 0
PC[19:0] ¬ imm[19:0] if branch taken and nP64KW = 1
PC[11:0] ¬ PC[11:0] + 2 otherwise
Example
L18411:
// assume current PC = 18411h.
LCALL NZ, 10107h
// call the subroutine at 10107h with the current PC pushed
// onto the stack (HS ¬ 18413h)
8-23
INSTRUCTION SET
LNKS imm:12
S3CB519
Saves the current PC in IL and jumps to the program address specified by imm:12. The current page number
PC[19:12] is not changed. Since this is a 1-word instruction, the return address saved in IL is (PC + 1). If the
program size is less than 64K word when PC is saved, PC[19:16] is not saved in ILX.
Operation
IL[15:0] ¬ current PC + 1
IL[19:0] ¬ current PC + 1
PC[11:0] ¬ imm:12
if program size is less than 64K word
if program size is equal to 64K word or more
Example
L18411:
// assume current PC = 18411h.
LNKS 107h
// call the subroutine at 18107h, with the current PC saved
// in IL (IL[19:0] ¬ 18412h) if program size is 64K word or more.
LLNK cc:4, imm:20
Saves the current PC in IL and jumps to the program address specified by imm:20. Since this is a 2-word
instruction, the return address saved in IL is (PC + 2). If the program size is less than 64K word when PC is saved,
PC[19:16] is not saved in ILX.
Operation
IL[15:0] ¬ current PC + 2 if branch taken and program size is less than 64K word
IL[19:0] ¬ current PC + 2 if branch taken and program size is 64K word or more
PC[15:0] ¬ imm[15:0] if branch taken and program size is less than 64K word
PC[19:0] ¬ imm[19:0] if branch taken and program size is 64K word or more
PC[11:0] ¬ PC[11:0] + 2 otherwise
Example
L18411:
// assume current PC = 18411h.
LLNK NZ, 10107h
// call the subroutine at 10107h with the current PC saved
// in IL (IL[19:0] ¬ 18413h) if program size is 64K word or more
RET, IRET
Returns from the current subroutine. IRET sets ie (SR0[1]) in addition. If the program size is less than 64K word,
PC[19:16] is not loaded from HS[19:16].
Operation
PC[15:0] ¬ HS[sptr - 2] and sptr ¬ sptr - 2 (pop stack) if program size is less than 64K word
PC[19:0] ¬ HS[sptr - 2] and sptr ¬ sptr - 2 (pop stack) if program size is 64K word or more
Example
RET
// assume sptr = 3h and HS[1] = 18407h.
// the next PC will be 18407h and sptr is set to 1h
8-24
S3CB519
LRET
INSTRUCTION SET
Returns from the current subroutine, using the link register IL. If the program size is less than 64K word, PC[19:16]
is not loaded from ILX.
Operation
PC[15:0] ¬ IL[15:0]
PC[19:0] ¬ IL[19:0]
if program size is less than 64K word
if program size is 64K word or more
Example
LRET
// assume IL = 18407h.
// the next instruction to execute is at PC = 18407h
// if program size is 64K word or more
JP/LNK/CALL
JP/LNK/CALL instructions are pseudo instructions. If JR/LNKS/CALLS commands (1 word instructions) can access
the target address, there is no conditional code in the case of CALL/LNK and the JP/LNK/CALL commands are
assembled to JR/LNKS/CALLS in linking time or else the JP/LNK/CALL commands are assembled to
LJP/LLNK/LCALL (2 word instructions) instructions.
8-25
INSTRUCTION SET
S3CB519
BIT MANIPULATION INSTRUCTIONS
BITop adr:8.bs
Performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result into
R3 of current GPR bank or back into memory depending on the value of TF bit.
BITop = BITS, BITR, BITC, BITT
BITS: bit set
BITR: bit reset
BITC: bit complement
BITT: bit test (R3 is not touched in this case)
bs: bit location specifier, 0 - 7.
Operation
R3 ¬ DM[00h:adr:8] BITop bs if eid = 0
R3 ¬ DM[IDH:adr:8] BITop bs if eid = 1 (no register transfer for BITT)
Set the Zero (Z) bit if the result is 0.
Example
BITS 25h.3
BITT 25h.3
// assume eid = 0. set bit 3 of DM[00h:25h] and store the result in R3.
// check bit 3 of DM[00h:25h] if eid = 0.
BMC/BMS
Clears or sets the TF bit, which is used to determine the destination of BITop instructions. When TF bit is clear, the
result of BITop instructions will be stored into R3 (fixed); if the TF bit is set, the result will be written back to
memory.
Operation
TF ¬ 0
TF ¬ 1
(BMC)
(BMS)
TM GPR, #imm:8
Performs AND operation on GPR and imm:8 and sets the Zero (Z) and Negative (N) bits. No change in GPR.
Operation
Z, N flag ¬ GPR & #imm:8
BITop GPR.bs
Performs a bit operation on GPR and stores the result in GPR.
Since the equivalent functionality can be achieved using OR GPR, #imm:8, AND GPR, #imm:8, and XOR GPR,
#imm:8, this instruction type doesn’t have separate op codes.
8-26
S3CB519
INSTRUCTION SET
AND SR0, #imm:8/OR SR0, #imm:8
Sets/resets bits in SR0 and stores the result back into SR0.
Operation
SR0 ¬ SR0 & #imm:8
SR0 ¬ SR0 | #imm:8
BANK #imm:2
Loads SR0[4:3] with #imm[1:0].
Operation
SR0[4:3] ¬ #imm[1:0]
MISCELLANEOUS INSTRUCTION
SWAP GPR, SPR
Swaps the values in GPR and SPR. SR0 and SR1 can NOT be used for this instruction.
No flag is updated, even though the destination is GPR.
Operation
temp ¬ SPR
SPR ¬ GPR
GPR ¬ temp
Example
SWAP R0, IDH
// assume IDH = 00h and R0 = 08h.
// after this, IDH = 08h and R0 = 00h.
PUSH REG
Saves REG in the stack (Pushes REG into stack).
REG = GPR, SPR
Operation
HS[sptr][7:0] ¬ REG and sptr ¬ sptr + 1
Example
PUSH R0
// assume R0 = 08h and sptr = 2h
// then HS[2][7:0] ¬ 08h and sptr ¬ 3h
8-27
INSTRUCTION SET
POP REG
S3CB519
Pops stack into REG.
REG = GPR, SPR
Operation
REG ¬ HS[sptr-1][7:0] and sptr ¬ sptr – 1
Example
POP R0
// assume sptr = 3h and HS[2] = 18407h
// R0 ¬ 07h and sptr ¬ 2h
POP
Pops 2 bytes from the stack and discards the popped data.
NOP
Does no work but increase PC by 1.
BREAK
Does nothing and does NOT increment PC. This instruction is for the debugger only. When this instruction is
executed, the processor is locked since PC is not incremented. Therefore, this instruction should not be used under
any mode other than the debug mode.
SYS #imm:8
Does nothing but increase PC by 1 and generates SYSCP[7:0] and nSYSID signals.
CLD GPR, imm:8
GPR ¬ (imm:8) and generates SYSCP[7:0], nCLDID, and nCLDWR signals.
CLD imm:8, GPR
(imm:8) ¬ GPR and generates SYSCP[7:0], nCLDID, and nCLDWR signals.
COP #imm:12
Generates SYSCP[11:0] and nCOPID signals.
8-28
S3CB519
INSTRUCTION SET
LDC
Loads program memory item into register.
Operation
[TBH:TBL] ¬ PM[ILX:ILH:ILL]
(LDC @IL)
[TBH:TBL] ¬ PM[ILX:ILH:ILL], ILL++
(LDC @IL+)
TBH and TBL are temporary registers to hold the transferred program memory items. These can be accessed only
by LD GPR and TBL/TBH instruction.
Example
LD ILX, R1
LD ILH, R2
LD ILL, R3
LDC @IL
// assume R1:R2:R3 has the program address to access
// get the program data @(ILX:ILH:ILL) into TBH:TBL
8-29
INSTRUCTION SET
S3CB519
PSEUDO INSTRUCTIONS
EI/DI
Exceptions enable and disable instruction.
Operation
SR0 ¬ OR SR0,#00000010b (EI)
SR0 ¬ AND SR0,#11111101b (DI)
Exceptions are enabled or disabled through this instruction. If there is an EI instruction, the SR0.1 is set and reset,
when DI instruction.
Example
DI
·
·
·
EI
SCF/RCF
Carry flag set and reset instruction.
Operation
CP R0,R0
AND R0,R0
(SCF)
(RCF)
Carry flag is set or reset through this instruction. If there is an SCF instruction, the SR1.0 is set and reset, when
RCF instruction.
Example
SCF
RCF
STOP/IDLE
MCU power saving instruction.
Operation
SYS #0Ah
SYS #05h
(STOP)
(IDLE)
The STOP instruction stops the both CPU clock and system clock and causes the microcontroller to enter STOP
mode. The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue.
Example
STOP(or IDLE)
NOP
NOP
NOP
·
·
8-30
INSTRUCTION SET
S3CB519
ADC— Add with Carry
Format:
ADC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
Operation:
Flags:
<op1> ¬ <op1> + <op2> + C
ADC adds the values of <op1> and <op2> and carry (C) and stores the result back into <op1>
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
.
Example:
ADC
ADC
R0, 80h
R0, R1
// If eid = 0, R0 ¬ R0 + DM[0080h] + C
// If eid = 1, R0 ¬ R0 + DM[IDH:80h] + C
// R0 ¬ R0 + R1 + C
ADD
ADC
R0, R2
R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of “ADD R0, R2” is not zero, Z flag can be set to ‘1’ if the result
of “ADC R1,R3” is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit addition, take care of the change of Z flag.
8-32
S3CB519
INSTRUCTION SET
ADD— Add
Format:
ADD <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
Flags:
<op1> ¬ <op1> + <op2>
ADD adds the values of <op1> and <op2> and stores the result back into <op1>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
.
Example:
Given: IDH:IDL0 = 80FFh, eid = 1
ADD
ADD
ADD
R0, 80h
R0, #12h
R1, R2
// R0 ¬ R0 + DM[8080h]
// R0 ¬ R0 + 12h
// R1 ¬ R1 + R2
ADD
ADD
ADD
ADD
R0, @ID0 + 2
R0, @[ID0 – 3]
R0, @[ID0 + 2]!
R0, @[ID0 – 2]!
// R0 ¬ R0 + DM[80FFh], IDH ¬ 81h, IDL0 ¬ 01h
// R0 ¬ R0 + DM[80FCh], IDH ¬ 80h, IDL0 ¬ FCh
// R0 ¬ R0 + DM[8101h], IDH ¬ 80h, IDL0 ¬ FFh
// R0 ¬ R0 + DM[80FDh], IDH ¬ 80h, IDL0 ¬ FFh
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-33
INSTRUCTION SET
S3CB519
AND — Bit-wise AND
Format:
AND <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ¬ <op1> & <op2>
AND performs bit-wise AND on the values in <op1> and <op2> and stores the result in <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: set if the MSB of result is 1. Reset if not.
Example:
Given: IDH:IDL0 = 01FFh, eid = 1
AND
AND
AND
R0, 7Ah
R1, #40h
R0, R1
// R0 ¬ R0 & DM[017Ah]
// R1 ¬ R1 & 40h
// R0 ¬ R0 & R1
AND
AND
AND
AND
R1, @ID0 + 3
R1, @[ID0 – 5]
R1, @[ID0 + 7]!
R1, @[ID0 – 2]!
// R1 ¬ R1 & DM[01FFh], IDH:IDL0 ¬ 0202h
// R1 ¬ R1 & DM[01FAh], IDH:IDL0 ¬ 01FAh
// R1 ¬ R1 & DM[0206h], IDH:IDL0 ¬ 01FFh
// R1 ¬ R1 & DM[01FDh], IDH:IDL0 ¬ 01FFh
In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data memory
DM[0051h-007Fh] are not mapped in S3CB519/S3FB519. In the last two instructions, the value of
IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed explanation about this addressing
mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-34
S3CB519
INSTRUCTION SET
AND SR0— Bit-wise AND with SR0
Format:
AND SR0, #imm:8
Operation:
SR0 ¬ SR0 & imm:8
AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the
result in SR0.
Flags:
–
Example:
Given: SR0 = 11000010b
nIE
nIE0
nIE1
EQU
EQU
EQU
~02h
~40h
~80h
AND
AND
SR0, #nIE | nIE0 | nIE1
SR0, #11111101b
In the first example, the statement “AND SR0, #nIE|nIE0|nIE1” clear all of bits of the global interrupt,
interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to ‘1’ by instruction “OR SR0,
#imm:8”. Refer to instruction OR SR0 for more detailed explanation about enabling bit.
In the second example, the statement “AND SR0, #11111101b” is equal to instruction DI, which is
disabling interrupt globally.
8-35
INSTRUCTION SET
S3CB519
BANK — GPR Bank selection
Format:
Operation:
Flags:
BANK #imm:2
SR0[4:3] ¬ imm:2
–
NOTE:
For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3.
Example:
BANK
LD
#1
R0, #11h
// Select register bank 1
// Bank1’s R0 ¬ 11h
BANK
LD
#2
R1, #22h
// Select register bank 2
// Bank2’s R1 ¬ 22h
8-36
S3CB519
INSTRUCTION SET
BITC— Bit Complement
Format:
BITC adr:8.bs
bs: 3-digit bit specifier
R3 ¬ ((adr:8) ^ (2**bs))
Operation:
if (TF == 0)
(adr:8) ¬ ((adr:8) ^ (2**bs)) if (TF == 1)
BITC complements the specified bit of a value read from memory and stores the result in R3 or
back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
NOTE:
Since the destination register R3 is fixed, it is not specified explicitly.
Given: IDH = 01, DM[0180h] = FFh, eid = 1
Example:
BMC
BITC
// TF ¬ 0
// R3 ¬ FEh, DM[0180h] = FFh
80h.0
80h.1
BMS
BITC
// TF ¬ 1
// DM[0180h] ¬ FDh
8-37
INSTRUCTION SET
S3CB519
BITR— Bit Reset
Format:
BITR adr:8.bs
bs: 3-digit bit specifier
Operation:
R3 ¬ ((adr:8) & ((11111111)2 - (2**bs)))
if (TF == 0)
(adr:8) ¬ ((adr:8) & ((11111111)2 - (2**bs))) if (TF == 1)
BITR resets the specified bit of a value read from memory and stores the result in R3 or back
into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
NOTE:
Since the destination register R3 is fixed, it is not specified explicitly.
Given: IDH = 01, DM[0180h] = FFh, eid = 1
Example:
BMC
BITR
// TF ¬ 0
// R3 ¬ FDh, DM[0180h] = FFh
80h.1
80h.2
BMS
BITR
// TF ¬ 1
// DM[0180h] ¬ FBh
8-38
S3CB519
INSTRUCTION SET
BITS — Bit Set
Format:
BITS adr:8.bs
bs: 3-digit bit specifier.
Operation:
R3 ¬ ((adr:8) | (2**bs))
if (TF == 0)
(adr:8) ¬ ((adr:8) | (2**bs)) if (TF == 1)
BITS sets the specified bit of a value read from memory and stores the result in R3 or back into
memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.
Flags:
Z: set if result is zero. Reset if not.
NOTE:
Since the destination register R3 is fixed, it is not specified explicitly.
Given: IDH = 01, DM[0180h] = F0h, eid = 1
Example:
BMC
BITS
// TF ¬ 0
// R3 ¬ 0F2h, DM[0180h] = F0h
80h.1
80h.2
BMS
BITS
// TF ¬ 1
// DM[0180h] ¬ F4h
8-39
INSTRUCTION SET
S3CB519
BITT — Bit Test
Format:
BITT adr:8.bs
bs: 3-digit bit specifier.
Operation:
Z ¬ ~((adr:8) & (2**bs))
BITT tests the specified bit of a value read from memory.
Z: set if result is zero. Reset if not.
Given: DM[0080h] = F7h, eid = 0
Flags:
Example:
BITT
JR
80h.3
Z, %1
// Z flag is set to ‘1’
// Jump to label %1 because condition is true.
·
·
·
%1
BITS
NOP
80h.3
·
·
·
8-40
S3CB519
INSTRUCTION SET
BMC/BMS– TF bit clear/set
Format:
BMS/BMC
Operation:
BMC/BMS clears (sets) the TF bit.
TF ¬ 0 if BMC
TF ¬ 1 if BMS
TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR, and
BITS.
Flags:
–
NOTE:
BMC/BMS are the only instructions that modify the content of the TF bit.
Example:
BMS
BITS
// TF ¬ 1
// TF ¬ 0
81h.1
BMC
BITR
LD
81h.2
R0, R3
8-41
INSTRUCTION SET
S3CB519
CALL — Conditional Subroutine Call (Pseudo Instruction)
Format:
CALL cc:4, imm:20
CALL imm:12
Operation:
If CALLS can access the target address and there is no conditional code (cc:4), CALL command is
assembled to CALLS (1-word instruction) in linking time, else the CALL is assembled to LCALL (2-word
instruction).
Example:
CALL
·
C, Wait
0088h
// HS[sptr][15:0] ¬ current PC + 2, sptr ¬ sptr + 2
// 2-word instruction
·
·
CALL
// HS[sptr][15:0] ¬ current PC + 1, sptr ¬ sptr + 2
·
// 1-word instruction
·
·
Wait: NOP
NOP
// Address at 0088h
NOP
NOP
NOP
RET
8-42
S3CB519
INSTRUCTION SET
CALLS — Call Subroutine
Format:
CALLS imm:12
Operation:
HS[sptr][15:0] ¬ current PC + 1, sptr ¬ sptr + 2 if the program size is less than 64K word.
HS[sptr][19:0] ¬ current PC + 1, sptr ¬ sptr + 2 if the program size is equal to or over 64K word.
PC[11:0] ¬ imm:12
CALLS unconditionally calls a subroutine residing at the address specified by imm:12.
Flags:
–
Example:
CALLS
Wait
·
·
·
Wait: NOP
NOP
NOP
RET
Because this is a 1-word instruction, the saved returning address on stack is (PC + 1).
8-43
INSTRUCTION SET
S3CB519
CLD— Load into Coprocessor
Format:
CLD imm:8, <op>
<op>: GPR
Operation:
(imm:8) ¬ <op>
CLD loads the value of <op> into (imm:8), where imm:8 is used to access the external
coprocessor's address space.
Flags:
–
Example:
AH
AL
BH
BL
EQU
EQU
EQU
EQU
00h
01h
02h
03h
·
·
·
CLD
CLD
AH, R0
AL, R1
// A[15:8] ¬ R0
// A[7:0] ¬ R1
CLD
CLD
BH, R2
BL, R3
// B[15:8] ¬ R2
// B[7:0] ¬ R3
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.
Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
8-44
S3CB519
INSTRUCTION SET
CLD— Load from Coprocessor
Format:
CLD <op>, imm:8
<op>: GPR
Operation:
<op> ¬ (imm:8)
CLD loads a value from the coprocessor, whose address is specified by imm:8.
Flags:
Z: set if the loaded value in <op1> is zero. Reset if not.
N: set if the MSB of the loaded value in <op1> is 1. Reset if not.
Example:
AH
AL
BH
BL
EQU
EQU
EQU
EQU
00h
01h
02h
03h
·
·
·
CLD
CLD
R0, AH
R1, AL
// R0 ¬ A[15:8]
// R1 ¬ A[7:0]
CLD
CLD
R2, BH
R3, BL
// R2 ¬ B[15:8]
// R3 ¬ B[7:0]
The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.
Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.
8-45
INSTRUCTION SET
S3CB519
COM — 1's or Bit-wise Complement
Format:
COM <op>
<op>: GPR
Operation:
<op> ¬ ~<op>
COM takes the bit-wise complement operation on <op> and stores the result in <op>.
Flags:
Z: set if result is zero. Reset if not.
N: set if the MSB of result is 1. Reset if not.
Example:
Given: R1 = 5Ah
COM
R1
// R1 ¬ A5h, N flag is set to ‘1’
8-46
S3CB519
INSTRUCTION SET
COM2— 2's Complement
Format:
Operation:
Flags:
COM2 <op>
<op>: GPR
<op> ¬ ~<op> + 1
COM2 computes the 2's complement of <op> and stores the result in <op>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative.
Example:
Given: R0 = 00h, R1 = 5Ah
COM2
COM2
R0
R1
// R0 ¬ 00h, Z and C flags are set to ‘1’.
// R1 ¬ A6h, N flag is set to ‘1’.
8-47
INSTRUCTION SET
S3CB519
COMC— Bit-wise Complement with Carry
Format:
Operation:
Flags:
COMC <op>
<op>: GPR
<op> ¬ ~<op> + C
COMC takes the bit-wise complement of <op>, adds carry and stores the result in <op>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
If register pair R1:R0 is a 16-bit number, then the 2’s complement of R1:R0 can be obtained by
COM2 and COMC as following.
COM2
COMC
R0
R1
Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register pair
R1: R0 has value of FF01h, then 2’s complement of R1: R0 is made of 00FFh by COM2 and COMC.
At this time, by instruction COMC, zero (Z) flag is set to ‘1’ as if the result of 2’s complement for 16-
bit number is zero. Therefore when programming 16-bit comparison, take care of the change of Z
flag.
8-48
S3CB519
INSTRUCTION SET
COP — Coprocessor
Format:
Operation:
Flags:
COP #imm:12
COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals.
–
Example:
COP
COP
#0D01h
#0234h
// generate 1 word instruction code(FD01h)
// generate 1 word instruction code(F234h)
The above two instructions are equal to statement “ELD A, #1234h” for MAC816 operation. The
microcode of MAC instruction “ELD A, #1234h” is “FD01F234”, 2-word instruction. In this, code ‘F’
indicates ‘COP’ instruction.
8-49
INSTRUCTION SET
S3CB519
CP— Compare
Format:
Operation:
Flags:
CP <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
<op1> + ~<op2> + 1
CP compares the values of <op1> and <op2> by subtracting <op2> from <op1>. Contents of <op1>
and <op2> are not changed.
C: set if carry is generated. Reset if not.
Z: set if result is zero (i.e., <op1> and <op2> are same). Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1
CP
CP
CP
R0, 80h
R0, #73h
R0, R1
// C flag is set to ‘1’
// Z and C flags are set to ‘1’
// V flag is set to ‘1’
CP
CP
CP
CP
R1, @ID0
// Z and C flags are set to ‘1’
R1, @[ID0 – 5]
R2, @[ID0 + 7]!
R2, @[ID0 – 2]!
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-50
S3CB519
INSTRUCTION SET
CPC — Compare with Carry
Format:
Operation:
Flags:
CPC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
<op1> ¬ <op1> + ~<op2> + C
CPC compares <op1> and <op2> by subtracting <op2> from <op1>. Unlike CP, however, CPC
adds (C - 1) to the result. Contents of <op1> and <op2> are not changed.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC
to compare two 16-bit numbers as follows.
CP
CPC
R0, R1
R2, R3
Because CPC considers C when comparing <op1> and <op2>, CP and CPC can be used in pair to
compare 16-bit operands. But note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit comparison, take care of the change of Z flag.
8-51
INSTRUCTION SET
S3CB519
DEC— Decrement
Format:
Operation:
Flags:
DEC <op>
<op>: GPR
<op> ¬ <op> + 0FFh
DEC decrease the value in <op> by adding 0FFh to <op>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: R0 = 80h, R1 = 00h
DEC
DEC
R0
R1
// R0 ¬ 7Fh, C, V and N flags are set to ‘1’
// R1 ¬ FFh, N flags is set to ‘1’
8-52
S3CB519
INSTRUCTION SET
DECC— Decrement with Carry
Format:
DECC <op>
<op>: GPR
Operation:
<op> ¬ <op> + 0FFh + C
DECC decrease the value in <op> when carry is not set. When there is a carry, there is no
change in the value of <op>.
Flags:
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to
decrement 16-bit number as follows.
DEC
DECC
R0
R1
Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming
16-bit decrement, take care of the change of Z flag.
8-53
INSTRUCTION SET
S3CB519
DI — Disable Interrupt (Pseudo Instruction)
Format:
DI
Operation:
Disables interrupt globally. It is same as “AND SR0, #0FDh” .
DI instruction sets bit1 (ie: global interrupt enable) of SR0 register to “0”
Flags:
–
Example:
Given: SR0 = 03h
DI
// SR0 ¬ SR0 & 11111101b
DI instruction clears SR0[1] to ‘0’, disabling interrupt processing.
8-54
S3CB519
INSTRUCTION SET
EI — Enable Interrupt (Pseudo Instruction)
Format:
EI
Operation:
Enables interrupt globally. It is same as “OR SR0, #02h” .
EI instruction sets the bit1 (ie: global interrupt enable) of SR0 register to “1”
Flags:
–
Example:
Given: SR0 = 01h
EI
// SR0 ¬ SR0 | 00000010b
The statement “EI” sets the SR0[1] to ‘1’, enabling all interrupts.
8-55
INSTRUCTION SET
S3CB519
IDLE — Idle Operation (Pseudo Instruction)
Format:
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue.
Idle mode can be released by an interrupt or reset operation.
The IDLE instruction is a pseudo instruction. It is assembled as “SYS #05H”, and this generates the
SYSCP[7-0] signals. Then these signals are decoded and the decoded signals execute the idle
operation.
Flags:
NOTE:
–
The next instruction of IDLE instruction is executed, so please use the NOP instruction after the IDLE
instruction.
Example:
IDLE
NOP
NOP
NOP
·
·
·
The IDLE instruction stops the CPU clock but not the system clock.
8-56
S3CB519
INSTRUCTION SET
INC— Increment
Format:
Operation:
Flags:
INC <op>
<op>: GPR
<op> ¬ <op> + 1
INC increase the value in <op>.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: R0 = 7Fh, R1 = FFh
INC
INC
R0
R1
// R0 ¬ 80h, V flag is set to ‘1’
// R1 ¬ 00h, Z and C flags are set to ‘1’
8-57
INSTRUCTION SET
S3CB519
INCC— Increment with Carry
Format:
INCC <op>
<op>: GPR
Operation:
<op> ¬ <op> + C
INCC increase the value of <op> only if there is carry. When there is no carry, the value of
<op> is not changed.
Flags:
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment
16-bit number as following.
INC
INCC
R0
R1
Assume R1:R0 is 0010h, statement “INC R0” increase R0 by one without carry and statement
“INCC R1” set zero (Z) flag to ‘1’ as if the result of 16-bit increment is zero. Note that zero (Z) flag do
not exactly reflect result of 16-bit operation. Therefore when programming 16-bit increment, take
care of the change of Z flag.
8-58
S3CB519
INSTRUCTION SET
IRET — Return from Interrupt Handling
Format:
IRET
Operation:
PC ¬ HS[sptr - 2], sptr ¬ sptr - 2
IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to
PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation.
Flags:
NOTE:
–
The program size (indicated by the nP64KW signal) determines which portion of PC is updated.
When the program size is less than 64K word, only the lower 16 bits of PC are updated
(i.e., PC[15:0] ¬ HS[sptr – 2]).
When the program size is 64K word or more, the action taken is PC[19:0] ¬ HS[sptr - 2].
Example:
SF_EXCEP:
NOP
// Stack full exception service routine
·
·
·
IRET
8-59
INSTRUCTION SET
S3CB519
JNZD— Jump Not Zero with Delay slot
Format:
JNZD <op>, imm:8
<op>: GPR (bank 3’s GPR only)
imm:8 is an signed number
PC ¬ PC[delay slot] - 2’s complement of imm:8
<op> ¬ <op> - 1
Operation:
JNZD performs a backward PC-relative jump if <op> evaluates to be non-zero. Furthermore, JNZD
decrease the value of <op>. The instruction immediately following JNZD (i.e., in delay slot) is always
executed, and this instruction must be 1 cycle instruction.
Flags:
NOTE:
–
Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however, that
the chosen instruction should be “dead” outside the loop for it executes even when the loop is exited
(i.e., JNZD is not taken).
Example:
Given: IDH = 03h, eid = 1
BANK
#3
LD
LD
R0, #0FFh
R1, #0
// R0 is used to loop counter
%1
LD
JNZD
LD
IDL0, R0
R0, %B1
@ID0, R1
// If R0 of bank3 is not zero, jump to %1.
// Clear register pointed by ID0
·
·
·
This example can be used for RAM clear routine. The last instruction is executed even if the loop is
exited.
8-60
S3CB519
INSTRUCTION SET
JP— Conditional Jump (Pseudo Instruction)
Format:
JP cc:4 imm:20
JP cc:4 imm:9
Operation:
If JR can access the target address, JP command is assembled to JR (1 word instruction) in linking
time, else the JP is assembled to LJP (2 word instruction) instruction.
There are 16 different conditions that can be used, as described in table 8-6.
Example:
%1
LD
R0, #10h
// Assume address of label %1 is 020Dh
·
·
·
JP
Z, %B1
C, %F2
// Address at 0264h
// Address at 0265h
JP
·
·
·
%2
LD
R1, #20h
// Assume address of label %2 is 089Ch
·
·
·
In the above example, the statement “JP Z, %B1” is assembled to JR instruction. Assuming that
current PC is 0264h and condition is true, next PC is made by PC[11:0] ¬ PC[11:0] + offset, offset
value is “64h + A9h” without carry. ‘A9’ means 2’s complement of offset value to jump backward.
Therefore next PC is 020Dh. On the other hand, statement “JP C, %F2” is assembled to LJP
instruction because offset address exceeds the range of imm:9.
8-61
INSTRUCTION SET
S3CB519
JR— Conditional Jump Relative
Format:
JR cc:4 imm:9
cc:4: 4-bit condition code
Operation:
PC[11:0] ¬ PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign-
extended to 12 bits when added to PC.
There are 16 different conditions that can be used, as described in table 8-6.
Flags:
NOTE:
–
Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to
compute the actual jump address, while LJP directly jumps to imm:20, the target.
Example:
JR
·
Z, %1
// Assume current PC = 1000h
// Address at 10A5h
·
·
%1
LD
R0, R1
·
·
·
After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to ‘1’. The range
of the relative address is from +255 to –256 because imm:9 is signed number.
8-62
S3CB519
INSTRUCTION SET
LCALL — Conditional Subroutine Call
Format:
LCALL cc:4, imm:20
Operation:
HS[sptr][15:0] ¬ current PC + 2, sptr ¬ sptr + 2, PC[15:0] ¬ imm[15:0] if the condition holds
and the program size is less than 64K word.
HS[sptr][19:0] ¬ current PC + 2, sptr ¬ sptr + 2, PC[19:0] ¬ imm:20 if the condition holds and
the program size is equal to or over 64K word.
PC[11:0] ¬ PC[11:0] + 2 otherwise.
LCALL instruction is used to call a subroutine whose starting address is specified by imm:20.
Flags:
–
Example:
LCALL
LCALL
L1
C, L2
Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word instruction,
the saved returning address on stack is (PC + 2).
8-63
INSTRUCTION SET
S3CB519
LD adr:8 — Load into Memory
Format:
LD adr:8, <op>
<op>: GPR
Operation:
DM[00h:adr:8] ¬ <op> if eid = 0
DM[IDH:adr:8] ¬ <op> if eid = 1
LD adr:8 loads the value of <op> into a memory location. The memory location is determined by
the eid bit and adr:8.
Flags:
–
Example:
Given: IDH = 01h
LD
80h, R0
If eid bit of SR0 is zero, the statement “LD 80h, R0” load value of R0 into DM[0080h], else eid bit
was set to ‘1’, the statement “LD 80h, R0” load value of R0 into DM[0180h]
8-64
S3CB519
INSTRUCTION SET
LD @idm— Load into Memory Indexed
Format:
LD @idm, <op>
<op>: GPR
Operation:
(@idm) ¬ <op>
LD @idm loads the value of <op> into the memory location determined by @idm. Details of the
@idm format and how the actual address is calculated can be found in chapter 2.
Flags:
–
Example:
Given R0 = 5Ah, IDH:IDL0 = 8023h, eid = 1
LD
LD
LD
LD
LD
@ID0, R0
// DM[8023h] ¬ 5Ah
@ID0 + 3, R0
@[ID0-5], R0
@[ID0+4]!, R0
@[ID0-2]!, R0
// DM[8023h] ¬ 5Ah, IDL0 ¬ 26h
// DM[801Eh] ¬ 5Ah, IDL0 ¬ 1Eh
// DM[8027h] ¬ 5Ah, IDL0 ¬ 23h
// DM[8021h] ¬ 5Ah, IDL0 ¬ 23h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-65
INSTRUCTION SET
S3CB519
LD— Load Register
Format:
LD <op1>, <op2>
<op1>: GPR
<op2>: GPR, SPR, adr:8, @idm, #imm:8
Operation:
<op1> ¬ <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
Given: R0 = 5Ah, R1 = AAh, IDH:IDL0 = 8023h, eid = 1
LD
LD
LD
LD
R0, R1
// R0 ¬ AAh
// R1 ¬ 80h
R1, IDH
R2, 80h
R0, #11h
// R2 ¬ DM[8080h]
// R0 ¬ 11h
LD
LD
LD
LD
R0, @ID0+1
R1, @[ID0-2]
R2, @[ID0+3]!
R3, @[ID0-5]!
// R0 ¬ DM[8023h], IDL0 ¬ 24h
// R1 ¬ DM[8021h], IDL0 ¬ 21h
// R2 ¬ DM[8026h], IDL0 ¬ 23h
// R3 ¬ DM[801Eh], IDL0 ¬ 23h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-66
S3CB519
INSTRUCTION SET
LD— Load GPR:bankd, GPR:banks
Format:
LD <op1>, <op2>
<op1>: GPR: bankd
<op2>: GPR: banks
Operation:
<op1> ¬ <op2>
LD loads a value of a register in a specified bank (banks) into another register in a specified bank
(bankd).
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
LD
LD
R2:1, R0:3
R0:0, R0:2
// Bank1’s R2 ¬ bank3’s R0
// Bank0’s R0 ¬ bank2’s R0
8-67
INSTRUCTION SET
S3CB519
LD— Load GPR, TBH/TBL
Format:
LD <op1>, <op2>
<op1>: GPR
<op2>: TBH/TBL
Operation:
<op1> ¬ <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
Flags:
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
Given: register pair R1:R0 is 16-bit unsigned data.
LDC
LD
LD
@IL
R1, TBH
R0, TBL
// TBH:TBL ¬ PM[ILX:ILH:ILL]
// R1 ¬ TBH
// R0 ¬ TBL
8-68
S3CB519
INSTRUCTION SET
LD— Load TBH/TBL, GPR
Format:
LD <op1>, <op2>
<op1>: TBH/TBL
<op2>: GPR
Operation:
<op1> ¬ <op2>
LD loads a value specified by <op2> into the register designated by <op1>.
–
Flags:
Example:
Given: register pair R1:R0 is 16-bit unsigned data.
LD
LD
TBH, R1
TBL, R0
// TBH ¬ R1
// TBL ¬ R0
8-69
INSTRUCTION SET
S3CB519
LD SPR — Load SPR
Format:
LD <op1>, <op2>
<op1>: SPR
<op2>: GPR
Operation:
<op1> ¬ <op2>
LD SPR loads the value of a GPR into an SPR.
Refer to Table 3-1 for more detailed explanation about kind of SPR.
Flags:
–
Example:
Given: register pair R1:R0 = 1020h
LD
LD
ILH, R1
ILL, R0
// ILH ¬ 10h
// ILL ¬ 20h
8-70
S3CB519
INSTRUCTION SET
LD SPR0— Load SPR0 Immediate
Format:
LD SPR0, #imm:8
Operation:
SPR0 ¬ imm:8
LD SPR0 loads an 8-bit immediate value into SPR0.
–
Flags:
Example:
Given: eid = 1, idb = 0 (index register bank 0 selection)
LD
LD
LD
LD
IDH, #80h
IDL1, #44h
IDL0, #55h
SR0, #02h
// IDH point to page 80h
The last instruction set ie (global interrupt enable) bit to ‘1’.
Special register group 1 (SPR1) registers are not supported in this addressing mode.
8-71
INSTRUCTION SET
S3CB519
LDC — Load Code
Format:
LDC <op1>
<op1>: @IL, @IL+
Operation:
TBH:TBL ¬ PM[ILX:ILH:ILL]
ILL ¬ ILL + 1 (@IL+ only)
LDC loads a data item from program memory and stores it in the TBH:TBL register pair.
@IL+ increase the value of ILL, efficiently implementing table lookup operations.
Flags:
–
Example:
LD
LD
LD
LDC
ILX, R1
ILH, R2
ILL, R3
@IL
// Loads value of PM[ILX:ILH:ILL] into TBH:TBL
// Move data in TBH:TBL to GPRs for further processing
LD
LD
R1, TBH
R0, TBL
The statement “LDC @IL” do not increase, but if you use statement “LDC @IL+”, ILL register is
increased by one after instruction execution.
8-72
S3CB519
INSTRUCTION SET
LJP— Conditional Jump
Format:
LJP cc:4, imm:20
cc:4: 4-bit condition code
Operation:
PC[15:0] ¬ imm[15:0] if condition is true and the program size is less than 64K word. If the program
is equal to or larger than 64K word, PC[19:0] ¬ imm[19:0] as long as the condition is true. There
are 16 different conditions that can be used, as described in table 8-6.
Flags:
NOTE:
–
LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address
of the jump.
Example:
LJP
·
C, %1
R0, R1
// Assume current PC = 0812h
// Address at 10A5h
·
·
%1
LD
·
·
·
After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true.
8-73
INSTRUCTION SET
S3CB519
LLNK— Linked Subroutine Call Conditional
Format:
LLNK cc:4, imm:20
cc:4: 4-bit condition code
Operation:
If condition is true, IL[19:0] ¬ {PC[19:12], PC[11:0] + 2}.
Further, when the program is equal to or larger than 64K word, PC[19:0] ¬ imm[19:0] as long as the
condition is true. If the program is smaller than 64K word, PC[15:0] ¬ imm[15:0].
There are 16 different conditions that can be used, as described in table 8-6.
Flags:
NOTE:
–
LLNK is used to conditionally to call a subroutine with the return address saved in the link register
(IL) without stack operation. This is a 2-word instruction.
Example:
LLNK
NOP
Z, %1
// Address at 005Ch, ILX:ILH:ILL ¬ 00:00:5Eh
// Address at 005Eh
·
·
·
%1
LD
R0, R1
·
·
·
LRET
8-74
S3CB519
INSTRUCTION SET
LNK— Linked Subroutine Call (Pseudo Instruction)
Format:
LNK cc:4, imm:20
LNK imm:12
Operation:
If LNKS can access the target address and there is no conditional code (cc:4), LNK command is
assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2
word instruction).
Example:
LNK
LNK
Z, Link1
Link2
// Equal to “LLNK Z, Link1”
// Equal to “LNKS Link2”
NOP
·
·
·
Link2: NOP
·
·
·
LRET
Subroutines
section CODE, ABS 0A00h
Subroutines
Link1: NOP
·
·
·
LRET
8-75
INSTRUCTION SET
S3CB519
LNKS— Linked Subroutine Call
Format:
LNKS imm:12
Operation:
IL[19:0] ¬ {PC[19:12], PC[11:0] + 1} and PC[11:0] ¬ imm:12
LNKS saves the current PC in the link register and jumps to the address specified by imm:12.
Flags:
NOTE:
–
LNKS is used to call a subroutine with the return address saved in the link register (IL) without stack
operation.
Example:
LNKS
Link1
// Address at 005Ch, ILX:ILH:ILL ¬ 00:00:5Dh
NOP
// Address at 005Dh
·
·
·
Link1: NOP
·
·
·
LRET
8-76
S3CB519
INSTRUCTION SET
LRET — Return from Linked Subroutine Call
Format:
LRET
Operation:
PC ¬ IL[19:0]
LRET returns from a subroutine by assigning the saved return address in IL to PC.
Flags:
–
Example:
LNK
Link1
Link1: NOP
·
·
·
LRET
; PC[19:0] ¬ ILX:ILH:ILL
8-77
INSTRUCTION SET
S3CB519
NOP — No Operation
Format:
NOP
Operation:
No operation.
When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction
time is delayed by approximately one machine cycle per each NOP instruction encountered.
Flags:
–
Example:
NOP
8-78
S3CB519
INSTRUCTION SET
OR— Bit-wise OR
Format:
OR <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
Flags:
<op1> ¬ <op1> | <op2>
OR performs the bit-wise OR operation on <op1> and <op2> and stores the result in <op1>.
Z: set if result is zero. Reset if not.
N: exclusive OR of V and MSB of result.
Example:
Given: IDH:IDL0 = 031Eh, eid = 1
OR
OR
OR
R0, 80h
R1, #40h
R1, R0
// R0 ¬ R0 | DM[0380h]
// Mask bit6 of R1
// R1 ¬ R1 | R0
OR
OR
OR
OR
R0, @ID0
// R0 ¬ R0 | DM[031Eh], IDL0 ¬ 1Eh
// R1 ¬ R1 | DM[031Dh], IDL0 ¬ 1Dh
// R2 ¬ R2 | DM[031Fh], IDL0 ¬ 1Eh
// R3 ¬ R3 | DM[031Dh], IDL0 ¬ 1Eh
R1, @[ID0-1]
R2, @[ID0+1]!
R3, @[ID0-1]!
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-79
INSTRUCTION SET
S3CB519
OR SR0— Bit-wise OR with SR0
Format:
OR SR0, #imm:8
Operation:
SR0 ¬ SR0 | imm:8
OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0.
–
Flags:
Example:
Given: SR0 = 00000000b
EID
IE
IDB1
IE0
IE1
EQU
EQU
EQU
EQU
EQU
01h
02h
04h
40h
80h
OR
OR
SR0, #IE | IE0 | IE1
SR0, #00000010b
In the first example, the statement “OR SR0, #EID|IE|IE0” set global interrupt(ie), interrupt 0(ie0) and
interrupt 1(ie1) to ‘1’ in SR0. On the contrary, enabled bits can be cleared with instruction “AND
SR0, #imm:8”. Refer to instruction AND SR0 for more detailed explanation about disabling bit.
In the second example, the statement “OR SR0, #00000010b” is equal to instruction EI, which is
enabling interrupt globally.
8-80
S3CB519
INSTRUCTION SET
POP — POP
Format:
POP
sptr ¬ sptr – 2
Operation:
POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated.
–
Flags:
Example:
Given: sptr[5:0] = 001010b
POP
This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b.
8-81
INSTRUCTION SET
S3CB519
POP — POP to Register
Format:
Operation:
Flags:
POP <op>
<op>: GPR, SPR
<op> ¬ HS[sptr - 1], sptr ¬ sptr - 1
POP copies the value on top of the stack to <op> and decrease sptr by 1.
Z: set if the value copied to <op> is zero. Reset if not.
N: set if the value copied to <op> is negative. Reset if not.
When <op> is SPR, no flags are affected, including Z and N.
Example:
POP
POP
R0
// R0 ¬ HS[sptr-1], sptr ¬ sptr-1
// IDH ¬ HS[sptr-1], sptr ¬ sptr-1
IDH
In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction “POP IDH” load
value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about POP
operations for hardware stack.
8-82
S3CB519
INSTRUCTION SET
PUSH— Push Register
Format:
PUSH <op>
<op>: GPR, SPR
Operation:
HS[sptr] ¬ <op>, sptr ¬ sptr + 1
PUSH stores the value of <op> on top of the stack and increase sptr by 1.
–
Flags:
Example:
PUSH
PUSH
R0
// HS[sptr] ¬ R0, sptr ¬ sptr + 1
// HS[sptr] ¬ IDH, sptr ¬ sptr + 1
IDH
In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction “PUSH
IDH” load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0] be emptied.
Refer to chapter 5 for more detailed explanation about PUSH operations for hardware stack.
8-83
INSTRUCTION SET
S3CB519
RET — Return from Subroutine
Format:
RET
Operation:
PC ¬ HS[sptr - 2], sptr ¬ sptr – 2
RET pops an address on the hardware stack into PC so that control returns to the subroutine call
site.
Flags:
–
Example:
Given: sptr[5:0] = 001010b
CALLS
Wait
// Address at 00120h
// Address at 01000h
·
·
·
Wait: NOP
NOP
NOP
NOP
NOP
RET
After the first instruction CALLS execution, “PC+1”, 0121h is loaded to HS[5] and hardware stack
pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value 0121h
on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became 001010b.
8-84
S3CB519
INSTRUCTION SET
RL — Rotate Left
Format:
RL <op>
<op>: GPR
Operation:
C ¬ <op>[7], <op> ¬ {<op>[6:0], <op>[7]}
RL rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C).
Flags:
C: set if the MSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R0 = 01001010b, R1 = 10100101b
RL
RL
R0
R1
// N flag is set to ‘1’, R0 ¬ 10010100b
// C flag is set to ‘1’, R1 ¬ 01001011b
8-85
INSTRUCTION SET
S3CB519
RLC— Rotate Left with Carry
Format:
RLC <op>
<op>: GPR
Operation:
C ¬ <op>[7], <op> ¬ {<op>[6:0], C}
RLC rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C), and the original C bit is copied into <op>[0].
Flags:
C: set if the MSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R2 = A5h, if C = 0
RLC
R2
// R2 ¬ 4Ah, C flag is set to ‘1’
RL
RLC
R0
R1
In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are
used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
8-86
S3CB519
INSTRUCTION SET
RR— Rotate Right
Format:
RR <op>
<op>: GPR
Operation:
C ¬ <op>[0], <op> ¬ {<op>[0], <op>[7:1]}
RR rotates the value of <op> to the right and stores the result back into <op>. The original LSB of
<op> is copied into carry (C).
Flags:
C: set if the LSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R0 = 01011010b, R1 = 10100101b
RR
RR
R0
R1
// No change of flag, R0 ¬ 00101101b
// C and N flags are set to ‘1’, R1 ¬ 11010010b
8-87
INSTRUCTION SET
S3CB519
RRC— Rotate Right with Carry
Format:
RRC <op>
<op>: GPR
Operation:
C ¬ <op>[0], <op> ¬ {C, <op>[7:1]}
RRC rotates the value of <op> to the right and stores the result back into <op>. The original LSB of
<op> is copied into carry (C), and C is copied to the MSB.
Flags:
C: set if the LSB of <op> (before rotating) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after rotating) is 1. Reset if not.
Example:
Given: R2 = A5h, if C = 0
RRC
R2
// R2 ¬ 52h, C flag is set to ‘1’
RR
RRC
R0
R1
In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC are
used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.
8-88
S3CB519
INSTRUCTION SET
SBC— Subtract with Carry
Format:
Operation:
Flags:
SBC <op1>, <op2>
<op1>: GPR
<op2>: adr:8, GPR
<op1> ¬ <op1> + ~<op2> + C
SBC computes (<op1> - <op2>) when there is carry and (<op1> - <op2> - 1) when there is no
carry.
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated.
N: set if result is negative. Reset if not.
Example:
SBC
SBC
R0, 80h
R0, R1
// If eid = 0, R0 ¬ R0 + ~DM[0080h] + C
// If eid = 1, R0 ¬ R0 + ~DM[IDH:80h] + C
// R0 ¬ R0 + ~R1 + C
SUB
SBC
R0, R2
R1, R3
In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of “ADD R0, R2” is not zero, zero (Z) flag can be set to ‘1’ if the
result of “SBC R1,R3” is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit addition, take care of the change of Z flag.
8-89
INSTRUCTION SET
S3CB519
SL — Shift Left
Format:
Operation:
Flags:
SL <op>
<op>: GPR
C ¬ <op>[7], <op> ¬ {<op>[6:0], 0}
SL shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).
C: set if the MSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = 01001010b, R1 = 10100101b
SL
SL
R0
R1
// N flag is set to ‘1’, R0 ¬ 10010100b
// C flag is set to ‘1’, R1 ¬ 01001010b
8-90
S3CB519
INSTRUCTION SET
SLA— Shift Left Arithmetic
Format:
Operation:
Flags:
SLA <op>
<op>: GPR
C ¬ <op>[7], <op> ¬ {<op>[6:0], 0}
SLA shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).
C: set if the MSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
V: set if the MSB of the result is different from C. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = AAh
SLA
R0
// C, V, N flags are set to ‘1’, R0 ¬ 54h
8-91
INSTRUCTION SET
S3CB519
SR— Shift Right
Format:
SR <op>
<op>: GPR
Operation:
C ¬ <op>[0], <op> ¬ {0, <op>[7:1]}
SR shifts <op> to the right by 1 bit. The LSB of the original <op> (i.e., <op>[0]) is copied into carry
(C).
Flags:
C: set if the LSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
Example:
Given: R0 = 01011010b, R1 = 10100101b
SR
SR
R0
R1
// No change of flags, R0 ¬ 00101101b
// C flag is set to ‘1’, R1 ¬ 01010010b
8-92
S3CB519
INSTRUCTION SET
SRA— Shift Right Arithmetic
Format:
SRA <op>
<op>: GPR
Operation:
C ¬ <op>[0], <op> ¬ {<op>[7], <op>[7:1]}
SRA shifts <op> to the right by 1 bit while keeping the sign of <op>. The LSB of the original <op>
(i.e., <op>[0]) is copied into carry (C).
Flags:
C: set if the LSB of <op> (before shifting) is 1. Reset if not.
Z: set if result is zero. Reset if not.
N: set if the MSB of <op> (after shifting) is 1. Reset if not.
NOTE:
SRA keeps the sign bit or the MSB (<op>[7]) in its original position. If SRA is executed ‘N’ times, N
significant bits will be set, followed by the shifted bits.
Example:
Given: R0 = 10100101b
SRA
SRA
SRA
SRA
R0
R0
R0
R0
// C, N flags are set to ‘1’, R0 ¬ 11010010b
// N flag is set to ‘1’, R0 ¬ 11101001b
// C, N flags are set to ‘1’, R0 ¬ 11110100b
// N flags are set to ‘1’, R0 ¬ 11111010b
8-93
INSTRUCTION SET
S3CB519
STOP — Stop Operation (pseudo instruction)
Format:
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter the STOP mode. In the STOP mode, the contents of the on-chip CPU
registers, peripheral registers, and I/O port control and data register are retained. A reset operation
or external or internal interrupts can release stop mode. The STOP instruction is a pseudo
instruction. It is assembled as “SYS #0Ah”, which generates the SYSCP[7-0] signals. These
signals are decoded and stop the operation.
NOTE:
The next instruction of STOP instruction is executed, so please use the NOP instruction after the
STOP instruction.
Example:
STOP
NOP
NOP
NOP
·
·
·
In this example, the NOP instructions provide the necessary timing delay for oscillation stabilization
before the next instruction in the program sequence is executed. Refer to the timing diagrams of
oscillation stabilization, as described in Figure 18-3, 18-4
8-94
S3CB519
INSTRUCTION SET
SUB— Subtract
Format:
Operation:
Flags:
SUB <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
<op1> ¬ <op1> + ~<op2> + 1
SUB adds the value of <op1> with the 2's complement of <op2> to perform subtraction on
<op1> and <op2>
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 0150h, DM[0143h] = 26h, R0 = 52h, R1 = 14h, eid = 1
SUB
SUB
SUB
R0, 43h
R1, #16h
R0, R1
// R0 ¬ R0 + ~DM[0143h] + 1 = 2Ch
// R1 ¬ FEh, N flag is set to ‘1’
// R0 ¬ R0 + ~R1 + 1 = 3Eh
SUB
SUB
SUB
SUB
R0, @ID0+1
R0, @[ID0-2]
R0, @[ID0+3]!
R0, @[ID0-2]!
// R0 ¬ R0 + ~DM[0150h] + 1, IDL0 ¬ 51h
// R0 ¬ R0 + ~DM[014Eh] + 1, IDL0 ¬ 4Eh
// R0 ¬ R0 + ~DM[0153h] + 1, IDL0 ¬ 50h
// R0 ¬ R0 + ~DM[014Eh] + 1, IDL0 ¬ 50h
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed
explanation about this addressing mode. The example in the SBC description shows how SUB and
SBC can be used in pair to subtract a 16-bit number from another.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-95
INSTRUCTION SET
S3CB519
SWAP— Swap
Format:
SWAP <op1>, <op2>
<op1>: GPR
<op2>: SPR
Operation:
<op1> ¬ <op2>, <op2> ¬ <op1>
SWAP swaps the values of the two operands.
–
Flags:
NOTE:
Among the SPRs, SR0 and SR1 can not be used as <op2>.
Given: IDH:IDL0 = 8023h, R0 = 56h, R1 = 01h
Example:
SWAP
SWAP
R1, IDH
R0, IDL0
// R1 ¬ 80h, IDH ¬ 01h
// R0 ¬ 23h, IDL0 ¬ 56h
After execution of instructions, index registers IDH:IDL0 (ID0) have address 0156h.
8-96
S3CB519
INSTRUCTION SET
SYS — System
Format:
Operation:
Flags:
SYS #imm:8
SYS generates SYSCP[7:0] and nSYSID signals.
–
NOTE:
Mainly used for system peripheral interfacing.
Example:
SYS
SYS
#0Ah
#05h
In the first example, statement “SYS #0Ah” is equal to STOP instruction and second example “SYS
#05h” is equal to IDLE instruction. This instruction does nothing but increase PC by one and
generates SYSCP[7:0] and nSYSID signals.
8-97
INSTRUCTION SET
S3CB519
TM — Test Multiple Bits
Format:
TM <op>, #imm:8
<op>: GPR
Operation:
Flags:
TM performs the bit-wise AND operation on <op> and imm:8 and sets the flags. The content of
<op> is not changed.
Z: set if result is zero. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: R0 = 01001101b
TM
R0, #00100010b
// Z flag is set to ‘1’
8-98
S3CB519
INSTRUCTION SET
XOR— Exclusive OR
Format:
XOR <op1>, <op2>
<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm
Operation:
<op1> ¬ <op1> ^ <op2>
XOR performs the bit-wise exclusive-OR operation on <op1> and <op2> and stores the result in
<op1>.
Flags:
Z: set if result is zero. Reset if not.
N: set if result is negative. Reset if not.
Example:
Given: IDH:IDL0 = 8080h, DM[8043h] = 26h, R0 = 52h, R1 = 14h, eid = 1
XOR
XOR
XOR
R0, 43h
// R0 ¬ 74h
// R1 ¬ 38h
// R0 ¬ 46h
R1, #00101100b
R0, R1
XOR
XOR
XOR
XOR
R0, @ID0
// R0 ¬ R0 ^ DM[8080h], IDL0 ¬ 81h
// R0 ¬ R0 ^ DM[807Eh], IDL0 ¬ 7Eh
// R0 ¬ R0 ^ DM[8083h], IDL0 ¬ 80h
// R0 ¬ R0 ^ DM[807Bh], IDL0 ¬ 80h
R0, @[ID0-2]
R0, @[ID0+3]!
R0, @[ID0-5]!
In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 8-5 for more detailed
explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)
8-99
INSTRUCTION SET
S3CB519
NOTES
8-100
S3CB519
CLOCK CIRCUIT
9
CLOCK CIRCUIT
OVERVIEW
The S3CB519 microcontroller has two oscillator circuits: a main system clock circuit and a subsystem clock circuit.
The CPU and peripheral hardware operate at the system clock frequency supplied by these circuits.
The maximum CPU clock frequency is determined by PCON register setting.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— External crystal or ceramic resonator oscillation source (or an external clock source)
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (f
divided by 1, 2, 4, 8, 16, 32, 64, 128)
OSC
— System clock control register, PCON
9-1
CLOCK CIRCUIT
S3CB519
Stop Release
Stop Release
INT
INT
Dividing
Ability
OSCCON.4
Sub-System
Oscillator
Circuit
Main-System
Oscillator
Circuit
Watch Timer
fx
fxt
Selector 1
fxx
Stop
OSCCON.2
OSCCON.3
OSCCON.0
Stop
1/1 - 1/4096
Frequency
Dividing
Circuit
Peripheral
1/1
1/2 1/4 1/8 1/16 1/32 1/64 1/128
PCON.2 - .0
Selector 2
CPU
CPU Stop Signal
by Idle or Stop
Oscillator
Control
Circuit
SYS #05H
SYS #0AH
Idle
Stop
Figure 9-1. System Clock Circuit Diagram
9-2
S3CB519
CLOCK CIRCUIT
Power Control Register (PCON)
02H, R/W, Reset: 04H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
System clock selection bits:
000 = fxx/128
001 = fxx/64
010 = fxx/32
011 = fxx/16
100 = fxx/8
101 = fxx/4
110 = fxx/2
111 = fxx/1
Figure 9-2. Power Control Register (PCON)
Oscillator Control Register (OSCCON)
03H, R/W, Reset: 00H
MSB .7
.6
.5
.4
.3
.2
.1
.0 LSB
System clock source selection bits:
0 = Mainsystem oscillator select
1 = Subsystem oscillator select
Not used
Not used
Subsystem oscillator control bits:
0 = Subsystem oscillator RUN
1 = Subsystem oscillator STOP
Mainsystem oscillator control bits:
0 = Mainsystem oscillator RUN
1 = Mainsystem oscillator STOP
Subsystem oscillator driving ability selection bits:
0 = Strong drive
1 = Normal drive
NOTE:
The oscillator selected by the OSCCON.0 can be stopped only by the "stop"
instruction. It cannot be stopped by the OSCCON settings.
Figure 9-3. Oscillator Control Register (OSCCON)
9-3
CLOCK CIRCUIT
S3CB519
NOTES
9-4
S3CB519
nRESET AND POWER-DOWN
10 nRESET AND POWER-DOWN
OVERVIEW
During a power-on reset, the voltage at V goes to High level and the nRESET pin is forced to Low level.
DD
The reset signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock.
This procedure brings S3CB519 into a known operating status.
For the time for CPU clock oscillation to stabilize, the nRESET pin must be held to low level for a minimum time
interval after the power supply comes within tolerance. (For the minimum time interval, see the electrical
characteristic).
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watchdog function (basic timer) is enabled.
— Ports are set to input mode except port 5 which is set to output mode.
— Peripheral control and data registers are disabled and reset to their default hardware values.
— The program counter (PC) is loaded with the program reset address in the ROM, 00000H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 00000H is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, make the appropriate settings to the
watchdog timer control register, WDTCON, before entering STOP mode.
10-1
nRESET AND POWER-DOWN
S3CB519
NOTES
10-2
S3CB519
I/O PORTS
11 I/O PORTS
OVERVIEW
The S3CB519 has five I/O ports (P0–P4) for general I/O and one output port (P5) dedicated for the key-strobe with
LCD segment data.
PORT 0
Two 8-bit control registers are used to configure the port 0 pins: P0CONH for pins P0.4–P0.6 and P0CONL for pins
P0.0–P0.3. Each byte contains four bit-pairs and each bit-pair configures one pin. The P0CONH and the P0CONL
registers also control the alternative functions.
For example, when bits 4 and 5 of P0CONL are “00”, P0.2 is selected for the input mode.
In this mode, you can set P0.2 as a normal input or an interrupt 2 or a timer 0 clock input by controlling P0INT and
T0CON.
P0INT and P0EDGE registers control the interrupt functions for INT0–INT6.
Port 0 Control Register, Low Byte (P0CONL)
21H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.1/INT1/T0/
T0CAP/
P0.3/INT3/ P0.2/INT2/
TACK/BLD T0CK/BUZ
P0.0/INT0/TB
T0PWM
P0CONL bit-pair pin configuration settings:
0 0
0 1
1 0
1 1
Input mode
(INT0 for P0.0, INT1/T0CAP for P0.1, INT2/T0CK for P0.2, INT3/TACK for P0.3)
Input mode, pull-up
(INT0 for P0.0, INT1/T0CAP for P0.1, INT2/T0CK for P0.2, INT3/TACK for P0.3)
Alternative mode
(TB for P0.0, T0/T0PWM for P0.1, BUZ for P0.2, BLD for P0.3)
Output mode, push-pull
Figure 11-1. Port 0 Low-byte Control Register (P0CONL)
11-1
I/O PORTS
S3CB519
Port 0 Control Register, High Byte (P0CONH)
20H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used P0.6/INT6/SI P0.5/INT5/SO P0.4/INT4/SCK
P0CONH bit-pair pin configuration settings:
0 0
0 1
1 0
1 1
Input mode
(INT4/SCK input for P0.4, INT5 for P0.5, INT6/SI for P0.6)
Input mode, pull-up
(INT4/SCK input for P0.4, INT5 for P0.5, INT6/SI for P0.6)
Alternative mode
(SCK output for P0.4, SO for P0.5, High-impedance for P0.6)
Output mode, push-pull
Figure 11-2. Port 0 High-byte Control Register (P0CONH)
Port 0 Interrupt Control Register (P0INT)
22H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
P0.0/INT0
P0.1/INT1
P0.6/INT6
P0.2/INT2
P0.5/INT5
P0.4/INT4
P0INT bit settings:
P0.3/INT3
0
1
Disable interrupt
Enable interrupt
Figure 11-3. Port 0 Interrupt Control Register (P0INT)
11-2
S3CB519
I/O PORTS
Port 0 Interrupt Edge Control Register (P0EDGE)
23H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
P0.0/INT0
P0.1/INT1
P0.6/INT6
P0.2/INT2
P0.5/INT5
P0.3/INT3
P0.4/INT4
P0EDGE bit settings:
0
1
Falling edge detection
Rising edge detection
Figure 11-4. Port 0 Interrupt Edge Control Register (P0EDGE)
11-3
I/O PORTS
PORT 1
S3CB519
P1CON contains four bit-pairs and bit-pair configures one pin. P1INT controls the interrupt function for KS0–KS3.
When the alternative mode is selected, KS0–KS3 can be used as key scan inputs with P5 (shared with LCD SEG)
strobe.
Port 1 Control Register (P1CON)
24H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.3/KS3
P1.2/KS2
P1.1/KS1
P1.0/KS0
P1CON bit-pair pin configuration settings:
0 0
0 1
1 0
Input mode (KSx interrupt)
Input mode, pull-up (KSx interrupt)
Alternative mode
- When key strobe is off (P5CON.7 = 'Low'), High-impedance
- Else other state: Key scan mode (KSx interrupt)
Output mode, push-pull
1 1
Figure 11-5. Port 1 Control Register (P1CON)
Port 1 Interrupt Control Register (P1INT)
25H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.3/KS3
P1.2/KS2
P1.1/KS1
P1.0/KS0
P1INT bit-pair pin configuration settings:
0 x
1 0
1 1
Interrupt disable
Interrupt enable, falling edge detection
Interrupt enable, rising edge detection
NOTE:
When key scan mode, P1INT setting has no meaning
Figure 11-6. Port 1 Interrupt Control Register (P1INT)
11-4
S3CB519
PORT 2
I/O PORTS
P2CON and P3CON contain two nibbles each and each nibble configures four pins.
Port 2 is shared by SEG48–SEG55, and Port 3 is shared by SEG40–SEG47.
Port 2 Control Register (P2CON)
28H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
High nibble port configuration Lower nibble port configuration
(P2.4/SEG51-P2.7/SEG48) (P2.0/SEG55-P2.3/SEG52)
P2CON pin configuration settings: (bit7, 6, 5, 4 or bit3, 2, 1, 0)
x000 Input mode
x001 Input mode, pull-up
x010 Output mode, push-pull
x011 Output mode, open-drain
x1xx
LCD Segment (SEG55-SEG52 for P2.0-P2.3 or SEG51-SEG48 for P2.4-P2.7)
Figure 11-7. Port 2 Control Register (P2CON)
PORT 3
Port 3 Control Register (P3CON)
2CH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
High nibble port configuration Lower nibble port configuration
(P3.4/SEG43-P3.7/SEG40) (P3.0/SEG47-P3.3/SEG44)
P3CON pin configuration settings: (bit7, 6, 5, 4 or bit3, 2, 1, 0)
x000 Input mode
x001 Input mode, pull-up
x010 Output mode, push-pull
x011 Output mode, open-drain
x1xx
LCD Segment (SEG47-SEG44 for P3.0-P3.3 or SEG43-SEG40 for P3.4-P3.7)
Figure 11-8. Port 3 Control Register (P3CON)
11-5
I/O PORTS
PORT 4
S3CB519
P4CON contains two nibbles and each nibble configures four pins.
Port 4 is shared by COM8–COM15, and I/O and COM switching are up to LMOD register.
Port 4 Control Register (P4CON)
30H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
High nibble port configuration Lower nibble port configuration
(P4.4/COM12-P4.7/COM15) (P4.0/COM8-P4.3/COM11)
P4CON pin configuration settings: (bit7, 6, 5, 4 or bit3, 2, 1, 0)
Input mode
xx00
xx01
xx10
xx11
Input mode, pull-up
Output mode, push-pull
Output mode, open-drain
NOTE:
P4.0-P4.7 can be converted to COM8-COM15 according to LMOD setting.
If only COM0-COM11 are selected as COM, COM12-COM15 are normal ports.
If only COM0-COM7 are selected as COM, COM8-COM15 are normal ports.
Figure 11-9. Port 4 Control Register (P4CON)
11-6
S3CB519
PORT 5
I/O PORTS
Port 5 , which has 15 pins, can be controlled by P5CON but cannot be used as normal I/O.
Port 5 is shared by SEG pins and makes the key-strobe. (for details, see LCD chapter).
When port 1 is selected as the alternative mode (key scan input) and the key strobe function of port 5 is enabled,
port 5 data register has the key-strobe value of the time when the key scan interrupt occurs.
For example, when P5.3 outputs strobe and any of port 1 are “Low”-state, forcing the key scan interrupt, port 5 data
register has the value "3". For P5.9, port 5 data register has "9".
Port 5 Control Register (P5CON)
34H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Key strobe selection bits:
0 0
0 1
1 0
1 1
P5.0-P5.15 as key strobe
Key strobe enable bit:
P5.0-P5.11 as key strobe
P5.0-P5.7 as key strobe
P5.0-P5.3 as key strobe
0
1
Disable key strobe
Enable key strobe
Strobe duration:
0
1
1.5/fw-45 usec
2/fw-64 usec
Interval between strobes:
0 0
0 1
1 0
1 1
32/fw-1 msec
64/fw-2 msec
128/fw-4 msec
256/fw-8 msec
P5 output mode:
0
1
Push-pull output
Open-drain output
NOTE:
fw is watch timer input clock (fw = 32768 Hz)
Figure 11-10. Port 5 Control Register (P5CON)
11-7
I/O PORTS
S3CB519
NOTES
11-8
S3CB519
BASIC TIMER/WATCHDOG TIMER
12 BASIC TIMER/WATCHDOG TIMER
OVERVIEW
WDTCON controls basic timer clock selection and watchdog timer clear bit.
Basic timer is used in two different ways:
·
As a clock source to watchdog timer to provide an automatic reset mechanism in the event of a system
malfunction (When watchdog function is enabled in ROM code option)
·
To signal the end of the required oscillation stabilization interval after a reset or stop mode release.
The reset value of basic timer clock selection bits is decided by the ROM code option. (see the section on ROM
code option for details). After reset, programmer can select the basic timer input clock using WDTCON.
Watchdog timer provides an automatic reset mechanism in the event of a system malfunction (When watchdog
function is enabled in ROM code option)
When watchdog function is enabled by the ROM code option, programmer must set WDTCON.0 periodically within
every 2048 ´ basic timer input clock time to prevent system reset.
Watchdog Timer Control Register (WDTCON)
0DH, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Not used
Not used
Watchdog timer clear bit:
0 = Not applicable
1 = clear watchdog timer counter
Basic timer counter clock selection bits:
000 = fxx/2
001 = fxx/4
010 = fxx/16
011 = fxx/32
100 = fxx/128
101 = fxx/256
110 = fxx/1024
111 = fxx/2048
Figure 12-1. Watchdog Timer Control Register (WDTCON)
12-1
BASIC TIMER/WATCHDOG TIMER
S3CB519
BLOCK DIAGRAM
Data Bus
RCOD_OPT .14 .13 .12
nRESET
MUX
WDTCON .6 .5 .4
Reset or Stop
1/2048
Data Bus
1/1024
1/256
1/128
1/32
1/16
1/4
Clear
BT OVF
BT INT
(note)
fb
8-bit Basic Counter
(Read Only)
MUX
1/2
OVF
3-bit Watchdog
RCOD_OPT .11
Timer Counter
clear
WDTCON .0
Reset
STOP
IDLE
NOTE: CPU start signal (32/fb)
(Power down release)
Figure 12-2. Basic Timer & Watchdog Timer Functional Block Diagram
12-2
S3CB519
WATCH TIMER
13 WATCH TIMER
OVERVIEW
Watch timer functions include real-time and watch-time measurements.
After the watch timer starts and time elapses, the watch timer interrupt is automatically set to "1", and interrupt
requests commence in 3.91 ms, 0.25 s, 0.5 s or 1 second.
The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz or 4 kHz signal to the BUZ output when the main
system clock frequency is 4.19 MHz. The watch timer supplies the clock frequency for the LCD controller (f
)
LCD
and BLD. Therefore, if the watch timer is disabled, the LCD and BLD controller do not operate.
— Real-time and Watch-time measurements
— Clock source generation for LCD controller
— Buzzer output frequency generator
Table 13-1. Watch Timer Control Register (WTCON): 8-Bit R/W
Bit Name
WTCON.7
Values
Function
Address
–
–
Not used
Not used
70H
WTCON.6
WTCON .5–.4
0
0
1
0
1
0
1
0
1
0.5 kHz buzzer (BUZ) signal output
1 kHz buzzer (BUZ) signal output
0
1
1
0
0
1
1
2 kHz buzzer (BUZ) signal output
4 kHz buzzer (BUZ) signal output
WTCON .3–.2
Set watch timer interrupt to 1 sec.
Set watch timer interrupt to 0.5 sec.
Set watch timer interrupt to 0.25 sec.
Set watch timer interrupt to 3.91 ms.
Selects (fx/128 or fx/64 ) as the watch timer clock
Selects the subsystem clock as watch timer clock
WTCON.1
WTCON.0
0
1
0
Stops the watch timer counter; clears the frequency dividing
circuits
1
Runs the watch timer counter
NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz.
13-1
WATCH TIMER
S3CB519
WATCH TIMER CIRCUIT DIAGRAM
WTCON .4 .5
fw/26 (0.5 kHz)
fw/25 (1 kHz)
fw/24 (2 kHz)
Buzzer Output
MUX
fw/23 (4 kHz)
fw/27
fxt
fw/213
fw/214
fw
32768 Hz
WTINT
Selector
Circuit
Clock
Selector
Frequency
Dividing
Circuit
fx/128
fx/64
fw/215 (1 H
fw/23
Z)
fLCD
Enable/Disable
WTCON .0
LMOD.0
WTCON .1
WTCON .2 .3
fx = Main system clock (4.19 MHz)
fxt = Subsystem clock (32768 Hz)
fw = Watch timer clock
Figure 13-1. Watch Timer Circuit Diagram
13-2
S3CB519
16-BIT TIMER (8-BIT TIMER A & B)
14 16-BIT TIMER (8-BIT TIMER A & B)
OVERVIEW
The 16-bit timer is used in one 16-bit timer or two 8-bit timers. When Bit 2 of TBCON is "1" , it operates as one 16-bit
timer. When it is “0”, it operates as two 8-bit timers. When it operates as one 16-bit timer, the TBCNT’s clock
source can be selected by setting TBCON.3. If TBCON.3 is “0”, the timer A’s overflow would be TBCNT’s clock
source. If it is “1”, the timer A’s interval out would be TBCNT’s clock source. The timer clock source can be
selected by the S/W.
Timer A Control Register (TACON)
40H, R/W, Reset: 00H
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Timer A operation enable bit:
0 = Stop
Not used
Not used
1 = Run
Timer A input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
Timer A counter clear bit:
0 = No effect
1 = Clear the timer A (when write)
1x0 = fxx/1
1x1 = TACLK
NOTE: 8-Bit Timer A is only available when TBCON.2 is setted "0" for 8-Bit operation mode.
Figure 14-1. Timer A Control Register (TACON)
INTERVAL TIMER FUNCTION
The timer A&B module can generate an interrupt: the Timer A and/or Timer B match interrupt (TAINT, TBINT). In
interval timer mode, a match signal is generated when the counter value is identical to the value written to the
reference data register, TADATA/TBDATA. The match signal generates Timer A and/or Timer B match interrupt and
clears the counter.
TB pin can be toggled whenever the timer B match interrupt occurs if I/O port setting is appropriate.
14-1
16-BIT TIMER (8-BIT TIMER A & B)
S3CB519
Timer B Control Register (TBCON)
44H, R/W, Reset: 00H
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Timer B operation enable bit:
0 = Stop
Not used
1 = Run
Timer B input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
Timer B counter clear bit:
0 = No effect
1 = Clear the timer B (when write)
1x0 = fxx/4
1x1 = TBCLK (Not used in this
device-no input clock)
Timer B mode selection bit:
0 = 8-bit operation mode
1 = 16-bit operation mode
When 16 bit operation Timer B input clock selection bit:
0 = Timer A overflow out
1 = Timer A interval out
NOTE: At 16-bit operation mode 16-bit counter clock input is selected by TACON .6, .5, .4
Figure 14-2. Timer B Control Register (TBCON)
14-2
S3CB519
16-BIT TIMER (8-BIT TIMER A & B)
Data Bus
8
TACON.1
TBCON.1
TBCON.2
TBCON.0
Timer A Data Register
(Read/Write)
MUX
TBCON.2
TBCON.3
TACON.0
TACON.6,.5,.4
Timer A Buffer Register
8-Bit Comparator
0
1
0
1
fxx/1024
fxx/256
MUX
MUX
fxx/64
fxx/8
M
U
X
Clear
TACNT (8-Bit
Up-Counter, Read Only)
TAINT
fxx/1
TACLK
0
1
MUX
TBCON.3
TBCON.2
TBCON.6,.5,.4
8-Bit Comparator
fxx/1024
fxx/256
fxx/64
fxx/8
M
U
X
TBCNT (8-Bit
Up-Counter, Read Olny)
Clear
1
0
MUX
MUX
1
0
fxx/4
TBOUT
TBINT
Interval
Output Gen.
TBCLK
Timer B Buffer Register
TBCON.2
TBCON.0
Timer B Data Register
(Read/Write)
TBCON.1
TBCON.2
TBCON.3
8
Data Bus
Figure 14-3. Timer A, B Function Block Diagram
14-3
16-BIT TIMER (8-BIT TIMER A & B)
S3CB519
NOTES
14-4
S3CB519
8-BIT TIMER (TIMER 0)
15 8-BIT TIMER (TIMER 0)
OVERVIEW
The 8-bit timer 0 is an 8-bit general-purpose timer/counter. Timer 0 has three operating modes, one of which you
select using the appropriate T0CON setting:
— Interval timer mode (Toggle output at T0 pin)
— Capture input mode with a rising or falling edge trigger at the T0CAP pin
— PWM mode (T0PWM)
15-1
8-BIT TIMER (TIMER 0)
S3CB519
FUNCTION DESCRIPTION
Timer 0 Interrupts
The Timer 0 module can generate two interrupts: the Timer 0 overflow interrupt (T0OVF), and the Timer 0 match/
capture interrupt (T0INT).
Interval Timer Function
The Timer 0 module can generate an interrupt: the Timer 0 match interrupt (T0INT).
In interval timer mode, a match signal is generated(,) and T0 is toggled when the counter value is identical to the
value written to the T0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt and
clears the counter.
If, for example, you write the value 10H to T0DATA and 0AH to T0CON, the counter will increment until it reaches
10H. At this point, the T0 interrupt request is generated and the counter value is reset and counting resumes.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM
pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to
the Timer 0 data register. In PWM mode, however, the match signal does not clear the counter but can generate a
match interrupt. The counter runs continuously, overflowing at FFH, and then repeats the incrementing from 00H.
Whenever an overflow occurs, an overflow(OVF) interrupt can be generated.
Although you can use the match or the overflow interrupt in PWM mode, interrupts are not typically used in PWM-
type applications. Instead, the pulse at the T0PWM pin is held to High level as long as the reference data value is
less than or equal to ( £ ) the counter value, and then the pulse is held to Low level for as long as the data value is
greater than ( > ) the counter value. One pulse width is equal to t
´ 256.
CLK
Capture Mode
In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value
into the T0 data register. You can select the rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by
setting the value of the Timer 0 capture input selection bit in the port control register.
Both kinds of Timer 0 interrupts can be used in capture mode: the Timer 0 overflow interrupt is generated whenever a
counter overflow occurs; the Timer 0 match/capture interrupt is generated whenever the counter value is loaded into
the T0 data register.
By reading the captured data value in T0DATA and assuming a specific value for the Timer 0 clock frequency, you
can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin.
15-2
S3CB519
8-BIT TIMER (TIMER 0)
TIMER 0 CONTROL REGISTER (T0CON)
You use the Timer 0 control register, T0CON, to
·
·
·
·
Select the Timer 0 operating mode (interval timer, capture mode, or PWM mode)
Select the Timer 0 input clock frequency
Clear the Timer 0 counter, T0CNT
Enable the Timer 0 overflow interrupt or Timer 0 match/capture interrupt
A reset clears T0CON to '00H'. This sets Timer 0 to normal interval timer mode, selects an input clock frequency of
/1024, and disables all Timer 0 interrupts. You can clear the Timer 0 counter at any time during normal operation
f
OSC
by writing a "1" to T0CON.3.
Timer 0 Control Register (T0CON)
50H, R/W, Reset: 00H
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Not used
Timer 0 input clock selection bits:
00 = fxx/1024
01 = fxx/256
10 = fxx/64
11 = External clock (T0CK)
Timer 0 match/capture interrupt enable bit:
0 = Disable
1 = Enable
Timer 0 operating mode selection bits:
00 = Interval mode (T0)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (Match & OVF interrupt
can occur)
Timer 0 overflow interrupt enable
bit:
0 = Disable
1 = Enable
Timer 0 counter clear bit:
0 = No
1 = Clear the timer 0 counter (when write)
Figure 15-1. Timer 0 Control Register (T0CON)
15-3
8-BIT TIMER (TIMER 0)
BLOCK DIAGRAM
S3CB519
T0CON.2
T0CON. 7-.6
Data Bus
8
T0OVF
OVF
1/1024
1/256
1/64
fxx
DIV
Clear
T0CON.3
T0CON.1
8-Bit Up Counter
(Read-Only)
MUX
R
T0CK
M
U
X
8-Bit Comparator
T0INT
Match
T0OUT
T0PWM
T0CAP
T0CON. 5-.4
Timer 0 Buffer Reg
T0CON. 5-.4
Counter Clear Signal
Match
Timer 0 Data
Register
8
Data Bus
Figure 15-2. Timer 0 Functional Block Diagram
15-4
S3CB519
SERIAL I/O INTERFACE
16 SERIAL I/O INTERFACE
OVERVIEW
The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
PROGRAMMING PROCEDURE
To program the SIO modules, follow these basic steps:
1. Configure the I/O pins at port (SO,nSCK, SI) by loading the appropriate value to the P0CONH register, if
necessary.
2. Load an 8-bit value to the SIOCON register to properly configure the serial I/O module. In this operation,
SIOCON.2 must be set to "1" to enable the data shifter.
3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.1) to "1".
4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation
starts.
5. When the shift operation (transmit/receive) is completed, the SIO pending bit is set to "1", and a SIO interrupt
request is generated.
16-1
SERIAL I/O INTERFACE
S3CB519
SIO CONTROL REGISTER (SIOCON)
Serial I/O Module Control Registers (SIOCON)
48H, R/W, Reset: 00H
MSB
LSB
.7
.6
.5
.4
.3
.2
.1
.0
SIO shift clock select bit:
0 = Internal clock (P.S clock)
1 = External clock (SCK)
Not used
SIO interrupt enable bit:
0 = Disable SIO interrupt
1 = Enable SIO interrupt
Data direction control bit:
0 = MSB-first
1 = LSB-first
SIO shift operation enable bit:
0 = Disable shifter and clock
1 = Enable shfter and clock
SIO mode selction bit:
0 = Rececive-only mode
1 = Transmit/receive mode
Shift clock edge selction bit:
0 = Tx at falling edges, Rx at rising
SIO counter clear and shift start bit:
0 = No action
1 = Tx at rising edges, Rx at falling
1 = Clear 3-bit counter and start shifting
Figure 16-1. Serial I/O Control Register (SIOCON)
16-2
S3CB519
SERIAL I/O INTERFACE
SIO PRE-SCALER REGISTER (SIOPS)
The values stored in the SIO pre-scaler registers, SIOPS, lets you determine the SIO clock rate (baud rate) as
follows:
Baud rate = Input clock/(Pre-scaler value + 1), or SCLK input clock
where the input clock is fxx/4
SIO Pre-scaler Register (SIOPS)
49H,R/W
MSB
LSB
.7
.6
.5
.4
.3
.2
.1
.0
Baud rate = (fxx /4)/(SIOPS + 1)
Figure 16-2. SIO Pre-scaler Register (SIOPS)
BLOCK DIAGRAM
3-Bit Counter
SIO INT
CLK
Clear
SIOCON.1
(Interrupt Enable)
SIOCON.3
SIOCON.7
(Shift Clock
Source Select)
SIOCON.4
(Edge Select)
SIOCON.2
(Shift Enable)
SIOCON.5
(Mode Select)
SCLK
SIOPS
MUX
CLK
8-Bit SIO Shift Buffer
SO
(SIODATA)
fxx/2
8-Bit P.S
1/2
SIOCON.6
(LSB/MSB First
Prescaled Value = 1/(SIOPS + 1)
Mode Select)
8
SI
Data Bus
Figure 16-3. SIO Functional Block Diagram
16-3
SERIAL I/O INTERFACE
S3CB519
SERIAL I/O TIMING DIAGRAMS
nSCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQS
Set SIOCON.3
Figure 16-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
nSCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI
SO
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
IRQS
Set SIOCON.3
Figure 16-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
16-4
S3CB519
BATTERY LEVEL DETECTOR
17 BATTERY LEVEL DETECTOR
OVERVIEW
The S3CB519 microcontroller has a built-in BLD (Battery Level Detector) circuit which allows detection of
power voltage drop of an external input level or internal V
DD.
When external input is selected by P0CONL, detection voltage level can be adjusted through the external divided
resistors ratio on BLD pin. Internal reference voltage is 1.2 V.
After detection, BLD is automatically disabled, and EOBLD bit is set.
Because the clock for BLD comes from the watch timer, watch timer must be enabled to use BLD.
BLDCON.3, .2, .1
S3CB519
Internal
VDD
P0CONL.7, .6
Criteria
Voltage
Setting
Circuit
M
U
VIN
X
-
BLD Result
(EOBLD)
External
+
VDD
VREF
VDD
BLD Pin
C1
VREF
BGR
External resistor for adjusting
detected voltage level
NOTES:
1. Internal reference voltage (VREF) = 1.2 V
2. C1 = 0.1
mF
Figure 17-1. Voltage Level Detection Circuit
17-1
BATTERY LEVEL DETECTOR
S3CB519
Battery Level Detector Control Register (BLDCON)
71H, R/W, Reset: 40H
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
BLD circuit on/off bit-auto clear:
0 = BLD circuit off
Not used
1 = BLD circuit on
EOBLD (End of BLD)-read only:
0 = On processing
1 = End of BLD
Select BLD criteria voltage bit:
010 = 2.4 V
BLD result bit-read only:
_
011 = 2.7 V
0 = criteria voltage < source voltage (VDD-VSS
)
100 = 3.0 V
101 = 3.3 V
1 = criteria voltage > source voltage (VDD-VSS
)
110 = 4.0 V
111 = 4.5 V
Figure 17-2. Battery Level Detector Control Register (BLDCON)
17-2
S3CB519
LCD CONTROLLER/DRIVER
18 LCD CONTROLLER/DRIVER
OVERVIEW
This microcontroller can directly drive the (56 segments ´ 16 commons) LCD panel. Data written to the LCD display
RAM can be transferred to the segment signal pins automatically without program control.
When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during Idle modes.
LCD RAM ADDRESS AREA
LCD RAM can be addressed by 8-bit RAM access instructions. When the bit value of a display segment is "1", the
LCD display is turned on; when the bit value is "0", the display is turned off.
Display RAM data are sent out through segment pins SEG0–SEG55 using a direct memory access (DMA) method
that is synchronized with the f
signal. RAM addresses in this location that are not used for the LCD display can
LCD
be allocated to general-purpose use.
LCD RAM (RAM BANK 12)
S
E
G
0
S
E
G
1
S
E
G
S
E
G
54
55
bit0
bit1
bit2
COM0
COM1
COM2
80H
82H
ECH
EEH
COM7
COM8
COM9
bit7
bit0
bit1
81H
83H
EDH
EFH
COM15
bit7
Figure 18-1. LCD Display Data RAM Organization
18-1
LCD CONTROLLER/DRIVER
S3CB519
LCD CONTROL REGISTER (LCON)
LCON controls LCD dividing resistor and LCD display.
LCD Control Register (LCON)
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Not used
Not used
LCD segment signal control bit:
00 = All LCD COM/SEG is ground and LCD clock off, TR1 off
01 = All LCD dots off, TR1 on
10 = All LCD dots on, TR1 on
11 = Normal LCD display, TR1 on
LCD dividing resistors selection bit:
0 = Normal LCD dividing resistors (R = 55 kohm)
1 = Diminish LCD dividing resistors (R = 28 kohm)
Figure 18-2. LCD Control Register (LCON)
LCD VOLTAGE DIVIDING RESISTORS
VDD
VDD
S3CB519 (1/5 Bias)
S3CB519 (1/4 Bias)
LCON.1, .2
TR1
LCON.1, .2
TR1
LCNST.0-3
LCNST.0-3
LCNST.7
LCNST.7
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
R
R
R
R
R
R
R
R
R
R
V
SS
VSS
VSS
VSS
Figure 18-3. Internal Voltage Dividing Resistor Connection
18-2
S3CB519
LCD CONTROLLER/DRIVER
LCD MODE REGISTER (LMOD)
LMOD controls LCD bias, duty, and clock.
LCD Mode Register (LMOD)
.5 .4 .3 .2
.7
.6
.1
.0
MSB
LSB
Not used
Not used
Bias selection bits:
0 = 1/4 bias
1 = 1/5 bias
Duty selection bits:
00 = 1/8 duty (COM0-COM7 select)
01 = 1/12 duty (COM0-COM11 select)
1x = 1/16 duty (COM0-COM15 select)
LCD Clock (LCDCK)
1/8 duty (COM0-7)
fw/27 (256 Hz)
fw/26 (512 Hz)
fw/25 (1024 Hz)
fw/24 (2048 Hz)
1/12 duty (COM0-11)
fw/26 (512 Hz)
1/16 duty (COM0-15)
fw/26 (512 Hz)
00
01
10
11
fw/25 (1024 Hz)
fw/24 (2048 Hz)
fw/23 (4096 Hz)
fw/25 (1024 Hz)
fw/24 (2048 Hz)
fw/23 (4096 Hz)
Watch timer (fw) selection bits:
(When main system clock is supplied to the watch timer source.)
0 = fLCD = 4096 Hz when fw = fx/128 (32.768 kHz @ fx = 4.19 MHz)
1 = fLCD = 8192 Hz when fw = fx/64 (65.563 kHz @ fx = 4.19 MHz)
Figure 18-4. LCD Mode Register (LMOD)
18-3
LCD CONTROLLER/DRIVER
S3CB519
LCD CONTRAST CONTROL REGISTER (LCNST)
LCNST controls LCD contrast.
LCD Contrast Register (LCNST)
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Not used
Duty selection bits:
0000 = 1/16 step (the dimmest level)
Contrast enable bits:
0 = Disable contrast
1 = Enable contrast
0001 = 2/16 step
0010 = 3/16 step
.....
1110 = 15/16 step
1111 = 16/16 step (the brightest level)
Figure 18-5. LCD Contrast Register (LCNST)
18-4
S3CB519
LCD CONTROLLER/DRIVER
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
0 1 2 3
15 0 1 2 3
15
V
V
DD
SS
FR
1 Frame
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
COM0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
COM1
COM2
SEG0
S S S S S
E E E E E
G G G G G
0 1 2 3 4
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
Figure 18-6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)
18-5
LCD CONTROLLER/DRIVER
S3CB519
0 1 2 3
15 0 1 2 3
15
V
V
DD
SS
FR
1 Frame
V
V
V
V
LC1
LC2
LC3
LC4
SEG1
V
V
LC5
SS
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SEG0-COM0
0V
-VLC5
-VLC4
-VLC3
-VLC2
-VLC1
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SEG1-COM0
0V
-VLC5
-VLC4
-VLC3
-VLC2
-VLC1
Figure 18-6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)
18-6
S3CB519
LCD CONTROLLER/DRIVER
COM0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
V
V
DD
SS
COM1
COM2
COM3
COM4
COM5
COM6
COM7
FR
1 Frame
V
LC1
V
V
V
V
LC2
COM0
LC3 = VLC4
S S S S S
E E E E E
G G G G G
0 1 2 3 4
LC5
SS
V
V
V
V
V
LC1
LC2
COM1
LC3 = VLC4
LC5
SS
V
V
V
V
V
LC1
LC2
COM2
SEG0
LC3 = VLC4
LC5
SS
V
V
V
V
V
LC1
LC2
LC3 = VLC4
LC5
SS
V
V
V
V
LC1
LC2
LC3 = VLC4
LC5
SEG0-COM0
0V
-VLC5
-VLC3 = -VLC4
-VLC2
-VLC1
Figure 18-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)
18-7
LCD CONTROLLER/DRIVER
LCD KEY SCAN
S3CB519
When P5CON.7 is set, strobe signal is output to P5.0/SEG39-P5.15/SEG24 during normal SEG output, and the
strobe signal number is selected by P5CON setting.
Key input is acquired from KS0/P1.0–KS3/P1.3 and is set in P1CON.
If any pin of P5.0–P5.15 is set only to SEG in P5CON, the selected pin does not output the key strobe signal.
If any of P1.0-P1.3 is set to anything other than the alternative mode (key scan mode), the selected pin acts as a
normal I/O.
When P5.0/SEG39–P5.15/SEG24 are set as key strobe, selected key strobe is output, pin by pin, continuously with
a selected interval and duration.
When KS0/P1.0–KS3/P1.3 are set as an alternative mode (key scan input), KS0–KS3 state is normally high-
impedance, and when SEGx strobe is out, KS0/P1.0–KS3/P1.3 setting is changed to input pull-up state.
The data (Port 1) is input right before the strobe disappears, and if any “Low” state appears, an interrupt occurs.
When the key scan interrupt occurs, user can read the Interrupt request register for the key input state and the Port
5 data register for the key strobe state. The data of the selected pin, P5, is not changed until next strobe occurs.
Port 1 data register has invalid data when in the key input state.
Port 5 data register value is ‘0’ for P5.0 strobe, ‘1’ for P5.1, ‘2’ for P5.2, …’0FH’ for P5.15 strobe.
18-8
S3CB519
LCD CONTROLLER/DRIVER
0 1 2 3
15 0 1 2 3
15
V
DD
SS
FR
V
1 Frame
Tframe
Tinterval
Tstrobe
V
V
V
V
V
V
LC1
LC2
LC3
LC4
LC5
SS
P5.0
P5.1
VLC1
VLC2
VLC3
VLC4
VLC5
VSS
VLC1
VLC2
VLC3
VLC4
P5.15
V
V
LC5
SS
NOTES:
1. Tframe
When P5.0-P5.3 is used, Tframe is Tinterval x 4,
When P5.0-P5.7 is used, Tframe is Tinterval x 8,
When P5.0-P5.11 is used, Tframe is Tinterval x 12,
When P5.0-P5.15 is used, Tframe is Tinterval x 16.
2. Tinterval, Tstrobe value is set by setting P5CON value.
Figure 18-8. LCD Waveform when Key Strobe Signal is Active
18-9
LCD CONTROLLER/DRIVER
S3CB519
NOTES
18-10
S3CB519
A/D CONVERTER
19 A/D CONVERTER
OVERVIEW
The ADC is Sigma-Delta type ADC for speech and telephony applications. The ADC contains both digital IIR/FIR
filters, and an on-chip voltage reference circuit is included to allow supply operations.
FEATURES
Sigma Delta ADC.
·
·
·
256X oversampling
On chip decimation filter
On chip voltage reference circuitry
19-1
A/D CONVERTER
S3CB519
A/D CONVERTER CONTROL REGISTER (ADCON)
User can select the A/D input clock for dividing higher crystal by controlling ADCON.
A/D converted data are 14-bit resolution and are input to ADDATAH (High byte), ADDATAL (Low byte) in 16-bit data
format. Because A/DC use 256X over-sampling, for 8 kHz sampling, when crystal is 2.048 MHz (= 8 kHz ´ 256),
user must select fx as AD/DA input clock.
And when crystal is 4.096 MHz (= 2 ´ 8 kHz ´ 256), user must select fx/2 as AD/DA input clock.
A/DC Control Register (ADCON)
4CH, R/W, Reset: 00H
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Not used
AD/DA input clock selection bits:
000 = fx
001 = fx/2
010 = fx/3
011 = fx/4
A/D enable bits:
0 = A/DC disable
1 = A/DC enable
AD/DA clock On/Off bits:
0 = AD/DA clock Off
1 = AD/DA clock On
100 = fx/5
101 = fx/6
110 = fx/8
111 = fx10
AD/DA interrupt enable bits:
0 = Interrupt disable
1 = Interrupt enable
Figure 19-1. A/DC Control Register (ADCON)
19-2
S3CB519
A/D CONVERTER
ADGAIN
ADDATAH
ADDATAL
-
ADINN
ADINP
Decimal
Filter
Modulator
+
AVREFOUT
C6
Voltage Reference
C5
C3
C3
L
L
REFH
REFL
+
+
C4
AVDD AVSS
C4
VDD
VSS
L
AVDD AVSS
NOTE:
C3:
0.1
m
F
TANTALUM CAPACITOR
CERAMIC CAPACITOR
TANTALUM CAPACITOR
C4, C6: 10 mF
C5:
L:
1 mF
0.1mH
Figure 19-2. A/D Converter Block Diagram
19-3
A/D CONVERTER
S3CB519
Differential-ended input application
VDD
ADINP
ADINN
+
-
R2
C1
R1
C2
R3
AVREFOUT
R4
R2'
C1'
R1'
R5
AVREFOUT
GND
ADGAIN
C2'
Voltage Gain: R5/(R1 + R2)
R3 = R4 x R5/(R4 +R5)
R1 = R1'
Example:
R1 = R1' = 390 k
R2 = R2' = 47 k
W
W
R2 = R2'
C1 = C1'
C2 = C2'
R3 = 110 k
R4 = 220 k
R5 = 220 k
W
W
W
C1 = C1' = 470 pF
C2 = C2' = 22 pF
Single-ended input application
VDD
R2
ADGAIN
ADINN
ADINP
-
R1
C0
R1
C1
+
GND
AVREFOUT
R2
2 x R1
Voltage Gain:
R2 = 2 x R1
Example:
R1 = 100 k
R2 = 200 k
C1 = 50 pF
W
W
R1>50 k
W
C1 = 1 x 10-5/R2
Figure 19-3. Application Example
19-4
S3CB519
D/A CONVERTER
20 D/A CONVERTER
OVERVIEW
This MCU has an 8-bit Digital-to-Analog converter with R-2R structure. This DAC (Digital – to Analog converter) is
8
used to generate analog voltage, V
(DACON).
with 256-steps (2 ). This function is controlled by the DAC mode register
DA,
To enable the converter, the DACON.0 must be set to “1”. To generate an analog voltage (V ), load the appropriate
DA
value to DADATA. The level of the analog voltage is determined by DADATA.
When a user writes data to DADATA, the contents of GR13 is shifted to GR14, GR12 to GR13, GR11 to GR12, and
DADATA to GR11.
The content of GR24 is output to DAO. When GR24 is output and some time passes, the contents of GR23 is
shifted to GR24, GR22 to GR23, GR21 to GR22. After all the contents of GR21–GR24 is out to DAO, GR11–GR14
will be copied to GR21–GR24.
Four consequent DA data will be written to DADATA every AD/DA interrupt. Then the four data will be out with same
interval until the next AD/DA interrupt occurs.
The interval between DAO and the next DAO is about 31 msec when a 4.096 MHz oscillator is used, and ADC clock
is fx/2.
The interval clock comes from the ADC. (See ADCON).
DADATA
(Read)
DADATA
(Write)
8
GR11 GR12 GR13 GR14
WR
V
REF
Load
8
8
SFT_CK
GR21 GR22 GR23 GR24
DAO
R2R
NOTE:
When write, data is written to DADATA (write),
When read, data is read from DADATA (read).
Figure 20-1. D/A Converter Circuit Diagram
20-1
D/A CONVERTER
S3CB519
A
B
C
D
A'
B'
C'
D'
DADATA
WR
A
B
A
C
B
A
D
C
B
A
A'
B'
A'
C'
B'
A'
D'
C'
B'
A'
GR11
GR12
GR13
GR14
Load_CK
GR21
GR22
GR23
GR24
SFT_CK
DAO
D
C
B
D
C
B
D
A
C
D
A
B
C
D
Figure 20-2. D/A Converter Timing Diagram
20-2
S3CB519
D/A CONVERTER
D/A CONVERTER DATA REGISTER (DADATA)
The DADATA specifies the digital data to generate analog voltage.
nRESET initializes the DADATA value to "00H". The D/A converter output value, V
, is calculated by following
DAO
formula.
= V ´ (n / 256) + V
1
2
V
–
V
(n = 0-255, DADATA value), where, V and V
is specified in electrical
DAO
PP
BIAS
PP
PP
BIAS
data and the V is a regulated output voltage.
PP
1
2
If DADATA value is 0, V
= V
–
V
PP
DAO
BIAS
If DADATA value is 128, V
= V
DAO
DAO
BIAS
BIAS
1
2
If DADATA value is 255, V
= V
+
V
PP
D/A CONVERTER CONTROL REGISTER (DACON)
DACON values are set to logic "00H" following nRESET, and this value disables DAC.
D/AC Control Register (DACON)
72H, R/W, Reset: 00H
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
D/A enable bits:
0 = D/AC disable
1 = D/AC enable
Figure 20-3. D/A Control Register (DACON)
20-3
D/A CONVERTER
S3CB519
NOTES
20-4
S3CB519
MAC816
21 MAC816
MAC816 ARCHITECTURE OVERVIEW
MAC816 is a 16-bit fixed-point DSP coprocessor for low-end DSP applications. It is designed as one of the DSP
coprocessor engines for CalmRISC, which targets towards cost-sensitive low-end multimedia DSP applications. The
generic coprocessor instructions for CalmRISC are renamed according to the intended operations on MAC816,
including the DSP data type, and the DSP addressing mode. Below represented is the top block diagram of
MAC816.
YA[13:0] XA[13:0]
XDI[15:0] XDO[15:0] YD[15:0]
YDIE
XDIE
XDOE
RP0[15:0]
RP1[15:0]
RP2[15:0]
RPD[15:0]
MC0[15:0]
MC1[15:0]
XB[15:0]
EYB2XB
EXB2YB
YB[15:0]
X[15:0]
Y[15:0]
Multiplier & Adder
nXMCS,
XMWR,
nYMCS,
YMWR,
MSR0[15:0]
MSR1[15:0]
MAH[15:0]
MAL[15:0]
SMACYM
EC[2:0],
nlMASK
Status
nRTCS,
RTWR,
RAT[1:0]
Decoder
IR [11:0]
Adder
A[15:0]
B[15:0]
CKI,
nRES,
nlREXE
Control
IR[11:0]
Figure 21-1. Top Block Diagram
21-1
MAC816
S3CB519
The MAC816 building blocks consist of:
— Multiplier and Accumulator Unit (MAU)
— Arithmetic Unit (AU)
— RAM Pointer Unit (RPU)
— Interface Unit (IU)
Basically, MAU (Multiplier and Accumulator Unit) is built around an 8-bit by 16-bit parallel multiplier and a 32-bit
adder for multiply-and-accumulate (MAC) operations. Hence, 16-bit by 16-bit MAC operations are performed in two
cycles in MAC816. AU performs 16-bit arithmetic and shift operations for DSP. RPU of MAC816 consists of 3 data
memory pointers and 2 control blocks for the pointer modulo calculation. The pointers are used for accessing the
data memory for a 16-bit data operand. Since two 16-bit data operands can be fetched simultaneously in a single
cycle through XD[15:0] and YD[15:0] for MAC operation, the data memory should be partitioned into two parts: X and
Y memory. IU is for the communication between CalmRISC and MAC816. It decodes coprocessor interface signals
from CalmRISC and controls the data paths in MAC816, according to the decoding result.
Most of MAC816 instructions are 1-word instruction, while several instructions which need 16-bit immediate value are
2-word instruction.
21-2
S3CB519
MAC816
PROGRAMMER’S MODEL
In this chapter, the important features of MAC816 are discussed in detail. How the data memory is organized is
discussed and the explanation of registers follows. Last, the host interface with CalmRISC will be explained.
DATA MEMORY ACCESSES
The total data memory address space for MAC816 is 32K-word. The 32K-word data memory space is physically
divided into XM (X area memory) and YM (Y area memory). This memory is actually shared with the host processor
(CalmRISC). The host processor accesses the 64K-byte data memory in byte width, otherwise MAC816 accesses it
in 2-byte width. MAC816 has two types of addressing modes. RPU can generate two 15-bit addresses every
instruction cycle which can be post-modified.
YA = 63FH
YMH, DA = C7EH
YML, DA = C7FH
YA = 440H
YMH, DA = 880H
XMH, DA = 87EH
YML, DA = 881H
XML, DA = 87FH
XA = 0040H
XA = 0000H
XMH, DA = 0080H
XMH, DA = 0000H
XML, DA = 0081H
XML, DA = 0001H
I/O Area
(128 Byte)
Figure 21-2. Data Memory Organization
21-3
MAC816
S3CB519
Table 21-1. RPU(RAM Pointer Unit) Registers
Registers
Mreg1
Mnemonics
RP0
Description
RAM Pointer register 0
Reset Value
RPi
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
RP1
RAM Pointer register 1
RP2
RAM Pointer register 2
RPD
RAM Pointer for short direct addressing
Modulo Control register 0 for RP0/RP1
Modulo Control register 1 for RP2
MCi
MC0
MC1
XB[15:0]
RP0[15:0]
RP1[15:0]
16
+ 1, 0, - 1, +2/- 2
Modulo Control
[14:0]
[15:0]
XA[14:0]
YA[14:0]
MC0[15:0]
IR[5:4] IR[3:0]
RPD[15:0]
RP2[15:0]
16
[14:0]
[15:0]
+ 1, 0, - 1, +2/- 2
Modulo Control
MC1[15:0]
Figure 21-3. RPU (RAM Pointer Unit) Block Diagram
21-4
S3CB519
MAC816
Short Direct Memory Addressing Mode
Six-bits embedded in the instruction code as LSBs and 9-bits from the RPD[14:6] of RPD register as MSB compose
the 15-bit address to the data memory address. This can be used with some instructions operating an Ai (A/B
register in AU) operand. In “load/store mreg1” instruction, a 4-bit embedded in the instruction code as LSBs and 11-
bits from the RPD[14:4] of RPD register as MSB compose the 15-bit address to the data memory address. This can
be used to load/store RAM pointer register from/to data memory.
Indirect Memory Addressing Mode
The RPi registers of RPU are used as a 15-bit address for indirect addressing XM (X area memory) or YM (Y area
memory). Some instructions can simultaneously access the XM and YM, and then RP0 is used for XM and RP2 for
YM. In indirect addressing mode, RPi register is modified by +1,-1,-2, and +2 after the addressing. The MSB of RPi
register enables modulo opera tion of the RPi modification. The RPU registers are divided into two groups of
simultaneous addressing over XA and YA: X-memory is addressed by RP0 and RP1 with MC0 and Y-memory is
addressed by RP2 with MC1. RPi from both groups can be used for both XA and YA for instruction, which uses only
one address register. In this instruction the XM and YM can be viewed as a single continuous data memory space.
Table 21-2. RPi register bit information
Bit position
[14:0]
Value
Description
0H–7FFFH Data memory(XM/YM) address
[15]
0
1
Modulo mode disable
Modulo mode enable
21-5
MAC816
S3CB519
Modulo Control Registers (MCi)
MCi controls RP0, RP1 and RP2 register modifications after indirect memory accessing. MCi has an upper boundary
value in MCi[9:0], a step size in MCi[12:10] and a modulo size information in MCi[15:13]. The upper boundary
determines the upper limit of the modulo body. The modulo size information determines the lower limit and size of
the modulo body as shown below. For example, assume RP0 = 87FFH and MC0 = 03FFH: If "@RP0+" is used on
the operand of the instruction, the data memory contents pointed by "07FFH" is accessed, and RP0 is updated to
"8400H" after memory accessing. Assume RP0 = 07FFH and MC0 = 03FFH: If "@RP0+" is used on the operand of
the instruction, the data memory contents pointed by "07FFH" is accessed, and RP0 is updated to "0800H" after
memory accessing.
Bit position
[9:0]
Value
Description
0H–3FFH Upper boundary
[12:10]
000
001
Step size = + 2
Step size = - 2
Reserved
010–111
000
[15:13]
Maximum modulo size = 1024 (0H to 3FFH),
Modulo body = RPi[14:10]:0000000000 to RPi[14:10]:MCi[9:0]
Maximum modulo size = 8 (0H to 7H),
001
010
011
100
101
110
111
Modulo body = RPi[14:3]:000 to RPi[14:3]:MCi[2:0]
Maximum modulo size = 16 (0H to 0FH),
Modulo body = RPi[14:4]:0000 to RPi[14:4]:MCi[3:0]
Maximum modulo size = 32 (0H to 1FH),
Modulo body = RPi[14:5]:00000 to RPi[14:5]:MCi[4:0]
Maximum modulo size = 64 (0H to 3FH),
Modulo body = RPi[14:6]:000000 to RPi[14:6]:MCi[5:0]
Maximum modulo size = 128 (0H to 7FH),
Modulo body = RPi[14:7]:0000000 to RPi[14:7]:MCi[6:0]
Maximum modulo size = 256 (0H to 0FFH),
Modulo body = RPi[14:8]:00000000 to RPi[14:8]:MCi[7:0]
Maximum modulo size = 512 (0H to 1FFH),
Modulo body = RPi[14:9]:000000000 to RPi[14:9]:MCi[8:0]
21-6
S3CB519
MAC816
COMPUTATION UNIT
The computation unit contains two main units, the Multiplier and Accumulator Unit (MAU) and Arithmetic Unit (AU).
YB[15:0]
16
XB[15:0]
16
Y[15:0]
yi[15:0]
X[15:0]
xi[15:0]
8
8 x 16 Multiplier
Shift Left
32-Bit Adder
Saturation
OPM
MA[31:0]
32
16
16-Bit Adder
OP
Saturation
A[15:0]
B[15:0]
Figure 21-4. Computation Unit Block Diagram
21-7
MAC816
S3CB519
Multiplier and Accumulator Unit (MAU)
The MAU consists of a 8 by 16 to 24 bit parallel multiplier, two 16-bit input registers(X and Y), a product output
shifter, and 32-bit product and accumulator register(MA). The multiplier performs signed by signed, signed by
unsigned, unsigned by signed, or unsigned by unsigned multiplication. By clearing “MSR1[2] (or M816)”, the MAU
can perform 16 by 16 to 32 bit parallel multiplication in 2 cycles. After the multiplier instruction, if a read instruction of
MA is followed, previous MA register value will be read out because. During 16 by 16 multiplication, in the second
cycle of multiplication, the instruction of MA modification can cause illegal multiplication results. Thus, multiplier
instruction should not be followed by MA register writing. The “MV” flag is set if arithmetic overflow occurs after an
arithmetic operation in the MA register, and if set “OPM”, the MA register is saturated to a 32-bit positive
(7FFFFFFFH) or negative (80000000H). The MA register is not updated by loading X and Y registers. Hence, the X
and Y registers can be used as a temporary data registers. The registers in MAU are as shown in the table.
Mnemonics
Description
Reset Value
Unknown
Unknown
Unknown
Unknown
X
Y
MAU X input register
MAU Y input register
MAL
MAU Accumulator register, MA[15:0]
MAU Accumulator register, MA[31:16]
MAH or MA
Arithmetic Unit (AU)
The AU consists of 16-bit adder, 1-bit shifter, and two result registers (A and B). The AU receives one operand from
Ai and another operand from XB or Ai. Operations between the two Ai registers are also possible. The source and
destination Ai register of an AU instruction are always the same. The XB bus is used for transferring one of the
register content, an immediate operand, or the content of a data memory location as a source operand. The AU
results are stored in one of the Ai registers. The AU can perform add, subtract, compare, and shift operations. It
uses two’s complement arithmetic operations. The AU evaluates the status flags of an arithmetic result. The “V” flag
is set if arithmetic overflow occurs after an arithmetic operation in A or B register, and if set to “OPA” or “OPB”, the A
or B register is saturated to a 16-bit positive (7FFFH) or negative (8000H). Data transfer between MAC816 and the
host processor can be achieved via A or B register. The host processor (CalmRISC) can directly access A and B
registers of MAC816 through “CLD GPR,imm” or “CLD imm,GPR” instruction.
21-8
S3CB519
MAC816
STATUS REGISTERS
Status Register 0 : MSR0
MSR0 is mainly reserved for flagging an AU result , for protecting control overflow, and for indicating test results.
Bit Name
Bit
Description
C
V
0
Carry flag
1
Overflow flag
Zero flag
Z
2
3
N
Negative flag
Test result flag
T
4
OPA
OPB
–
5
Overflow Protection control for A register
Overflow Protection control for B register
Reserved
6
15–7
MSR0[0] (or C) is the carry of AU executions. MSR0[1] (or V) is the overflow flag of AU executions. It is set to 1 if
and only if the carry-in into the 16-th bit position of addition/subtraction differs from the carry-out from the 16-th bit
position. MSR0[2] (or Z) is the zero flag, which is set to 1 if and only if the AU result is zero. MSR0[3] (or N) is the
negative flag. Basically, the most significant bit (MSB) of AU results becomes the N flag. However, if an AU
instruction touches the overflow flag (V) like ADD, SUB, CP, etc, N flag is updated as exclusive-OR of V and the
MSB of the AU result. This implies that even if an AU operation results in overflow, N flag is still valid. T flag is set to
1 if the result of “ETST cond.” Instruction is true. MSR0[5] (or OPA) or MSR0[6] (or OPB) enables arithmetic
saturation when an arithmetic overflow occurs in A or B register.
Status Register 1 : MSR1
MSR1 consists of status flags of MAU operation, control bit for MAU, and selection bits of EC[I].
Bit Name
PSH1
OPM
Bit
0
Description
Multiplier product 1 bit shift control
Overflow Protection control for MA register
Multiplication mode control
MA overflow flag
1
M816
MV
2
3
SEC0
SEC1
SEC2
7–4
11–8
15–12
EC[0] selection
EC[1] selection
EC[2] selection
21-9
MAC816
S3CB519
MSR1[0] (or PSH1) enables the product to shift by one bit to the left. MSR1[1] (or OPM) controls MA saturation.
MSR1[2] (or M816) selects the operating mode for the multiplier. If M816=1, then the multiplier performs 8 by 16 bit
to 24 bit multiplication. Otherwise (M816=0), the multiplier performs 16 by 16 bit to 32 bit multiplication in two
cycles. MSR1[3] (or MV) is the overflow flag of MAU executions. It is set to 1 if an arithmetic overflow (32-bit
overflow) occurs after an arithmetic operation in MAU. It is cleared by a processor reset or “ECR MV” and modified
by writing to MSR1. SECi selects the combination of EC[I]. The flag information for the host processor is selected by
setting SECi.
Value( of SECi)
0000
Description
EC[I] = Z, Set to 1 if Z flag is 1.
EC[I] = not Z
EC[I] = N
0001
0010
0011
EC[I] = not N
EC[I] = C
0100
0101
EC[I] = not C
EC[I] = V
0110
0111
EC[I] = not V
EC[I] = T
1000
1001
EC[I] = GT
1010
EC[I] = LE
1011
EC[I] = MV
1100
EC[I] = not MV
reserved
1101–1111
21-10
S3CB519
MAC816
HOST INTERFACE
MAC816 is interfaced to the host processor according to CalmRISC coprocessor interface scheme explained below.
CalmRISC supports an efficient and seamless interface with coprocessors. By integrating a MAC (multiply and
accumulate) with the CalmRISC core, not only microcontroller functions but also complex digital signal processing
algorithms can be implemented in a single development platform (or MDS). CalmRISC has a set of dedicated signal
pins, through which data/command/status are exchanged between CalmRISC and a coprocessor. Depicted below
are the coprocessor signal pins and a figure of how two processors are interfaced.
Program
ROM
Data
RAM
Data Bus [7:0]
SYSCP [11:0]
nCOPID
nCLDID
CalmRISC
Coprocessor
CLDWR
EC[2:0]
Figure 21-5. Coprocessor Interface Diagram
21-11
MAC816
S3CB519
As shown in the coprocessor interface diagram above, the coprocessor interface signals of CalmRISC are:
SYSCP[11:0], nCOPID, nCLDID, nCLDWR, and EC[2:0]. The data are exchanged through the data buses, DI[7:0]
and DO[7:0]. CalmRISC issues the command to a coprocessor through SYSCP[11:0] in COP instructions. The
status of a coprocessor can be sent back to CalmRISC through EC[2:0], and these flags can be checked in the
condition codes of branch instructions. The coprocessor instructions are listed in the following table.
Table 21-3. Coprocessor instructions
Mnemonic
COP
Op 1
#imm:12
GPR
Op 2
–
Description
Coprocessor operation
CLD
imm:8
GPR
label
Data transfer from coprocessor into GPR
Data transfer of GPR to coprocessor
CLD
imm:8
EC2–0
JP(or JR)
CALL
Conditional branch with coprocessor status flags
LNK
The coprocessor of CalmRISC does not have its own program memory (that is, passive coprocessor) as shown in
Figure 7 -1. In fact, the coprocessor instructions are fetched and decoded by CalmRISC, which issues the command
to the coprocessor through the interface signals. For example, if “COP #imm:12” instruction is fetched, then the 12-
bit immediate value (imm:12) is loaded on SYSCP[11:0] signal with nCOPID active in ID/MEM stage, to request the
coprocessor to perform the designated operation. The interpretation of the 12-bit immediate value is totally up to the
coprocessor. The instruction set of the coprocessor is determined by arranging the 12 bit immediate field. In other
words, CalmRISC only provides a set of generic coprocessor instructions, and its installation to a specific
coprocessor instruction set can differ from one coprocessor to another. CLD Write instructions
(“CLD imm:8, GPR”) put the content of a GPR register of CalmRISC on the data bus (DO[7:0] ) and issue the
address(imm:8) of the coprocessor internal register on SYSCP[7:0] with nCLDID active and CLDWR active.
CLD Read instructions (“CLD GPR, imm:8” in Table 1) work similarly, except that the content of the coprocessor
internal register addressed by the 8-bit immediate value is read into a GPR register through DI[7:0] with nCLDID
active and CLDWR inactive.
The timing diagram given below is a coprocessor instruction pipeline and shows the time the coprocessor performs
the required operations. Suppose I2 is a coprocessor instruction. First, it is fetched and decoded by CalmRISC (at t =
T(i-1)). Once it is identified as a coprocessor instruction, CalmRISC indicates to the coprocessor the appropriate
command through the coprocessor interface signals (at t = T(i)). Then the coprocessor performs the designated
tasks at t = T(i) and t = T(i+1). Hence IF from CalmRISC and then ID/MEM and EX from the coprocessor constitute
the pipeline for I2. Similarly, if I3 is a coprocessor instruction, the coprocessor’s ID/MEM and EX stages replace the
corresponding stages of CalmRISC.
21-12
S3CB519
MAC816
CalmRISC
T (i -1)
T (i)
T (i +1)
IF
ID/MEM
IF
EX
ID/MEM
IF
I
I
I
1
2
3
: Normal Instruction
EX
: Coprocessor Instruction
: Coprocessor Instruction
ID/MEM
EX
Coprocessor
Interface Signals
For I
2
For I3
Coprocessor
ID/MEM
EX
I
I
2:
ID/MEM
EX
3:
Figure 21-6. Coprocessor Instruction Pipeline
In a multi-processor system, the data transfer between processors is an important factor to determine the efficiency
of the overall system. Suppose an input data stream is accepted by a processor, in order to share data with other
processors, there should be some efficient mechanism to transfer the data to the processors. In CalmRISC, data is
transferred through a single shared data memory. The shared data memory in a multi-processor has some inherent
problems such as data hazards and deadlocks. However, the coprocessor in CalmRISC accesses the shared data
memory only at the time designated by CalmRISC, a time at which CalmRISC is guaranteed not to access the data
memory, and therefore there is no contention over the shared data memory. Another advantage of the proposed
scheme is that the coprocessor can access the data memory in its own bandwidth.
21-13
MAC816
S3CB519
INSTRUCTION SET
GLOSSARY
This chapter describes the MAC816 instruction set, and the details of each instruction are listed in alphabetical order
. The following notations are used for the description and mnemonics of assembler.
Table 21-4. Notation and Convention
Notation
Interpretation
<opN>
Operand N. N can be omitted if there is only one operand. Typically, <op1> is the
destination (and source) operand and <op2> is the source operand.
adr:N
Content of memory location specified by N-bit address
N-bit immediate number
Bit-wise AND
#imm:N
&
|
~
Bit-wise OR
Bit-wise NOT
^
Bit-wise XOR
N**M
(N)M
Mth power of N
M-based number N
21-14
S3CB519
MAC816
Table 21-5. MAC816 Registers
Mnemonic Descriptions
Notation
Operand Code
Mreg
0000–0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
–
MARN
Y
Reserved
MA[31:16] + MA[15], MA higher word with round-off
Y[15:0], multiplier Y input register
X[15:0], multiplier X input register
MA[15:0], multiplier accumulator lower 16-bits
MA[31:16], multiplier accumulator higher 16-bits
RP0[15:0], RAM pointer register 0
RP0[15:0], RAM pointer register 1
RP0[15:0], RAM pointer register 2
RAM pointer for short direct addressing
Modulo control register 0 for RP0/RP1
Modulo control register 1 for RP2
MAC816 status register 0
X
MAL
MAH
RP0
RP1
RP2
RPD
MC0
MC1
MSR0
MSR1
A
MAC816 status register 1
Ai
A[15:0], AU result register A
1
B
B[15:0], AU result register B
Am
00
A
A[15:0], AU result register A
01
B
B[15:0], AU result register B
10
AC
A[15:0], AU result register A with Carry
B[15:0], AU result register B with Carry
A[15:0], AU result register A
11
BC
MAm
00
A
01
B
B[15:0], AU result register B
10
MAL
MAH
MA[15:0], multiplier accumulator lower 16-bits
MA[31:16], multiplier accumulator higher 16-bits
11
21-15
MAC816
S3CB519
Table 21-5. MAC816 Registers (Continued)
Notation
Operand Code
Mnemonic
–
Descriptions
Mreg2
000–011
100
101
110
111
00
Reserved
Mreg2s
Mreg2d
Y
Y[15:0], multiplier Y input register
X[15:0], multiplier X input register
MA[15:0], multiplier accumulator lower 16-bits
MA[31:16], multiplier accumulator higher 16-bits
RP0[15:0], RAM pointer register 0
RP0[15:0], RAM pointer register 1
RP0[15:0], RAM pointer register 2
RAM pointer for short direct addressing
Modulo control register 0 for RP0/RP1
Modulo control register 1 for RP2
MAC816 status register 0
X
MAL
MAH
RP0
RP1
RP2
RPD
MC0
MC1
MSR0
MSR1
Mreg1
Mreg3
01
10
11
00
01
10
11
MAC816 status register 1
Table 21-6. Data Transfer Registers
Descriptions
Notation
Register Address
Creg
00
01
10
11
A[7:0], AU result register A lower 8-bits
A[15:8], AU result register A higher 8-bits
B[7:0], AU result register B lower 8-bits
B[15:8], AU result register B higher 8-bits
21-16
S3CB519
MAC816
Table 21-7. Memory Access Mode Information
Operand Code Mnemonic Descriptions
Content of memory location specified by RP0,
Notation
@rpm
0000
0001
0010
@rp0+
@rp0-
@rp0s
RP0 post-increment by 1 with modulo mode
Content of memory location specified by RP0,
RP0 post-decrement by 1 with modulo mode
Content of memory location specified by RP0,
RP0 post-modification by +2 or –2 with modulo mode
0011
0100
@rp0
Content of memory location specified by RP0
@rp1+
Content of memory location specified by RP1,
RP1 post-increment by 1 with modulo mode
0101
0110
@rp1-
@rp1s
Content of memory location specified by RP1,
RP1 post-decrement by 1 with modulo mode
Content of memory location specified by RP1,
RP1 post-modification by +2 or –2 with modulo mode
0111
1000
@rp1
Content of memory location specified by RP1
@rp2+
Content of memory location specified by RP2,
RP2 post-increment by 1 with modulo mode
1001
1010
@rp2-
@rp2s
Content of memory location specified by RP2,
RP2 post-decrement by 1 with modulo mode
Content of memory location specified by RP2,
RP2 post-modification by +2 or –2 with modulo mode
1011
1100–1111
00
@rp2
-
Content of memory location specified by RP2
Reserved
@rp0m
@rp0+
Content of memory location specified by RP0,
RP0 post-increment by 1 with modulo mode
01
10
@rp0-
@rp0s
Content of memory location specified by RP0,
RP0 post-decrement by 1 with modulo mode
Content of memory location specified by RP0,
RP0 post-modification by +2 or –2 with modulo mode
11
00
@rp0
Content of memory location specified by RP0
@rp2m
@rp2+
Content of memory location specified by RP2,
RP2 post-increment by 1 with modulo mode
01
10
11
@rp2-
@rp2s
@rp2
Content of memory location specified by RP2,
RP2 post-decrement by 1 with modulo mode
Content of memory location specified by RP2,
RP2 post-modification by +2 or –2 with modulo mode
Content of memory location specified by RP2
21-17
MAC816
S3CB519
Table 21-8. Condition Code Information
Notation
cc
Operand Code
0000
Mnemonic
Descriptions
Z
NZ
C
Z = 1
0001
Z = 0
0010
C = 1
0011
NC
NEG
POS
V1
C = 0
0100
N = 1
0101
N = 0
0110
V = 1
0111
V0
V = 0
1000
–
Reserved
N = 0 and Z = 0
N = 1 and Z = 1
MV = 1
MV = 0
Reserved
1001
GT
LE
1010
1011
MV1
MV0
–
1100
1101–1111
Table 21-9. Control Bit Code Information
Notation
Operand Code
Mnemonic
OPM
Descriptions
bs
000
001
010
011
100
101
110
111
MSR1[1]
PSH1
ME0
MSR1[0]
RP0[15], RP0 modulo mode enable
RP1[15], RP1 modulo mode enable
MSR1[2]
ME1
M816
ME2
RP2[15], RP2 modulo mode enable
MSR0[5]
OPA
OPB
MSR0[6]
21-18
S3CB519
MAC816
Table 21-10. AU operation code information
Mnemonic Descriptions
Notation
Operand Code
00
EMOD0
ELD/ELDT
EADD/EADDT
ESUB/ESUBT
ECP/ECPT
ERR/ERRT
ERL/ERLT
Load
01
Addition
10
Subtraction
Comparison
Rotate right
Rotate left
Arithmetic shift right
Arithmetic shift left
Increment
11
EMOD1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010–1111
ESR/ESRT
ESL/ESLT
EINC/EINCT
EDEC/EDECT
ENEG/ENEGT
ECR/ECRT
ENORM/ENORMT
EABS/EABST
–
Decrement
Negation
Clear
Normalization
Absolution
reserved
Table 21-11. Others
Notation
Operand Code
Mnemonic
Descriptions
Unsigned by unsigned multiplication
Unsigned by signed multiplication
Signed by unsigned multiplication
Signed by signed multiplication
Reset
sXsY
00
01
10
11
0
uu
us
su
none
ER
ES
rs
ts
1
Set
0
ELD/
Execute mnemonic always
EMOD1/
EMOD0
1
ELDT/
Execute mnemonic when test result flag (MSR0[4] or T) is
EMOD1T/
EMOD0T
set.
If T = 0, act as nop.
21-19
MAC816
S3CB519
INSTRUCTION ENCODING
Table 21-12. Instruction Encoding
Instruction
ELD Mreg2,@rpm
ELD @rpm,Mreg2
ELD Mreg3,@rpm
ELD @rpm,Mreg3
ELD Mreg1,adr:4
ELD adr:4,Mreg1
ESEC0 #imm:4
11 10
9
8
7
0
1
6
5
4
3
2
1
0
2nd Word
00
00
01
Mreg2
rpm
–
00
01
10
11
00
Mreg3
Mreg1
Mreg1
00
adr[3:0]
10
Imm[3:0]
ESEC0 #imm:4
01
ESEC0 #imm:4
10
ECR MV
11
ELD Mreg2d,Mreg2s
EMOD0 A,#imm:5
ELD adr:6,MAm
01
Mreg2d
Mreg2s
Imm[4:0]
adr[3:0]
1
EMOD0
11
00
01
10
11
00
adr[5:4]
MAm
ELD MAm,adr:6
01
10
MAm
Am
EADD Am,adr:6
ESUB Am,adr:6
ECP Am,adr:6
ELD Mreg,Am
00
01
Mreg
ELD Am,Mreg
ELD/ELDT @rpm,Am
EMOD1/EMOD1T Am
EMOD0/EMOD0T Am,MAm
EMOD0/EMOD0T Am,@rpm
1
0
1
ts
rpm
01
EMOD1
MAm
EMOD0
rpm
1
EMOD0
21-20
S3CB519
MAC816
Table 21-12. Instruction Encoding (Continued)
Instruction
11 10
9
8
7
6
5
4
3
2
1
0
2nd Word
ELD Mreg,#imm:16
EMOD0 Am,#imm:16
EMAD @rp0m,@rp2m,sXsY
EMSB @rp0m,@rp2m,sXsY
EMUL @rp0m,@rp2m,sXsY
EMUL Ai,@rp2m,sXsY
EMUL X,@rp2m,sXsY
EMUL @rp0mY,,sXsY
EMAD Ai,@rp2m,sXsY
EMAD X,@rp2m,sXsY
EMAD @rp0m,Y,sXsY
EMSB Ai,@rp2m,sXsY
EMSB X,@rp2m,sXsY
EMSB @rp0m,Y,sXsY
EMAD X,Y,sXsY
11
00
01
10
Mreg
Imm[15:12]
Imm[11:0]
EMOD0
00
Am
rp0m
rp2m
sXsY
–
01
10
11
0
Ai
10
11
rp0m
rp2m
11
00
01
10
0
0
Ai
Ai
10
11
rp0m
rp2m
10
11
00
rp0m
00
EMSB X,Y,sXsY
01
EMUL X,Y,sXsY
10
ESR MA
01
00
xx
ESL MA
01
ERND MA
10
ENOP
1
xxxxx
rpm
bs
ERPM rpm
00
01
10
11
ER/ES bs
11
rs
ETST cc
cc
Imm[3:0]
ELD RPDN,#imm:4
NOTE: "X" means not applicable.
21-21
MAC816
S3CB519
QUICK REFERENCE
Operation
Table 21-13. Quick Reference
Operand2 Function
#imm:5
Operand1
Flag
ELD
A
op1 ¬ op2
–
EADD
ESUB
ECP
op1 ¬ op1 + op2
op1 ¬ op1 - op2
op1 - op2
c.z,v,n
c,z,v,n
c,z,v,n
ELD
ELD
ELD
RPDN
Adr:6
#imm:4
Am/MAm
Adr:6
RPD[7:4] ¬ op2
op1 ¬ op2
Am/MAm
Am
op1 ¬ op2
EADD
ESUB
ECP
Adr:6
op1 ¬ op1 + op2
op1 ¬ op1 - op2
op1 - op2
c.z,v,n
c,z,v,n
c,z,v,n
ELD
ELD
ELD
ELD
ELD
ELD
ELD
Mreg1
Adr:4
Am
Adr:4
Mreg1
Mreg
op1 ¬ op2
op1 ¬ op2
op1 ¬ op2
op1 ¬ op2
op1 ¬ op2
op1 ¬ op2
op1 ¬ op2
–
–
–
–
–
–
–
mreg
Mreg2d
Mreg2
@rpm
Am
Am
Mreg2s
@rpm
Mreg2
MAm
ELD
op1 ¬ op2
–
EADD
ESUB
ECP
op1 ¬ op1 + op2
op1 ¬ op1 - op2
op1 - op2
c.z,v,n
c,z,v,n
c,z,v,n
ELDT
EADDT
ESUBT
ECPT
If T=1, same as ELD
If T=1, same as EADD
If T=1, same as ESUB
If T=1, same as ECP
–
c.z,v,n
c,z,v,n
c,z,v,n
ELD
@rpm
Am
Am
op1 ¬ op2
–
ELDT
If T=1, same as ELD
ELD
@rpm
op1 ¬ op2
–
EADD
ESUB
ECP
op1 ¬ op1 + op2
op1 ¬ op1 - op2
op1 - op2
c.z,v,n
c,z,v,n
c,z,v,n
ELDT
EADDT
ESUBT
ECPT
If T=1, same as ELD
If T=1, same as EADD
If T=1, same as ESUB
If T=1, same as ECP
–
c.z,v,n
c,z,v,n
c,z,v,n
21-22
S3CB519
MAC816
Flag
Table 21-13. Quick Reference (Continued)
Operation Operand1 Operand2 Function
MSR0[4] ¬ cc (condition check)
ETST
ELD
cc
mreg
A
–
–
–
#imm:16
#imm:16
op1 ¬ op2
ELD
op1 ¬ op2
–
EADD
ESUB
ECP
op1 ¬ op1 + op2
op1 ¬ op1 - op2
op1 - op2
c.z,v,n
c,z,v,n
c,z,v,n
ERPM
ER
rpm
bs
–
RP ¬ modified RP
op1 ¬ 0
–
–
–
–
–
–
ES
bs
op1 ¬ 10
ESEC0
ESEC1
ESEC2
MSR1
#imm:4
MSR1[7:4] ¬ imm[3:0]
MSR1[11:8] ¬ imm[3:0]
MSR1[15:12] ¬ imm[3:0]
ERR
Am
–
when Am!=AC/BC, op ¬ {op1}>>1, op1[15] ¬ op1[0],
c ¬ op1[0]
when Am=AC/BC, op1¬ {c:op1}>>1, c ¬ op1[0]
when t=1, same as ERR
c,z,v,n
c,z,v,n
ERRT
ERL
Am
Am
Am
Am
Am
Am
Am
Am
–
–
–
–
–
–
–
–
when Am!=AC/BC, op¬ {op1}<<1, op1[0]¬ op[15], c¬ op[15],
when Am=AC/BC, op1¬ {op1:c}<<1, c¬ op[15]
when t=1, same as ERL
c,z,v,n
ERLT
ESR
c,z,v,n
c,z,v,n
when Am!=AC/BC, op ¬ {op1}>>1, c ¬ op1[0]
when Am=AC/BC, op1 ¬ {c:op1}>>1, c ¬ op1[0]
when t=1, same as ESR
ESRT
ESL
c,z,v,n
c,z,v,n
when Am!=AC/BC, op1 ¬ {op1}<<1, op1[0] ¬ 0, c ¬ op[15],
when Am=AC/BC, op1 ¬ {op1:c}<<1, c ¬ op[15]
when t=1, same as ESL
ESLT
EINC
c,z,v,n
c,z,v,n
when Am!=AC/BC, op1 ¬ op1+1
when Am=AC/BC, op1 ¬ op1+c
when t=1, same as EINC
EINCT
EDEC
c,z,v,n
c,z,v,n
when Am!=AC/BC, op1 ¬ op1+ffffh
when Am=AC/BC, op1 ¬ op1+ffffh+c
when t=1, same as EDEC
EDECT
ENEG
c,z,v,n
c,z,v,n
when Am!=AC/BC, op1 ¬ ~op1+1
when Am=AC/BC, op1 ¬ ~op1+c
when t=1, same as ENEG
ENEGT
EABS
c,z,v,n
c,z,v,n
when Am!=AC/BC, if op[15]=1, op1 ¬ ~op1+1
when Am=AC/BC, op[15]=1, op1 ¬ ~op1+c
when t=1, same as EABS
EABST
ENORM
c,z,v,n
c,z,v,n
when Am!=AC/BC, if op1[15]^op1[14]=0,
op1 ¬ {op1}<<1, op1[0] ¬ 0, RP0 ¬ RP0+1
when Am=AC/BC, if op1[15]^op1[14]=0,
op1 ¬ {op1:c}<<1, RP0 ¬ RP0+1
when t=1, same as ENORMT
ENORMT
c,z,v,n
–
ECR
Am
–
op1 ¬ 0
ECRT
when t=1, same as ECR
21-23
MAC816
S3CB519
Table 21-13. Quick Reference (Concluded)
Operand1 Operand2 Operand3 Function
Operation
Flag
–
ESR
MA
MA
MA
MA
–
–
op1 ¬ op1>>1
op1 ¬ op1<<1
ESL
–
–
–
–
MV
MV
MV
ERND
EMAD
MA[31:16] ¬ MA[31:16] + MA[15]
X-reg ¬ @rp0m, Y-reg ¬ @rp2m,
MA ¬ MA+X*Y
@rp0m
@rp2m
EMSB
EMUL
EMAD
EMSB
EMUL
EMAD
EMSB
EMUL
EMAD
EMSB
EMUL
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
@rp0m
@rp0m
Ai
@rp2m
@rp2m
@rp2m
@rp2m
@rp2m
@rp2m
@rp2m
@rp2m
Y
X-reg ¬ @rp0m, Y-reg ¬ @rp2m,
MA ¬ MA-X*Y
MV
–
X-reg ¬ @rp0m, Y-reg ¬ @rp2m,
MA ¬ (X*Y)
X-reg ¬ op2, Y-reg ¬ @rp2m,
MA ¬ MA+X*Y
MV
MV
–
Ai
X-reg ¬ op2, Y-reg ¬ @rp2m,
MA ¬ MA-X*Y
Ai
X-reg ¬ op2, Y-reg ¬ @rp2m,
MA ¬ (X*Y)
X
Y-reg ¬ @rp2m,
MV
MV
–
MA ¬ MA+X*Y
X
Y-reg ¬ @rp2m,
MA ¬ MA-X*Y
X
Y-reg ¬ @rp2m,
MA ¬ (X*Y)
@rp0m
@rp0m
@rp0m
X-reg ¬ @rp0m,
MV
MV
–
MA ¬ MA+X*Y
Y
X-reg ¬ @rp0m,
MA ¬ MA-X*Y
Y
X-reg ¬ @rp0m,
MA ¬ (X*Y)
EMAD
EMSB
EMUL
MA
MA
MA
X
X
X
Y
Y
Y
MA ¬ MA+X*Y
MV
MV
–
MA ¬ MA-X*Y
MA ¬ (X*Y)
21-24
S3CB519
MAC816
MAC816 INSTRUCTION DESCRIPTION
EABS — Absolute
Format:
EABS <op>
<op>: Am
Operation:
If the MSB of <op> is 1, <op> ¬ ~<op> +1 when <op> is A or B.
If the MSB of <op> is 1, <op> ¬ ~<op> +C when <op> is AC or BC.
EABS adds the values 0 and the 2’s complement of <op>.
Flags:
C: set if the borrow of result is zero. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
21-25
MAC816
S3CB519
EABST — Absolute conditional
Format:
EABST <op>
<op>: Am
Operation:
Flags:
If T=1, then same as EABS, else no operation
If T=1, then same as EABS, else no operation
21-26
S3CB519
MAC816
EADD— Add
Format:
Operation:
Flags:
EADD <op1>, <op2>
<op1>: Am: A, B, AC, BC
<op2>: adr:6, @rpm, Ai, Mreg, #imm:16, #imm:5
<op1> ¬ <op1 + <op2> when <op1> is A or B.
<op1> ¬ <op1 + <op2> + C when <op1> is AC or BC.
EADD adds the values in <op1> and <op2> and stores the result in <op1>.
C: set if the carry of result is 1. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
NOTE:
If <op1> is B, <op2> can not be #imm:5.
21-27
MAC816
S3CB519
EADDT — Add conditional
Format:
EADDT <op1>, <op2>
<op1>: Am: A, B, AC, BC
<op2>: @rpm, Ai, MAH,MAL
Operation:
Flags:
If T=1, then same as EADD, else no operation
If T=1, then same as EADD, else no operation
21-28
S3CB519
MAC816
ECP — Compare
Format:
ECP <op1>, <op2>
<op1>: Am
<op2>: adr:6, @rpm, Ai, Mreg, #imm:16, #imm:5
Operation:
<op1> + ~<op2> +1 when <op1> is A or B.
<op1> + ~<op2> +C when <op1> is AC or BC.
ECP compares the values of <op1> and <op2> by subtracting <op2> from <op1>.
Contents of <op1> and <op2> are not changed.
Flags:
NOTE:
C: set if the borrow of result is zero. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
If <op1> is B, <op2> can not be #imm:5.
21-29
MAC816
S3CB519
ECPT — Compare conditional
Format:
ECPT <op1>, <op2>
<op1>: Am: A, B, AC, BC
<op2>: @rpm, Ai, MAH,MAL
Operation:
Flags:
If T=1, then same as ECP, else no operation
If T=1, then same as ECP, else no operation
21-30
S3CB519
MAC816
ECR — Clear
Format:
ECRT <op>
<op>: Ai, MV
Operation:
<op> ¬ 0
ECRT clears Ai or MV.
21-31
MAC816
S3CB519
ECRT — Clear
Format:
ECRT <op>
<op>: Ai
Operation:
If T=1, <op> ¬ 0
ECRT clears Ai when T=1.
21-32
S3CB519
MAC816
EDEC — Decrement
Format:
EDEC <op>
<op>: Am
Operation:
<op> ¬ <op> + 0xffff when <op> is A or B.
<op> ¬ <op> + 0xffff + C when <op> is AC or BC.
EDEC decrements the value in <op>.
Flags:
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
21-33
MAC816
S3CB519
EDECT — Decrement conditional
Format:
EDECT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as EDEC, else no operation
If T=1, then same as EDEC, else no operation
21-34
S3CB519
MAC816
EINC — Increment
Format:
EINC <op>
<op>: Am
Operation:
<op> ¬ <op> + 1 when <op> is A or B.
<op> ¬ <op> + C when <op> is AC or BC.
EINC increments the value in <op>.
Flags:
C: set if carry is generated. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
21-35
MAC816
S3CB519
EINCT — Increment conditional
Format:
EINCT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as EINC, else no operation
If T=1, then same as EINC, else no operation
21-36
S3CB519
MAC816
ELD Adr — Load Adr
Format:
ELD <op1>, <op2>
<op1>,<op2>: adr:6, MAi / adr:4,Mreg1
Operation:
<op1> ¬ <op2>
ELD Adr loads a value specified by <op2> into the memory location determined by <op1>
21-37
MAC816
S3CB519
ELD Ai— Load Ai
Format:
ELD <op1>, <op2>
<op1>: Ai: A, B
<op2>: adr:6, @rpm, Ai, Mreg, #imm:5, #imm:16
Operation:
NOTE:
Ai ¬ <op2>
ELD Ai loads a value specified by <op2> into the register designated by Ai.
If <op1> is B, <op2> can not be #imm:5.
21-38
S3CB519
MAC816
ELD Mreg — Load Mreg
Format:
ELD <op1>, <op2>
<op1>: Mreg
<op2>: Ai
Operation:
Mreg ¬ Ai
ELD Mreg loads a value specified by <op2> into the register designated by Mreg.
21-39
MAC816
S3CB519
ELD Mreg1 — Load Mreg1
Format:
ELD <op1>, <op2>
<op1>: Mreg1: RP0, RP1, RP2, RPD
<op2>: adr:4
Operation:
Mreg1 ¬ adr:4
ELD Mreg1 loads the content of memory location determined by adr:4 into the register
designated by Mreg1.
21-40
S3CB519
MAC816
ELD Mreg2 — Load Mreg2
Format:
ELD <op1>, <op2>
<op1>: Mreg2: X, Y, MAH, MAL
<op2>: @rpm
Operation:
Mreg2 ¬ @rpm, rpi ¬ post-modified rpi
ELD Mreg2 loads the content of memory location determined by @rpm into the register
designated by Mreg2.
21-41
MAC816
S3CB519
ELD Mreg3 — Load Mreg3
Format:
ELD <op1>, <op2>
<op1>: Mreg3: MC0, MC1, MSR0, MSR1
<op2>: @rpm
Operation:
Mreg3 ¬ @rpm
ELD Mreg3 loads the content of memory location determined by @rpm into the register
designated by Mreg3.
21-42
S3CB519
MAC816
ELD @rpm — Load into memory indexed
Format:
ELD <op1>, <op2>
<op1>: @rpm
<op2>: Ai, Mreg2, Mreg3
Operation:
@rpm ¬ <op2>, rpi ¬ post-modified rpi
ELD @rpm loads the value of <op2> into the memory location determined by @rpm.
21-43
MAC816
S3CB519
EMAD — Multiplication and Addition
Format:
Operation:
Flags:
EMAD <op1>, <op2>,sXsY
<op1>,<op2>: @rp0m,@rp2m / Ai,@rp2m / X,@rp2m / @rp0m,Y / X,Y
X ¬ <op1>, Y ¬ <op2>, MA ¬ MA + {sign,X}*{sign,Y}
EMAD multiplies the values in <op1> and <op2> and adds the result in MA.
MV: Set if the arithmetic overflow occurs in MA after this instruction.
21-44
S3CB519
MAC816
EMSB — Multiplication and Subtraction
Format:
Operation:
Flags:
EMSB <op1>, <op2>,sXsY
<op1>,<op2>: @rp0m,@rp2m / Ai,@rp2m / X,@rp2m / @rp0m,Y / X,Y
X ¬ <op1>, Y ¬ <op2>, MA ¬ MA – {sign,X}*{sign,Y}
EMAD multiplies the values in <op1> and <op2> together and subtracts the result in MA.
MV: Set if the arithmetic overflow occurs in MA after this instruction.
21-45
MAC816
S3CB519
EMUL — Multiply
Format:
EMUL <op1>, <op2>,sXsY
<op1>,<op2>: @rp0m,@rp2m / Ai,@rp2m / X,@rp2m / @rp0m,Y / X,Y
Operation:
X ¬ <op1>, Y ¬ <op2>, MA ¬ {sign,X}*{sign,Y}
EMUL multiplies the values in <op1> and <op2> and stores the result in MA.
21-46
S3CB519
MAC816
ENEG — Negate
Format:
ENEG <op>
<op>: Am
Operation:
<op> ¬ ~<op> +1 when <op> is A or B.
<op> ¬ ~<op> +C when <op> is AC or BC.
ESUB adds the values 0 and the 2’s complement of <op> to to negate <op>.
Flags:
C: set if the borrow of result is zero. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
21-47
MAC816
S3CB519
ENEGT — Negate conditional
Format:
ENEGT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as ENEG, else no operation
If T=1, then same as ENEG, else no operation
21-48
S3CB519
MAC816
ENOP — No operation
Format:
Operation:
Flags:
ENOP
No operation
No operation
21-49
MAC816
S3CB519
ENORM — Normalization step
Format:
Operation:
Flags:
ENORM <op>
<op>: Am
If <op>[15] == <op>[14], <op> ¬ <op> << 1, RP0 ¬ RP0+1 when <op> is A or B.
If <op>[15] == <op>[14], <op> ¬ {<op>,C} <<1, RP0 ¬ RP0+1 when <op> is AC or BC.
C: <op>[15] ^ <op>[14]
Z: set if result is zero. Reset if not
V: reset to zero.
N: set if the MSB of result is 1. Reset if not
21-50
S3CB519
MAC816
ENORMT — Normalization step conditional
Format:
ENORMT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as ENORM, else no operation
If T=1, then same as ENORM, else no operation
21-51
MAC816
S3CB519
ER — Bit Reset
Format:
ER bs
Operation:
bs ¬ 0
ES resets the specified bit.
21-52
S3CB519
MAC816
ERL — Rotate Left
Format:
ERL <op>
<op>: Am
Operation:
<op> ¬ {<op>[14:0],<op>[15]}, C ¬ <op>[15] when Am is A or B.
<op> ¬ {<op>[14:0],C}, C ¬ <op>[15] when Am is AC or BC.
ERL rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C).
Flags:
C: set if the MSB of <op> (before shifting) is 1. Reset if not
Z: set if result is zero. Reset if not
V: reset to zero.
N: set if the MSB of result is 1. Reset if not
21-53
MAC816
S3CB519
ERLT — Rotate Left conditional
Format:
ERLT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as ERL, else no operation
If T=1, then same as ERL, else no operation
21-54
S3CB519
MAC816
ERND — Round off
Format:
ERND MA
Operation:
MA[31:16] ¬ MA[31:16] + MA[15], MA[15:0] ¬ 0
ERND adds 0x8000 to the lower 16-bit position of MA and stores the result in MA.
Flags:
MV: set if overflow is generated. Reset if not
21-55
MAC816
S3CB519
ERPM — Modify Ram pointer
Format:
ERPM rpm
Operation:
rpi ¬ modified rpi
ERPM modifies a rpi by rpm.
NOTE:
It does not generate a cycle of RAM access.
21-56
S3CB519
MAC816
ERR — Rotate Right
Format:
ERR <op>
<op>: Am
Operation:
<op> ¬ {<op>[0], <op>[15:1]}, C ¬ <op>[0] when Am is A or B.
<op> ¬ {C, <op>[15:1]}, C ¬ <op>[0] when Am is AC or BC.
RR rotates the value of <op> to the right and stores the result back into <op>.
The original LSB of <op> is copied into carry (C).
Flags:
C: set if the LSB of <op>(before shifting) is 1. Reset if not
Z: set if result is zero. Reset if not
V: reset to zero.
N: set if the MSB of result is 1. Reset if not
21-57
MAC816
S3CB519
ERRT — Rotate Right conditional
Format:
ERRT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as ERR, else no operation
If T=1, then same as ERR, else no operation
21-58
S3CB519
MAC816
ES — Bit Set
Format:
ES bs
Operation:
bs ¬ 1
ES sets the specified bit.
21-59
MAC816
S3CB519
ESEC0 / ESEC1 / ESEC2 — Set SECi
Format:
ESEC0 #imm:4
ESEC1 #imm:4
ESEC2 #imm:4
Operation:
ESEC0: SEC0[3:0] ¬ #imm:4
ESEC1: SEC1[3:0] ¬ #imm:4
ESEC2: SEC2[3:0] ¬ #imm:4
21-60
S3CB519
MAC816
ESL — Shift Left
Format:
ESL <op>
<op>:Am
Operation:
<op> ¬ {<op>[14:0],0}, C ¬ <op>[15] when <op> is A or B.
<op> ¬ {<op>[14:0],C}, C ¬ <op>[15] when <op> is AC or BC.
ESL shifts to the left by 1 bit. The MSB of the original <op> is copied into carry(C).
Flags:
C: set if the MSB of <op>(before shifting) is 1. Reset if not
Z: set if result is zero. Reset if not
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
21-61
MAC816
S3CB519
ESLT — Shift Left conditional
Format:
ESLT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as ESL, else no operation
If T=1, then same as ESL, else no operation
21-62
S3CB519
MAC816
ESR — Shift Right
Format:
ESR <op>
<op>:Am
Operation:
<op> ¬ {<op>[15],<op>[15:1]}, C ¬ <op>[0] when <op> is A or B.
<op> ¬ {C,<op>[15:1]}, C ¬ <op>[0] when <op> is AC or BC.
ESR shifts to the right by 1 bit. The LSB of the original <op> is copied into carry(C).
Flags:
C: set if the LSB of <op>(before shifting) is 1. Reset if not
Z: set if result is zero. Reset if not
V: set to zero
N: set if result is negative. Reset if not
21-63
MAC816
S3CB519
ESRT — Shift Right conditional
Format:
ESRT <op>
<op>: Am
Operation:
Flags:
If T=1, then same as ESR, else no operation
If T=1, then same as ESR, else no operation
21-64
S3CB519
MAC816
ESUB — Subtract
Format:
ESUB <op1>, <op2>
<op1>: Am
<op2>: adr:6, @rpm, Ai, Mreg, #imm:16, #imm:5
Operation:
<op1> ¬ <op1> + ~<op2> +1 when <op1> is A or B.
<op1> ¬ <op1> + ~<op2> +C when <op1> is AC or BC.
ESUB adds the values in <op1> and the 2’s complement of <op2>,
to perform subtraction on <op1> and <op2>.
Flags:
NOTE:
C: set if the borrow of result is zero. Reset if not.
Z: set if result is zero. Reset if not.
V: set if overflow is generated. Reset if not.
N: exclusive OR of V and MSB of result.
If <op1> is B, <op2> can not be #imm:5.
21-65
MAC816
S3CB519
ESUBT — Subtract conditional
Format:
ESUBT <op1>, <op2>
<op1>: Am
<op2>: @rpm, Ai, MAH, MAL
Operation:
Flags:
If T=1, then same as ESUB, else no operation
If T=1, then same as ESUB, else no operation
21-66
S3CB519
MAC816
ETST — Test Condition
Format:
Operation:
Flags:
ETST cc
cc: Z, NZ, C, NC, NEG, POS, V1, V0, GT, LE, MV1, MV0
T ¬ test result
ETST tests the specified condition of a flag.
T: set if test result is true. Reset if not
21-67
MAC816
S3CB519
NOTES
21-68
S3CB519
ELECTRICAL DATA
22 ELECTRICAL DATA
OVERVIEW
Table 22-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
Input voltage
V
–
-0.3 to + 6.5
V
DD
V
–
–
-0.3 to V + 0.3
V
V
I
DD
Output voltage
Output current high
V
-0.3 to V + 0.3
O
DD
I
One I/O pin active
-18
mA
OH
All I/O pins active
One I/O pin active
-60
Output current low
I
+ 30
mA
OL
Total pin current for port
–
+ 100
°
Operating temperature
Storage temperature
T
-25 to + 85
C
A
°
T
–
-65 to + 150
C
STG
Table 22-2. D.C. Electrical Characteristics
°
°
(T = -25 C to + 85 C, V
= 2.2 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
fxx = 8.2 MHz
Min
Typ
Max
Unit
Operating voltage
V
3.0
–
5.5
5.5
V
DD
fxx = 4.1 MHz
2.2
–
–
Input high voltage
Input low voltage
V
All input pins except V
0.8 V
V
V
V
IH1
IH2
IL2
DD
DD
V
X , XT
V
-0.1
DD
IH2
IN
IN
V
All input pins except V
X , XT
–
–
0.2 V
IL1
DD
V
0.1
IL2
IN
IN
22-1
ELECTRICAL DATA
S3CB519
Table 22-2. D.C. Electrical Characteristics (Continued)
°
°
(T = -25 C to + 85 C, V = 2.2 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
-1.0
Typ
Max
Unit
Output high voltage
V
V
= 5 V; I = -1 mA
V
V
–
–
V
OH1
DD
OH
DD
All output pins except V
OH2
V
V
= 5 V; I = -15 mA
-1.0
DD
–
–
OH2
DD
OH
Port 5
Output low voltage
V
V
= 4.5-5.5 V; I = 15 mA
–
0.4
–
2
3
V
OL1
DD
OL
Input high leakage
current
I
V
= V
DD
–
mA
LIH1
IN
All input pins except I
LIH2
I
V
= V
DD
20
-3
LIH2
IN
X , XT , X , XT
OUT
IN
IN OUT
Input low leakage
current
I
V
= 0 V
IN
–
–
LIL1
All input pins except I
LIL2
I
V
= 0 V
IN
-20
LIL2
X , XT , X , XT , nRESET
OUT
IN
IN OUT
Output high leakage
current
I
V
= V
–
–
–
–
3
-3
70
LOH
OUT
DD
All I/O pins and Output pins
V = 0 V
OUT
Output low
leakage current
I
LOL
All I/O pins and Output pins
Pull-up resistor
R
V
= 0 V; V = 5 V ± 10%
30
50
kW
L1
IN
DD
°
All port, T = 25 C
A
R
V
= 0 V; V = 5 V ± 10%
110
210
310
L2
IN
DD
°
T = 25 C, nRESET only
A
22-2
S3CB519
ELECTRICAL DATA
Table 22-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = -25 C to + 85 C, V = 2.2 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
V = 2.7 to 5.5 V
DD
Min
Typ
Max
Unit
|V –COMi|
V
–
–
120
mV
DD
DC
voltage drop (I=0-15)
-15 uA per common pin
LCNST = 00000000b
|V –SEGi|
V
V = 2.7 to 5.5 V
DD
–
–
120
70
mV
DD
DS
voltage drop (I=0-55)
-15 uA per segment pin
LCNST = 00000000b
LCD voltage
R
V
= 2.7 to 5.5 V; LCON.3 = 0
40
55
kW
LCD1
LCD
dividing resistor
R
V
V
= 2.7 to 5.5 V; LCON.3 = 1
= 2.7 to 5.5 V;
20
–
28
35
–
LCD2
LCD
LCD
Total contrast
resistor
R
140
CNST
LCNST = 10000000b
= 2.7 to 5.5 V
V
-0.2
DD
V
V
+0.2
DD
VLC Output voltage
V
V
V
DD
LC1
LCD
0.8V -0.2
DD
0.8 V
0.8V +0.2
DD
V
LCD clock = 0 Hz
DD
DD
DD
DD
LC2
0.6V -0.2
DD
0.6 V
0.4 V
0.2 V
0.6V +0.2
DD
V
LCNST = 00000000b
LC3
0.4V -0.2
DD
0.4V +0.2
DD
V
LC4
0.2V -0.2
DD
0.2V +0.2
DD
V
LC5
(1)
I
Run mode; V = 5 V ± 10%
DD
–
–
–
4
8
mA
mA
mA
mA
Supply current
DD1
6 MHz crystal oscillator
4 MHz crystal oscillator
2.7
2
5.4
4
V
= 3 V ± 10%
DD
6 MHz crystal oscillator
4 MHz crystal oscillator
1.3
1.2
2.6
2.5
I
Idle mode: V = 5 V ± 10 %
DD
DD2
6 MHz crystal oscillator
4 MHz crystal oscillator
1.0
0.5
2.0
1.5
Idle mode: V = 3 V± 10 %
DD
6 MHz crystal oscillator
4 MHz crystal oscillator
0.4
17
1.0
34
I
Sub-run mode; V = 3 V± 10 %
DD
–
–
–
mA
mA
mA
DD3
Main stop, 32 kHz sub-osc.
I
Sub-idle mode; V = 3 V± 10 %
DD
4.8
0.2
10
3
DD4
Main stop, 32 kHz
I
Stop mode; V = 5 V ± 10 %,
DD
DD5
°
T = 25 C
A
°
0.1
2
V
= 3 V ± 10 %, T = 25 C
DD
A
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads
and ADC, DAC, BLD, LCD voltage dividing resistor.
22-3
ELECTRICAL DATA
S3CB519
Table 22-3. A.C. Electrical Characteristics
°
°
(T = -25 C to + 85 C, V = 2.2 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input high,
low width
t
,
–
200
–
ns
P0, P1
INTH
V
= 5 V
t
DD
INTL
RSL
nRESET input
low width
t
V
= 5 V ± 10 %
5
–
–
ms
DD
NOTE: User must keep a larger value than the min value.
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 22-1. Input Timing for External Interrupts (Port 0, Port 1)
tRSL
nRESET
0.2 VDD
Figure 22-2. Input Timing for nRESET
22-4
S3CB519
ELECTRICAL DATA
Table 22-4. Data Retention Supply Voltage in Stop Mode
°
°
(T = -25 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
V
–
2.2
–
5.5
V
DDDR
Data retention
supply current
I
V
= 2.2 V
DDDR
–
–
2
mA
DDDR
nRESET
Occur
Oscillation
Stabilization Time
Stop Mode
Normal
Operating Mode
Data Retention Mode
V
DD
V
DDDR
Execution of
STOP Instruction
nRESET
0.2VDD
t
WAIT
NOTE:
tWAIT is same as 2048 x 32 x 1/fxx
Figure 22-3. Stop Mode Release Timing When Initiated by a nRESET
22-5
ELECTRICAL DATA
S3CB519
Oscillation
Stabilization Time
OSC Start
up time
Normal
Operating
Mode
Stop Mode
Data Retention
VDD
VDDDR
Execution of
STOP Instruction
INT
0.2 VDD
t
WAIT
NOTE:
tWAIT is same as 2048 x 32 x 1/fxx. The value of 2048 which is selected for the clock
source of the basic timer can be changed. And then the value of tWAIT will be changed.
Figure 22-4. Stop Mode (Main) Release Timing Initiated by Interrupts
Oscillation
Stabilization Time
OSC Start
up time
Stop Mode
Normal
Operating
Mode
Data Retention
VDD
VDDDR
Execution of
STOP Instruction
INT
0.2 VDD
t
WAIT
NOTE:
tWAIT is same as 256 x 32 x 1/fxx. The oscillator strat up time is less than
100 ms. The value of 256 which is selected for the clock source of basic timer
must be kept within this value.
Figure 22-5. Stop Mode (Sub) Release Timing Initiated by Interrupts
22-6
S3CB519
ELECTRICAL DATA
Table 22-5. Synchronous SIO Electrical Characteristics
(T = -25 C to + 85 C, V = 4.5 V to 5.5 V, V = 0 V, fxx = 10 MHz oscillator )
°
°
A
DD
SS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK Cycle time
t
–
200
–
–
ns
CYC
Serial Clock High Width
Serial Clock Low Width
t
–
–
–
60
60
–
–
–
–
–
–
SCKH
t
SCKL
Serial Output data delay
time
t
50
OD
Serial Input data setup
time
t
–
–
40
–
–
–
–
ID
Serial Input data Hold
time
t
100
IH
t
CYC
t
SCKL
tSCKH
SCK
0.8 VDD
0.2 VDD
tID
tIH
0.8 VDD
0.2 VDD
SI
Input Data
tOD
SO
Output Data
Figure 22-6. Serial Data Transfer Timing
22-7
ELECTRICAL DATA
S3CB519
Table 22-6. BLD Electrical Characteristics
°
(T = 25 C, V = 2.2 V to 5.5 V, V = 0 V)
A
DD
SS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
BLD Voltage
VB0
Internal V mode
Typ-0.15
2.4
Typ+0.15
V
DD
VB1
VB2
VB3
VB4
VB5
VB6
2.7
3.0
3.3
4.0
4.5
1.2
Typ-0.3
Typ+0.3
External Input mode,
Typ-0.15
Typ+0.15
V
= 2.2 V–3.0 V
DD
VB7
External Input mode,
Typ-0.3
1.2
Typ+0.3
V
V
V
= 3.0 V–5.5 V
= 5.5 V
DD
DD
DD
BLD Current
IBLD
TB
–
–
50
100
–
mA
ms
(note)
BLD Response
= 5.5 V
1/fw
NOTE: The fw must be greater than 10 msec.
Table 22-7. ADC Electrical Characteristics
(T = -25 C to + 85 C, V = 3.0 V to 5.5 V, V = 0 V)
°
°
A
DD
SS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ADC Current
IADC
V
= 3.3 V
–
1.5
3
mA
DD
Sampling Frequency
Resolution
–
–
–
–
–
8
11
–
kHz
bits
Measurement Bandwidth: 20 Hz–4 kHz,
14
Full scale input sine wave: 1 kHz, Sampling
frequency: 8 kHz
Signal to Distortion
ratio
–
70
75
–
dB
Offset Error
–
–
–
–
–
2
±20
mV
Input Voltage Range
V
= 3.3 V
–
V
DD
PP
NOTE: All the data in this ADC characteristics is measured in the condition of V = 3.3 V
DD
22-8
S3CB519
ELECTRICAL DATA
Table 22-8. DAC Electrical Characteristics
(T = -25 C to + 85 C, V = 2.4 V to 5.5 V, V = 0 V)
°
°
A
DD
SS
Parameter
Symbol
Conditions
= 5.5 V
Min
Typ
Max
Unit
DAC Current
IDAC
V
–
1.5
3.0
mA
DD
Resolution
–
–
–
–
-3
8
–
–
3
bits
LSB
LSB
ms
Absolute Accuracy
Differential Linearity Error
Output Delay
DLE
–
-1.5
–
–
1.5
250
–
–
Output Load Resistance
Ro
–
–
10
1.5
kW
Output Level
(peak to peak)
°
°
1.2
1.88
V
T = -30 C to + 60 C
PP
A
Regulator Bias voltage
Output Interval
–
–
V
= 3.3 V
–
–
V
/2
–
–
V
DD
DD
OSC = 4.096 MHz;
31
ms
AD/DA clock input = 8 kHz
22-9
ELECTRICAL DATA
S3CB519
Table 22-9. Main Oscillator Frequency (f
1)
OSC
°
°
(T = -25 C to + 85 C V = 2.2 V to 5.5 V)
A
DD
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal/Ceramic
External clock
RC
V
= 2.2 V–5.5 V
0.4
–
4.1
MHz
DD
X
IN
XOUT
C1
C2
V
V
V
= 2.5 V–5.5 V
= 3.0 V–5.5 V
= 2.2 V–5.5 V
6.2
8.2
4.1
DD
DD
DD
0.4
–
MHz
X
IN
XOUT
V
V
= 2.5 V–5.5 V
= 3.0 V–5.5 V
6.2
8.2
–
DD
DD
R = 20 Kohm, V = 5 V
–
2
MHz
DD
XIN
XOUT
NOTE: Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
Table 22-10. Main Oscillator Clock Stabilization Time (T
)
ST1
°
°
(T = -25 C + 85 C, V = 4.5 V to 5.5 V)
A
DD
Oscillator
Test Condition
= 4.5 V to 5.5 V
Min
Typ
Max
Unit
Crystal
V
–
–
10
ms
DD
Ceramic
Stabilization occurs when V is equal to the minimum
–
–
4
ms
DD
oscillator voltage range.
V
= 4.5 V to 5.5 V
DD
External clock
X input high and low level width (t , t
)
50
–
–
ns
IN
XH XL
NOTE: Oscillation stabilization time (T
) is the time required for the CPU clock to return to its normal oscillation
ST1
frequency after a power-on occurs, or when Stop mode is ended by a nRESET signal.
22-10
S3CB519
ELECTRICAL DATA
1/fosc1
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 22-7. Clock Timing Measurement at X
Table 22-11. Sub Oscillator Frequency (f
IN
)
OSC2
°
°
(T = -25 C + 85 C, V = 2.2 V to 5.5 V)
A
DD
Oscillator
Clock Circuit
XT IN XT OUT
Test Condition
Min
32
Typ
32.768
Max
Unit
Crystal
Crystal oscillation frequency
35
kHz
C1 = 22 pF,
R = 39 kW
C2 = 33 pF
R
C1
C2
NOTE: Oscillation frequency and XTin input frequency data are for oscillator characteristics only.
Table 22-12. Sub Oscillator (Crystal) Start up Time (t
)
ST2
°
°
(T = -25 C + 85 C, V = 2.2 V to 5.5 V)
A
DD
Oscillator
Test Condition
Min
Typ
Max
Unit
Normal mode
Strong mode
V
V
V
V
= 4.5 V to 5.5 V
= 2.2 V to 4.5 V
= 3.0 V to 5.5 V
= 2.2 V to 3.0 V
–
1
2
sec
DD
DD
DD
DD
–
–
–
–
–
–
10
6
2
NOTE: Oscillation stabilization time (t
) is the time required for the oscillator to it’s normal oscillation when stop mode is
ST2
released by interrupts.
22-11
ELECTRICAL DATA
S3CB519
fxx
10 MHz
C
8 MHz
6 MHz
B
A
4 MHz
0.4 MHz
1
2
3
4
5
6
7
Supply Voltage (V)
Minimum instruction clock = 1/(1 x oscillator frequency)
A = 2.2 V: 4.1 MHz
B = 2.5 V: 6.2 MHz
C = 3.0 V: 8.2 MHz
Figure 22-8. Operating Voltage Range
22-12
S3CB519
MECHANICAL DATA
23 MECHANICAL DATA
OVERVIEW
The S3CB519 microcontroller is currently available in a 100-pin QFP and TQFP package.
23-1
MECHANICAL DATA
S3CB519
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
0.15 - 0.05
0.10 MAX
100-QFP-1420C
#100
+ 0.10
0.30 - 0.05
#1
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.65
0.15 MAX
(0.58)
0.10 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 23-1. 100-QFP-1420C Package Dimensions
23-2
S3CB519
MECHANICAL DATA
16.00
± 0.20
0-7
14.00
+ 0.073
0.127 - 0.037
0.08 MAX
100-TQFP-1414
#100
+ 0.07
- 0.03
#1
0.20
0.05-0.15
1.00
1.20 MAX
0.50
0.08 MAX
(1.00)
±
0.05
NOTE: Dimensions are in millimeters.
Figure 23-2. 100-TQFP-1414 Package Dimensions
23-3
MECHANICAL DATA
S3CB519
NOTES
23-4
S3CB519
DEVELOPMENT TOOLS
24 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with windows95/98/NT as its operating system can be used. One type of
debugging tool including hardware and software is provided: the effective cost and powerful in-circuit emulator,
InvisibleMDS, for CalmRISC8. Samsung also offers support software that includes debugger, Compiler, Assembler,
and a program for setting options.
CALMSHINE: IDE(INTEGRATED DEVELOPMENT ENVIRONMENT)
CalmRISC8 Samsung Host Interface for In-circuit Emulator, CalmSHINE, is a multi window based debugger for
CalmRISC8. CalmSHINE provides pull-down, pop-up and tool-bar menus, mouse support, function/hot keys, syntax
highlight, tool-tip, drag-and-drop and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user
interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added or removed,
docked or undocked completely.
INVISIBLE MDS: IN-CIRCUIT EMULATOR
The evaluation chip of CalmRISC8 has a basic debugging utility block. Using this block, evaluation chip directly
interfaces with host through only communication wire. So, InvisibleMDS offers simple and powerful debugging
environment.
CALMRISC8 C-COMPILER: CALM8CC
The CalmRISC8 Compiler offers the standard features of the C language, plus many extensions for MCU
applications, such as interrupt handling in C and data placement controls, designed to take fully advantage of
CalmRISC8 facilities. It conforms to the ANSI specification. It supports standard library of functions applicable to
MCU systems. The standard library also conforms to the ANSI standard. It generates highly size-optimized code for
CalmRISC8 by fully utilizing CalmRISC8 architecture. It is available in a Windows version integrated with the
CalmSHINE.
CALMRISC8 RELOCATABLE ASSEMBLER: CALM8ASM
The CalmRISC8 Assembler is a relocatable assembler for Samsung's CalmRISC8 MCU and its MAC816 and
MAC2424 coprocessors. It translates a source file containing assembly language statements into a relocatable
machine object code file in Samsung format. It runs on WINDOWS95 compatible operating systems. It supports
macros and conditional assembly. It produces the relocatable object code only, so the user should link object files.
Object files can be linked with other object files and loaded into memory.
CALMRISC8 LINKER: CALM8LINK
The CalmRISC8 Linker combines Samsung object format files and library files and generates absolute, machine-
code executable hex programs or binary files for CalmRISC8 MCU and its MAC816 and MAC2424 coprocessors. It
generates the map file, which shows the physical addresses to which each section and symbol is bounded, start
addresses of each section and symbol, and size of them. It runs on WINDOWS95 compatible operating systems.
24-1
DEVELOPMENT TOOLS
S3CB519
EMULATION PROBE BOARD CONFIGURATION
PWR
TP3
TP2
TP1
Single input
Differential input
CN1
CN2
JP1
0
1
2
51
52
POWER
Power on/off
Sub X-TAL Main X-TAL
JP9
1
53
TP4
JP4
S3EB510
157
105
Invisible
MDS
SRAM
SRAM
U10
U2
SW1
49
50
99
100
EP-B519
SM1402A
NOTES:
1. Unit: mm
2. SW1: reset
3. Power: power input (5V/500mA)
4. ADGAIN, AVREFOUT, ADINN, ADINP signals are not connected with CN1/CN2.
If you make an ADC application, refer to Figure 24-1 and use that circuit block.
Also you can refer to Figure 19-2 A/D converter block diagram for AVREFOUT, AVDD, AVSS, REFH, REFL.
Figure 24-1. Emulation Probe Board Configuration
Invisible MDS Connector = 10-pin/normal Pitch (2.54mm)
Pin No.
Pin Name
Pin No.
Pin Name
1
V
6
PTD0_TxD
DD
2
3
4
5
PNTRST_NINIT
PTCK_MCLK
PTMS
7
8
GND
UCLK
JTAGSEL
–
9
PTDI_RxD
10
24-2
S3CB519
DEVELOPMENT TOOLS
EXTERNAL EVENT INPUT HEADERS (JP4)
These input headers are used to add the break condition to the core status externally when the break using
CalmBreaker occurs in the evaluation chip.
EXT_BK
EVACHIP_EXTBK[0]
EXT_BK0
EVACHIP_EXTBK[1]
EXT_BK1
EVACHIP_EXTBK[2]
EXT_BK2
EVACHIP_EXTBK[3]
EXT_BK3
EVENT MATCH OUTPUT HEADERS (JP9)
Four event match signals and one combination event signal are occurred by the CalmBreaker in the evaluation chip.
These signals are transmitted through the evaluation chip.
EVMAT
EVACHIP_EXTBK[0]
EVMAT0
EVACHIP_EXTBK[1]
EVMAT1
EVACHIP_EXTBK[2]
EVMAT2
EVACHIP_EXTBK[3]
EVMAT3
EXTERNAL BREAK INPUT HEADERS (TP4)
This input pin is used to break during the evaluation chip run.
EVACHIP_BKREQX
BKREQX
24-3
DEVELOPMENT TOOLS
S3CB519
A/D CONVERTER FUNCTION BLOCK
Differential-ended Input Application
VDD
TP1
TP2
D1
D2
Analog
Signal
Input
ADINP
R17
C29 R16
C30
S3EB510
R18
AVREFOUT
R21
Analog
Signal
Input
ADINN
R20
D4
C31 R19
D3
R22
ADGAIN
GND
C32
C29 = 470 pF
C31 = 470 pF
C30 = 22 pF
C32 = 22 pF
R16 = 390 k
R18 = 110 k
R20 = 47 k
R22 = 220 k
W
W
W
W
R17 = 47k
R19 = 390 k
R21 = 220k
W
W
W
Single-ended Input Application
VDD
R25
TP3
ADGAIN
ADINN
D5
D6
Analog
Signal
Input
R23
R24
C34
C33
S3EB510
ADINP
GND
AVREFOUT
C33 = 200 nF
C34 = 56 pF
R23 = R24 = 100 k
W
R25 = 200 k
W
NOTE:
When you make some application board, you must use this circuit block.
Figure 24-2. A/D converter Function Block Diagram
24-4
S3CB519
DEVELOPMENT TOOLS
COMMUNICATION SELECTION
JP5-JP8 State
Description
When differential-ended input application is used for the ADC, JP5–JP8
must be set.
JP8
JP7
JP6
JP5
When Single-ended input application is used for the ADC, JP5–JP8 must be
set.
JP8
JP7
JP6
JP5
USE CLOCK SETTING FOR EXTERNAL CLOCK MODE
Proper crystal and capacitors for main clock should be inserted into pin socket on the IE Board as follows;
XIN
Y2
XOUT
C
C
X-Tal
SUB CLOCK SETTING
For sub-clock mode a crystal, 32.768 kHz and capacitors should be inserted into pin socket on the IE Board as
follows;
XT IN
Y1
XT OUT
C
C
R
X-Tal
NOTE: The value of resistor is 39 kW.
24-5
DEVELOPMENT TOOLS
S3CB519
CN1, CN2 PIN ASSIGNMENT
CN1,2 are the signals of IE-B519 and their pin assignment is the same as the pin of S3CB519.
CN1
1
Function
P4.1/COM9
CN1
2
Function
P4.2/COM10
P4.4/COM12
P4.6/COM14
P0.0
CN2
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Function
P3.7/SEG40
P5.1/SEG38
P5.3/SEG36
P5.5/SEG34
P5.7/SEG32
P5.9/SEG30
P5.11/SEG28
P5.13/SEG26
P5.15/SEG24
SEG22
CN2
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
Function
P5.0/SEG39
P5.2/SEG37
P5.4/SEG35
P5.6/SEG33
P5.8/SEG31
P5.10/SEG29
P5.12/SEG27
P5.14/SEG25
SEG23
3
P4.3/COM11
P4.5/COM13
P4.7/COM15
P0.1
4
5
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
P0.2
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
P0.3
P0.4
P0.5
P0.6
VDD
VSS
NC
NC
NC
NC
SEG21
NC
RSSETB EXT
NC
SEG20
SEG19
DAC
SEG18
SEG17
NC
NC
CKSEG16
PDSEG14
PDSEG12
PDSEG10
PDSEG8
PDSEG15
PDSEG13
PDSEG11
PDSEG9
PDSEG7
PDSEG5
PDSEG3
PDSEG1
COM0
NC
NC
NC
NC
NC
P1.0
P1.1
P1.2
P1.3
P2.0/SEG55
P2.2/SEG53
P2.4/SEG51
P2.6/SEG49
P3.0/SEG47
P3.2/SEG45
P3.4/SEG43
P3.6/SEG41
PDSEG6
P2.1/SEG54
P2.3/SEG54
P2.5/SEG54
P2.7/SEG54
P3.1/SEG54
P3.3/SEG54
P3.5/SEG54
PDSEG4
PDSEG2
PDSEG0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
100 P4.0/COM8
24-6
相关型号：
S3CB519XX-QX
RISC Microcontroller, 8-Bit, MROM, 10.24MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100
SAMSUNG
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