S3CB018 [SAMSUNG]
The S3CB018/FB018 single-chip CMOS microcontroller; 该S3CB018 / FB018单芯片CMOS微控制器
| 型号： | S3CB018 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3CB018/FB018 single-chip CMOS microcontroller |
| 文件： | 总33页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3CB018/FB018
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
CALMRISC OVERVIEW
The S3CB018/FB018 single-chip CMOS microcontroller is designed for high performance using Samsung’ s
newest 8-bit CPU core, CalmRISC.
CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has
separate program memory and data memory. Both instruction and data can be fetched simultaneously without
causing a stall, using separate paths for memory access. Represented below is the top block diagram of the
CalmRISC microcontroller.
1-1
PRODUCT OVERVIEW
S3CB018/FB018
S3CB018/FB018 OVERVIEW
FEATURES SUMMARY
CPU
8-Bit Serial I/O Interface
·
·
·
·
8-bit transmit/receive mode
8-bit receive mode
·
8-Bit RISC architecture
Memory
LSB first or MSB first transmission selectable
Internal and external clock source
·
·
ROM: 4 Kword (8 K-byte)
RAM: 3072 (1024+2048) byte
1024 (X-memory) byte
16-Bit Serial I/O Interface
2048 (Y-memory) byte
·
·
16-bit transmit/receive mode
External clock source
Stack
·
size: maximum 16 (word)-level
Coprocessor
26 I/O Pins
·
·
·
MAC 816
8 x 16, 16 x 16 Multiply and Accumulation
Arithmetic operation
·
I/O: 26 pins, including 8 S/W open drain pins
8-Bit Basic Timer
Two Power-Down Modes
·
·
Programmable interval timer
8 kinds of clock source
·
·
Idle mode: only CPU clock stop
Stop mode: selected system clock and CPU
clock stop
Watchdog Timer
System reset when 11-bit counter overflows
·
Oscillation Sources
16-Bit Timer/Counter
·
Crystal and Ceramic (0.4-20MHz), RC
Oscillation
·
·
Programmable interval timer
·
Programmable oscillation source
Two 8-bit timer counter mode and one 16-bit
timer counter mode, selectable by S/W
Instruction Execution Times
Watch Timer
·
·
50ns at 20MHz for 1 cycle instruction
100ns at 20MHz for 2 cycle instruction
·
·
Real time clock or interval time measurement
Four frequency outputs for buzzer sound
1-2
S3CB018/FB018
PRODUCT OVERVIEW
20
PA[19:0]
PD[15:0]
Program Memory Address
Generation Unit
PC[19:0]
20
8
8
HS[0]
Hardware
Stack
HS[15]
TBH
TBL
DO[7:0]
DI[7:0]
ABUS[7:0]
BBUS[7:0]
R0
R1
R2
R3
ALUL
ALUR
Flag
ALU
GPR
RBUS
SR1
ILH
SR0
ILL
ILX
IDL0
Data Memory
Address
DA[15:0]
IDH
Generation Unit
IDL1
Bank 0,1
SPR
Figure 1-1. Top Block Diagram of CalmRISC
1-3
PRODUCT OVERVIEW
S3CB018/FB018
The CalmRISC building blocks consist of:
— An 8-bit ALU
— 16 general purpose registers (GPR)
— 11 special purpose registers (SPR)
— 16-level hardware stack
— Program memory address generation unit
— Data memory address generation unit
16 GPR’ s are grouped into four banks (Bank0 to Bank3) and each bank has four 8-bit registers (R0, R1, R2, and
R3). SPR’ s, designed for special purposes, include status registers, link registers for branch-link instructions, and
data memory index registers. The data memory address generation unit provides the data memory address
(denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are
accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address
generation unit contains a program counter, PC[19:0], and supplies the program memory address through
PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory access.
CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage area.
CalmRISC has a 3-stage pipeline as described below:
Instruction Decode/
Data Memory Access
(ID/MEM)
Instruction Fetch
(IF)
Execution/Writeback
(EXE/WB)
Figure 1-2. CalmRISC Pipeline Diagram
As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data
memory where R is a GPR, can be one operand of an ALU instruction as shown below:
The first stage (or cycle) is Instruction Fetch stage (IF for short), where the instruction pointed to by the program
counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is Instruction Decode and
Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data
memory access is performed, if necessary. The final stage is Execute and Write-back stage (EXE/WB), where the
required ALU operation is executed and the result is written back into the destination registers.
Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction
is completely finished, but is performed immediately after the current instruction fetch is done. The pipeline stream
of instructions is illustrated in the following diagram.
1-4
S3CB018/FB018
PRODUCT OVERVIEW
/ 1
IF
/ 2
ID/MEM EXE/WB
IF ID/MEM EXE/WB
/ 3 IF ID/MEM EXE/WB
/ 4 IF IF
/ 5
ID/MEM EXE/WB
IF ID/MEM EXE/WB
/ 6 IF ID/MEM EXE/WB
Figure 1-3. CalmRISC Pipeline Stream Diagram
Most CalmRISC instructions are 1-word instructions, while same branch instructions such as “ LCALL” and “ LJT”
instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction and it takes two
clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction (CPI)
is 1 except for long branches, which take 2 clock cycles per instruction.
1-5
PRODUCT OVERVIEW
S3CB018/FB018
OSC
Control
WT
BT/WDT
SI
S0
SCK
P3.0 - P3.1
P2.0 - P2.7
Port 3
Port 2
CalmRISC
CPU
SIO
TACLK
Timer A
Timer B
SIO
TAOUT
TBCLK
TBOUT
P1.0 - P1.7
P0.0 - P0.7
Port 1
Port 0
X-Memory
1024 Byte
Y-Memory
2048 Byte
Control Register
128 Byte
(38 Byte)
ADDA
MAC
816
Figure 1-4. S3CB018/FB018 Block Diagram
1-6
S3CB018/FB018
PRODUCT OVERVIEW
PIN ASSIGNMENTS
VSS
XOUT
XIN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P3.1/SCLK/INT01
P3.0/SDAT/INT00
P2.7/TACLK
P2.6/TBOUT
P2.5/TBCLK
P2.4/TAOUT
P2.3/INT13
P2.2/INT12
P2.1/INT11
P2.0/INT10
P1.2
TEST
SI/P0.0
SO/P0.1
RESET
S3CB018
32-SOP
SCK/P0.2
BUZ/P0.3
CSI/P0.4
CSO/P0.5
9
10
11
12
13
14
15
16
(Top-View)
CSCK/P0.6
CFSYNC/P0.7
P1.0
P1.3
P1.4
P1.5
P1.6
P1.1
P1.7
Figure 1-5. 32-SOP Pin Assignment
VSS
XOUT
XIN
TEST
SI/P0.0
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P3.1/SCLK/INT01
P3.0/SDAT/INT00
P2.7/TACLK
P2.6/TBOUT
P2.5/TBCLK
P2.4/TAOUT
P2.3/INT13
P2.2/INT12
P2.1/INT11
P2.0/INT10
P1.2
S3CB018
30-SDIP
SO/P0.1
RESET
SCK/P0.2
BUZ/P0.3
CSI/P0.4
CSO/P0.5
CSCK/P0.6
CFSYNC/P0.7
P1.0
9
10
11
12
13
14
15
(Top View)
P1.3
P1.4
P1.5
P1.1
Figure 1-6. 30-SDIP Pin Assignment
1-7
PRODUCT OVERVIEW
S3CB018/FB018
I/O PIN DESCRIPTION
Table 1-1. S3CB018/FB018 Pin Descriptions (32-SOP)
Pin Description
Pin
Name
Pin
Type
Circuit
Type
Share
Pins
P0.0-P0.7
I/O
I/O port with bit programmable pins; Input and output mode are
selectable by software; Software assignable pull-up. P0.4-P0.7
can be used as inputs for comparator input CIN0-CIN3.;
Alternately they can be used as SI, SO, SCK, BUZ, CSI, CSO,
CSCK, CFSYNC.
D-2
F-10
SI, SO, SCK
BUZ, CSI,
CSO, CSCK,
CFSYNC
P1.0-P1.7
P2.0-P2.7
O
Output port with bit programmable pins; Push-pull output mode
and open-drain output mode are selected by software;
Software assignable pull-up.
E-2
I/O
I/O port with bit programmable pins; Input and output mode are
selectable by software; Software assignable pull-up; P2.0-P2.3
can be used as inputs for external interrupts INT10-INT13.
(with noise filter) ; Alternately they can be used as TAOUT,
TACLK or TBOUT, TBCLK.
D-4
D-2
INT10-INT13
TAOUT
TACLK
TBOUT
TBCLK
P3.0-P3.1
I/O
I/O port with bit programmable pins; Input or output mode
selected by software; software assignable pull-up; P3.0-P3.1
can be used as inputs for external interrupts INT00-INT01.
(with noise filter and interrupt polarity control)
D-4
INT00-INT01
Table 1-2. S3CB018/FB018 Pin Descriptions (30-SDIP)
Pin Description
Pin
Name
Pin
Type
Circuit
Type
Share
Pins
P0.0-P0.7
I/O
I/O port with bit programmable pins; Input and output mode are
selectable by software; Software assignable pull-up. P0.4-P0.7
can be used as SI, SO, SCK, BUZ, CSI, CSO, CSCK,
CFSYNC, Alternately.
D-2
F-10
SI, SO, SCK
BUZ, CSI,
CSO, CSCK,
CFSYNC
P1.0-P1.5
P2.0-P2.7
O
O port with bit programmable pins; Push-pull output mode and
open-drain output mode are selected by software; Software
assignable pull-up.
E-2
I/O
I/O port with bit programmable pins; Input and output mode are
selectable by software; Software assignable pull-up; P2.0-P2.3
can be used as inputs for external interrupts INT10-INT13.
(with noise filter); Alternately they can be used as TAOUT,
TACLK or TBOUT, TBCLK.
D-4
D-2
INT10-INT13
TAOUT
TACLK
TBOUT
TBCLK
P3.0-P3.1
I/O
I/O port with bit programmable pins; Input or output mode
selected by software; software assignable pull-up; P3.0-P3.1
can be used as inputs for external interrupts INT00-INT01.
(with noise filter and interrupt polarity control)
D-4
INT00-INT01
NOTE: In S3CB018/FB018, the CSI, CSO, CSCK, CFSYNC pins are shared with P0.7-P0.4.
1-8
S3CB018/FB018
PRODUCT OVERVIEW
Table 1-3. I/O Pin Description
Description
Pin Name
CSI
Pin Type
I
O
I
AD/DA Serial Input (from codec)
CSO
AD/DA Serial Output (to codec)
AD/DA Serial Clock (from codec)
AD/DA Sync signal (from codec)
Serial data input
CSCK
CFSYNC
SI
I
I/O
I/O
I/O
I/O
I
SO
Serial data output
SCK
Serial I/O interface clock signal
BUZ
0.5 kHz, 1 kHz, 2 kHz, or 4 kHz frequency output at 4.19 MHz for buzzer sound
INT10-INT13
External interrupts. Stop release. Can’ t be masked by S/W individually but
wholly.
TAOUT
TACLK
TBOUT
TBCLK
INT00-INT01
SDAT
I/O
I/O
I/O
I/O
I
Timer A interval mode output
Timer A counter external clock input
Timer B interval mode output
Timer B counter external clock input
External interrupts. Stop release. Can be masked by S/W individually.
Serial data for Programmable memory
Serial clock for Programmable memory
Power supply
I
SCLK
I
VDD
–
VSS
–
Ground
TEST
–
Test signal input
RESET
X , X
I
Reset signal
–
Crystal, ceramic and RC oscillator signal for system clock (For external clock
IN
OUT
input, use X and input X 's reverse phase to X )
IN
IN
OUT
1-9
PRODUCT OVERVIEW
S3CB018/FB018
PIN ASSIGNMENTS
P0.0
P0.1
P0.2
1
2
3
4
5
6
7
8
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
XDA4
XDA5
XDA6
GND
XDA7
XDA8
XDA9
V
DD
P0.3
P0.4
P0.5
GND
P0.6
P0.7
V /V
DD DDI
9
XDA10
XDA11
XDA12
XDA13
GND
TEST
PA0
PA1
PA2
VDD/VDDI
PA3
PA4
PA5
GND
PA6
PA7
V
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
DD
P1.0
P1.1
P1.2
P1.3
GND
P1.4
P1.5
P1.6
P1.7
GND
S3EB010
160-QFP
X
IN
XOUT
V
/V
DDI DD
P2.0
P2.1
P2.2
(Top-View)
PA8
PA9
V
DD
PA10
PA11
GND
PA12
PA13
PA14
PA15
VDD
PA16
PA17
PA18
PA19
BKREQX
P2.3
P2.4
GND
P2.5
P2.6
P2.7
VDD
P3.0
P3.1
GND
TMODE
82
81
PIN_RESB
Figure 1-7. S3EB010 Pin Diagram
1-10
S3CB018/FB018
PRODUCT OVERVIEW
Table 1-4. Evaluation Chip Pin Descriptions
No.
1-3
5-9
Pin Name
P0.0-P0.2
Pin Type
Description
I/O
Port 0
Port 1
P0.3-P0.7
12-15
17-20
22
P1.0-P1.3
P1.4-P1.7
O
X
I
Clock In
Clock Out
Port 2
IN
X
23
O
OUT
25-27
29, 30
32, 34
36, 37
39
P2.0-P2.2
P2.3, P2.4
P2.5-P2.7
P3.0, P3.1
TMODE
I/O
I/O
Port 3
I
I
I
I
Test Mode pin; 1: skip warm-up time, 0: normal mode
Asynchronous reset, active low
40
PIN_RESB
JTAGSEL
41
JTAG mode select; 1: parallel, 0: serial
JTAG/UART pin
42
PNTRST_STSTEINI
T
44
45
46
PTCK_MCLK
PTMS
I
I
I
JTAG/UART pin
JTAG/UART pin
JTAG/UART pin
PTDI_RXD
47
49
PTDO_TXD
NPMWE
O
O
O
O
O
I
JTAG/UART pin
Program Memory Write Enable, active low
Program Memory Output Enable, active low
Program Memory Chip Select, active low
Run Status Indicator
50
NPMOE
51
NPMCS
52
RUNST
54
OUTDIS
I/O PAD Disable for debugger
55
DOCNTX
XDOCNTX
NPM64KW
PD15-PD14
PD13-PD11
PD10-PD8
PD7-PD4
PD3-PD0
I
Data Bus Output Control
56
I
External X-Memory Data Bus Output Control
Up to 64KW Program Memory, active low
Program Memory Data Bus
57
I
59, 60
62-64
66-68
70-73
75-78
I/O
1-11
PRODUCT OVERVIEW
S3CB018/FB018
Table 1-4. Evaluation Chip Pin Descriptions (Continued)
No.
80
Pin Name
Pin Type
Description
ICLKO
O
I
ICLK Output
81
BKREQX
PA19-PA16
PA15-PA12
PA11-PA8
PA7, PA6
PA5-PA3
PA2-PA0
TEST
Break input for debugger
Program Memory Address
82-85
87-90
92-95
97, 98
100-102
104-106
107
O
I
Test pin for debugger
109-112
114-116
118-124
126-129
131-134
136-138
140-144
146
XDA13-XDA10
XDA9-XDA7
XDA6-XDA0
XD0-XD3
XD4-XD7
XD8-XD10
XD11-XD15
CSNXH
O
External X-Memory Address
I/O
External X-Memory Data Bus
O
O
O
O
O
O
O
O
O
I
External X-Memory High Byte Chip Select, active low
External X-Memory Low Byte Chip Select, active low
External X-Memory Write Enable, active low
External X-Memory Output Enable, active low
External I/O Word Chip Select, active low
External I/O Byte Chip Select, active low
External I/O Even Indicator; 1:Even, 0: Odd
External I/O Write Enable, active low
External I/O Output Enable, active low
AD / DA Serial Input (from codec)
147
CSNXL
148
WENX
149
OENX
151
CSNWIO
CSNBIO
EVENIO
WENIO
152
153
154
155
OENIO
157
CSIN
158
CSCLK
I
AD / DA Serial Clock (from codec)
159
CFSYNC
CSOUT
I
AD / DA Sync signal (from codec)
160
O
–
AD / DA Serial Output (to codec)
VDD
Power supply
4, 11, 24, 28, 35, 43, 53, 61, 69, 86, 96, 103, 113
125, 135, 145, 156
GND
Ground
–
8, 16, 21, 31, 38, 48, 58, 65, 74, 79, 91, 99, 108, 117
130, 139, 150
1-12
S3CB018/FB018
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-up
Enable
P-Channel
I/O
Pull-Up
Resistor
Data
Circuit
Type C
In
Output
Disable
Schmitt Trigger
Figure 1-8. Pin Circuit Type B (RESET)
Figure 1-10. Pin Circuit Type D-2
(P0.0-P0.3, P2.4-P2.7)
VDD
Pull-up
Enable
VDD
P-Channel
I/O
Data
P-Channel
Circuit
Type C
Data
Output
Disable
Out
N-Channel
Output
Disable
Noise
Filter
Ext. INT
Schmitt Trigger
Input
Figure 1-11. Pin Circuit Type D-4 (P2.0-P2.3, P3)
Figure 1-9. Pin Circuit Type C
1-13
PRODUCT OVERVIEW
S3CB018/FB018
VDD
VDD
Pull-up
Enable
Open-drain
Enable
P-Channel
Out
Data
Circuit
Type C
I/O
Output
Disable
Data
N-Channel
Comparator
Enable
Input
Reserved
Figure 1-12. Pin Circuit Type E-2 (P1)
Figure 1-13. Pin Circuit Type F-10 (P0.4-P0.7)
1-14
S3CB018/FB018
ELECTRICAL DATA
18 ELECTRICAL DATA
OVERVIEW
Table 18-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Unit
V
Supply voltage
Input voltage
Output voltage
Output current
high
–
– 0.3 to + 6.0
V
DD
V
– 0.3 to V + 0.3
–
–
I
DD
V
– 0.3 to V + 0.3
O
DD
I
One I/O pin active
– 18
– 60
mA
OH
All I/O pins active
One I/O pin active
Total pin current for ports 1, 2, 3
–
I
Output current
low
+ 30
OL
+ 100
°
C
T
Operating
– 40 to + 85
A
temperature
T
Storage
–
– 65 to + 150
STG
temperature
Table 18-2. D.C. Electrical Characteristics
= 1.8 V to 5.5 V)
DD
°
°
(T = – 40 C to + 85 C, V
A
Parameter
Operating Voltage
(HSX mode)
Symbol
Conditions
Min
Typ
Max
Unit
V
F
= 20 MHz
4.5
–
5.5
V
DD
CPU
F
F
= 3 MHz
1.8
4.5
5.5
5.5
CPU
V
= 10 MHz
Operating Voltage
(MSX mode)
–
DD
CPU
F
= 3 MHz
1.8
5.5
CPU
18-1
ELECTRICAL DATA
S3C
°
°
(T
=
40
C, V
= 1.8 V to 5.5 V)
Conditions
A
Parameter
Min
Max
Unit
V
0.8 V
–
V
IH1
IH2
DD
X
V 0.1
-
DD
IH2
V
All input pins except V
0.2 V
Input low voltage
–
–
–
IL1
IL2
DD
V
X
0.1
–
IL2
IN
V
V
= 5V; I = -1 mA
V
-1.0
DD
Output high voltage
Output low voltage
V
OH1
DD
OH
All output pins
= 5V; = 8 mA
OL
V
V
I
–
2
OL1
DD
All output pins except VOL2
V
I
V
= 5V;
I
= 15 mA, Port 1
2
3
OL2
DD
OL
V
= V
DD
Input high leakage
current
–
–
–
–
uA
LIH1
IN
All input pins except I
LIH2
LIL2
I
V
= V
20
-3
LIH2
IN
DD
IN
X , XT
IN
I
V
= 0 V
Input low leakage
current
LIL1
IN
All input pins except I
V = 0 V
IN
I
-20
LIL2
X , XT , RESET
IN
IN
I
V
= V
Output high leakage
current
–
–
–
–
3
uA
LOH
OUT
DD
All I/O pins and Output pins
V = 0 V
OUT
I
Output low leakage
current
-3
LOL
All I/O pins and Output pins
°
R
Oscillator feed back
resistors
510
710
910
kW
V
X
= 5.0 V, T = 25 C, X = V
,
,
osc1
DD
A
IN
DD
(HSX)
= 0V
OUT
°
R
osc2
510
2.0
30
710
2.7
50
910
3.5
70
V
X
= 5.0 V,T = 25 C, X = V
,
DD
A
IN
DD
(MSX)
= 0V
OUT
°
= 5.0 V, T = 25 C, X = V
A IN DD
R
osc3
MW
kW
V
X
DD
(LSX)
= 0V
OUT
R
Pull-up resistor
V
= 0 V; V = 5 V ± 10%
L1
IN
DD
°
Ports 0,1,2,3,4,5 T =25 C
A
R
L2
110
210
310
V
= 0 V; V = 5 V ± 10%
IN
DD
°
T =25 C, RESET only
A
18-2
S3CB018/FB018
ELECTRICAL DATA
Table 18-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
(1)
(2)
Operating mode: V = 5 V ± 10%
–
10
20
mA
Supply current
I
DD
DD1
20 MHz crystal oscillator(HSX)
5 MHz crystal oscillator(MSX)
4
2
8
4
V
= 3 V ± 10%
DD
5 MHz crystal oscillator(MSX)
(3)
Idle mode: V = 5 V ± 10%
–
–
2.5
5
mA
uA
I
DD
DD2
20 MHz crystal oscillator(HSX)
5 MHz crystal oscillator(MSX)
1
2
V
= 3 V± 10%
0.4
0.8
DD
5 MHz crystal oscillator(MSX)
I
Stop mode
0.5
0.2
3
DD3
V
= 5 V ± 10%
DD
V
= 3 V ± 10%
1.2
DD
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. In operating current test mode Timer A and Timer B are running.
3. In idle current test mode the Watch timer is running.
4. The operating and idle currents are measured at weak mode.
Table 18-3. A. C. Electrical Characteristics
°
°
(T = –40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
P2.0 - P2.3, P3.0 - P3.1
Min
Typ
Max
Unit
t
,
Interrupt input high,
low width
200
–
–
ns
INTH
V
= 5V
t
DD
INTL
t
RESET input
low width
1
–
–
us
V
= 5V ± 10%
RSL
DD
NOTE: User must keep a value larger than the min value.
18-3
ELECTRICAL DATA
S3CB018/FB018
tINTL
tINTH
0.8 VDD
0.2 VDD
Figure 18-1. Input Timing for External Interrupts
tRSL
RESET
0.2 VDD
Figure 18-2. Input Timing for RESET
18-4
S3CB018/FB018
ELECTRICAL DATA
Table 18-4. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
Data retention
supply voltage
1.5
–
5.5
V
DDDR
I
V
= 1.5V
Data retention
supply current
–
–
2
µA
DDDR
DDDR
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
RESET
Occur
Oscillation
Stabilization Time
Stop Mode
Normal
Data Retention Mode
Operating Mode
VDD
VDDDR
Execution of
STOP Instruction
RESET
0.2VDD
tWAIT
NOTE: tWAIT is the same as 2048 x 32 x 1/fxx
Figure 18-3. Stop Mode Release Timing When Initiated by a RESET
18-5
ELECTRICAL DATA
S3CB018/FB018
Oscillation
Stabilization Time
Osc Start
up time
Normal
Stop Mode
Operating
Mode
Data Retention
VDD
INT
VDDDR
Execution of
STOP Instruction
0.2VDD
tWAIT
tWAIT is the same as 2048 x 32 x 1/fxx. The value of 2048 which is selected for the clock
source of the basic timer counter can be changed. Then the value of tWAIT will be changed
and ,when you select 16 instead of 32, the value of twait will also be changed.
NOTE:
Figure 18-4. Stop Mode Release Timing When Initiated by Interrupts
18-6
S3CB018/FB018
ELECTRICAL DATA
Table 18-5. Synchronous SIO Electrical Characteristics
°
°
(T = – 40 C to + 85 C V = 4.5 V to 5.5 V, V = 0 V, fxx = 10 MHz oscillator )
A
DD
SS
Conditions
–
Parameter
Symbol
Min
Typ
Max
Unit
t
SCK Cycle time
200
–
–
–
ns
CYC
t
Serial Clock High
Width
–
–
–
–
–
60
60
–
–
–
–
–
–
SCKH
t
Serial Clock Low
Width
–
50
–
SCKL
t
Serial Output data
delay time
OD
t
Serial Input data
setup time
40
100
ID
t
Serial Input data
Hold time
–
IH
tCYC
SCKL
SCKH
t
t
SCK
DD
0.8 V
DD
0.2 V
tID
tIH
DD
0.8 V
SI
Input Data
0.2 VDD
tOD
SO
Output Data
Figure 18-5. Serial Data Transfer Timing
18-7
ELECTRICAL DATA
S3CB018/FB018
Table 18-6. Main Oscillator Frequency
= 1.8 V to 5.5 V)
DD
°
°
(T = -40 C + 85 C, V
A
Oscillator
Clock Circuit
Test Condition
LSX mode
Min
Typ
Max
Unit
Crystal
32
32.768
35
kHz
XIN
XOUT
C1
C2
MSX mode
HSX mode
LSX mode
0.4
0.4
32
–
–
10
20
35
MHz
kHz
Ceramic
32.768
XIN
XOUT
C1
C2
MSX mode
HSX mode
LSX mode
0.4
0.4
32
–
–
10
20
35
MHz
kHz
External clock
XIN
XOUT
32.768
MSX mode
HSX mode
0.4
0.4
1.4
–
–
2
10
20
MHz
MHz
r = 22Kohm, V = 5 V
RC
2.6
DD
Direct soldering
NOTES:
1. Keep the wiring length as short as possible.
2. Do not cross the wiring with the other signal lines.
3. Do not route the wiring near a signal line through which a high fluctuating current flows.
4. Always make the ground point of the oscillator capacitor the same potential as VSS.
5. Do not ground the capacitor to a ground pattern through which a high current flows.
6. Do not fetch signals from the oscillator.
18-8
S3CB018/FB018
ELECTRICAL DATA
3000
2500
2000
1500
1000
15K
22K
30K
33K
36K
62K
82K
120K
180K
300K
500
0
1.8
2V
3V
4V
5V
5.5V
6V
VDD [V]
Figure 18-6. RC Oscillator Characteristic Curve
18-9
ELECTRICAL DATA
S3CB018/FB018
Table 18-7. Main Oscillator Oscillation Stabilization Time (t
)
ST1
°
°
(T = -40 C + 85 C, V
= 4.5 V to 5.5 V)
A
DD
Oscillator
Test Condition(Normal mode)
Min
Typ
Max
Unit
V
= minimum oscillation voltage range.
HSX
MSX
LSX
Crystal
–
–
10
ms
DD
Ceramic
–
–
–
4
–
ms
ns
X
V
input high and low level width (t , t
)
)
External clock
50
IN
XH XL
= minimum oscillation voltage range.
Crystal
–
–
–
–
100
50
ms
ms
ns
DD
Ceramic
X
V
input high and low level width (t , t
XH XL
External clock
50
–
–
–
IN
= minimum oscillation voltage range.
32768Hz
Crystal
200
500
ms
DD
NOTE: Oscillation stabilization time (t
) is the time that is required to stabilize oscillation after a reset or STOP mode
ST1
release.
1/fosc1
tXL
tXH
XIN
DD
V
- 0.1 V
0.1 V
Figure 18-7. Clock Timing Measurement at X
IN
18-10
S3CB018/FB018
ELECTRICAL DATA
fCPU
B
20 MHz
10 MHZ
3 MHZ
A
0.4 MHz
1
2
3
4
5
6
7
1.8
4.5
5.5
Supply Voltage (V)
Minimum instruction clock = 1/1 x oscillator frequency
Figure 18-8. HSX Mode Operating Voltage Range
fCPU
B
10 MHz
A
3 MHZ
0.4 MHz
1
2
3
4
5
6
7
1.8
4.5
5.5
Supply Voltage (V)
Minimum instruction clock = 1/1 x oscillator frequency
Figure 18-9. MSX Mode Operating Voltage Range
18-11
S3CB018/FB018
MECHANICAL DATA
19 MECHANICAL DATA
OVERVIEW
The S3CB018/FB018 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package
(32-SOP-450A). Package dimensions are shown in Figures 20-1 and 20-2.
#30
#16
0-15
30-SDIP-400
#1
#15
27.88MAX
27.48
± 0.2
±
0.56 0.1
1.778
±
(1.30)
1.12 0.1
NOTE: Dimensions are in millimeters.
Figure 19-1. 30-Pin SDIP Package Dimensions
19-1
MECHANICAL DATA
S3CB018/FB018
#32
#17
32-SOP-450A
#1
#16
+ 0.1
0.20
- 0.05
19.90 ±
0.2
1.27
(0.43)
0.40 ± 0.1
NOTE: Dimensions are in millimeters
Figure 19-2. 32-SOP-450A Package Dimensions
19-2
S3CB018/FB018
S3FB018
20 S3FB018 FLASH MCU
OVERVIEW
The S3FB018 single-chip CMOS microcontroller is the FLASH version of the S3CB018 microcontroller.
It has an on-chip FLASH ROM instead of masked ROM. The FLASH ROM is accessed in serial data format.
The S3FB018 is fully compatible with the S3CB018, both in function and in pin configuration. Because of its simple
programming requirements, the S3FB018 is ideal for use as an evaluation chip for the S3CB018.
20-1
S3FB018
S3CB018/FB018
PIN ASSIGNMENTS
V
SS
VDD
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OUT
X
SCLK
P3.1/INT01/
XIN
P3.0/INT00/SDAT
P2.7/TACLK
P2.6/TBOUT
P2.5/TBCLK
P2.4/TAOUT
P2.3/INT13
P2.2/INT12
P2.1/INT11
P2.0/INT10
P1.2
V
PP
/TEST
SI/P0.0
SO/P0.1
S3FB018
32-SOP
RESET
/
RESET
SCK/P0.2
BUZ/P0.3
CSI/P0.4
CSO/P0.5
CSCK/P0.6
CFSYNC/P0.7
P1.0
9
10
11
12
13
14
15
16
(Top-View)
P1.3
P1.4
P1.5
P1.6
P1.1
P1.7
Figure 20-1. 32-SOP Pin Assignment
V
XOUT
XIN
SS
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
V
DD
P3.1/INT01/SCLK
P3.0/INT00/SDAT
P2.7/TACLK
P2.6/TBOUT
P2.5/TBCLK
P2.4/TAOUT
P2.3/INT13
P2.2/INT12
P2.1/INT11
P2.0/INT10
P1.2
V
PP/TEST
SI/P0.0
SO/P0.1
S3FB018
30-SDIP
RESET
/
RESET
SCK/P0.2
BUZ/P0.3
CSI/P0.4
CSO/P0.5
CSCK/P0.6
CFSYNC/P0.7
P1.0
9
10
11
12
13
14
15
(Top View)
P1.3
P1.4
P1.5
P1.1
Figure 20-2. 30-SDIP Pin Assignment
20-2
S3CB018/FB018
S3FB018
Table 20-1. Descriptions of Pins Used to Read/Write the FLASH ROM
During Programming
Main Chip
Pin Name
P3.0
Pin Name
Pin No.
I/O
Function
SDAT
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input/push-
pull output port.
30(28)
I/O
P3.1
SCLK
Serial clock pin. Input only pin.
31(29)
4
I/O
I
TEST
Vpp (TEST)
Power supply pin for FLASH ROM cell writing
(indicates that FLASH enters into the writing mode).
When 12.5 V is applied, FLASH is in writing mode
and, when 5 V is applied, FLASH is in the reading
mode. When FLASH is operating , hold GND.
RESET
RESET
Chip Initialization
7
I
V
/V
V
/V
Logic power supply pin. V should be tied to
32/1(30/1)
–
DD SS
DD SS
DD
+5 V during programming.
NOTE: Pin No. is for 100 QFP type package. (for 100 TQFP, the pins with the same name have same functions).
Table 20-2. Comparison of S3FB018 and S3CB018 Features
Characteristic
Program Memory
Operating Voltage (V
S3FB519
4K word (8K byte) FLASH ROM
1.8 V to 5.5 V
S3CB519
4K word (8K byte) FLASH ROM
1.8 V to 5.5 V
)
DD
V
= 5 V, V (TEST) = 12.5 V
PP
OTP Programming Mode
Pin Configuration
DD
32-SOP/30-SDIP
32-SOP/30-SDIP
FLASH ROM Programmability User programmable
Programmed at the factory
20-3
S3FB018
S3CB018/FB018
Table 20-3. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Unit
V
Supply voltage
Input voltage
Output voltage
Output current
high
–
– 0.3 to + 6.0
V
DD
V
– 0.3 to V + 0.3
–
I
DD
V
– 0.3 to V + 0.3
–
One I/O pin active
All I/O pins active
One I/O pin active
Total pin current for ports 1, 2, 3
–
O
DD
I
– 18
– 60
mA
OH
I
Output current
low
+ 30
OL
+ 100
°
C
T
Operating
– 40 to + 85
A
temperature
T
Storage
–
– 65 to + 150
STG
temperature
Table 20-4. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Operating Voltage
(HSX mode)
Symbol
Conditions
= 20 MHz
Min
Typ
Max
Unit
V
F
4.5
–
5.5
V
DD
CPU
F
F
= 3 MHz
1.8
4.5
5.5
5.5
CPU
V
= 10 MHz
Operating Voltage
(MSX mode)
–
DD
CPU
F
= 3 MHz
1.8
5.5
CPU
20-4
S3CB018/FB018
S3FB018
Table 20-4. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
V
All input pins except V
0.8 V
DD
V
DD
Input high voltage
–
V
IH1
IH2
V
X
V 0.1
-
DD
IH2
IN
V
V
All input pins except V
0.2 V
Input low voltage
–
–
DD
IL1
IL2
X
0.1
–
IL2
IN
V
V
= 5V; I = -1 mA
V
-1.0
DD
Output high voltage
Output low voltage
–
–
V
OH1
DD
OH
All output pins
= 5V; = 8 mA
OL
V
V
I
–
2
OL1
DD
All output pins except VOL2
V
I
V
= 5V;
I
= 15 mA, Port 1
2
3
OL2
DD
OL
V
= V
DD
Input high leakage
current
–
–
–
–
uA
LIH1
IN
All input pins except I
LIH2
LIL2
I
V
= V
20
-3
LIH2
IN
DD
IN
X , XT
IN
I
V
= 0 V
Input low leakage
current
LIL1
IN
All input pins except I
V = 0 V
IN
I
-20
LIL2
X , XT , RESET
IN
IN
I
V
= V
Output high leakage
current
–
–
–
–
3
uA
LOH
OUT
DD
All I/O pins and Output pins
V = 0 V
OUT
I
Output low leakage
current
-3
LOL
All I/O pins and Output pins
°
R
Oscillator feed back
resistors
510
710
910
kW
V
X
= 5.0 V, T = 25 C
osc1
DD
A
(HSX)
= V , X = 0V
OUT
IN
DD
°
R
510
2.0
30
710
2.7
50
910
3.5
70
V
X
= 5.0 V, T = 25 C
osc2
DD
A
(MSX)
= V , X = 0V
OUT
IN
DD
°
R
osc3
MW
kW
V
X
= 5.0 V, T = 25 C
DD
A
(LSX)
= V , X = 0V
OUT
IN
IN
DD
R
Pull-up resistor
V
= 0 V; V = 5 V ± 10%
L1
DD
°
Ports 0,1,2,3,4,5 T =25 C
A
R
L2
110
210
310
V
= 0 V; V = 5 V ± 10%
IN
DD
°
T =25 C, RESET only
A
20-5
S3FB018
S3CB018/FB018
Table 20-4. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
(1)
(2)
Operating mode: V = 5 V ± 10%
–
10
20
mA
Supply current
I
DD
DD1
20 MHz crystal oscillator(HSX)
5 MHz crystal oscillator(MSX)
4
2
8
4
V
= 3 V ± 10%
DD
5 MHz crystal oscillator(MSX)
(3)
Idle mode: V = 5 V ± 10%
–
–
2.5
5
mA
uA
I
DD
DD2
20 MHz crystal oscillator(HSX)
5 MHz crystal oscillator(MSX)
1
2
V
= 3 V± 10%
0.4
0.8
DD
5 MHz crystal oscillator(MSX)
I
Stop mode
0.5
0.2
3
DD3
V
= 5 V ± 10%
DD
V
= 3 V ± 10%
1.2
DD
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. In operating current test mode Timer A and Timer B are running.
3. In idle current test mode the Watch timer is running.
4. The operating and idle currents are measured at weak mode.
20-6
相关型号：
S3CB519XX-QX
RISC Microcontroller, 8-Bit, MROM, 10.24MHz, CMOS, PQFP100, 14 X 20 MM, QFP-100
SAMSUNG
©2020 ICPDF网 联系我们和版权申明