S3C9664XX-AM [SAMSUNG]

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDIP24, 0.300 INCH, SDIP-24;
S3C9664XX-AM
型号: S3C9664XX-AM
厂家: SAMSUNG    SAMSUNG
描述:

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDIP24, 0.300 INCH, SDIP-24

时钟 微控制器 光电二极管 外围集成电路
文件: 总148页 (文件大小:784K)
中文:  中文翻译
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S3C9664/P9664 (Preliminary Spec)  
PRODUCT OVERVIEW  
1
PRODUCT OVERVIEW  
SAM87RI PRODUCT FAMILY  
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide  
range of integrated peripherals, and support OTP device.  
A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming  
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating  
modes are included to support real-time operations.  
S3C9664 MICROCONTROLLER  
The S3C9664 microcontroller with USB function can be used in a wide range of general purpose applications. It  
is especially suitable for joystick, game pad controller or mouse and is available in 20-pin DIP, 24-pin SDIP and  
20, 24-pin SOP. The S3C9664 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process.  
It is built around the powerful SAM88RCRI CPU core.  
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register  
space, the size of the internal register file was logically expanded. The S3C9664 has 4 K bytes of program  
memory on-chip, and 208 bytes of RAM including 16 bytes of working register. Using the SAM88RCRI design  
approach, the following peripherals were integrated with the SAM88RCRI core:  
— Two configurable I/O ports (14 I/O pins on 20 pin package, 18 I/O pins on 24pin package)  
— Analog-to-digital converter with six input channel and 10-bit resolution  
— One 8-bit basic timer for watchdog function  
— One 8 bit timer/counter with three operating modes (Timer 0)  
— One 8 bit timer (Timer 1)  
OTP  
The S3C9664 microcontroller is also available in OTP (One Time Programmable) version, S3P9664. S3P9664  
microcontroller has an on-chip 4 K byte one-time-programmable EPROM instead of masked ROM.  
The S3P9664 is compatible to S3C9664, both in function and in pin configuration.  
1-1  
PRODUCT OVERVIEW  
S3C9664/P9664 (Preliminary Spec)  
FEATURES  
CPU  
USB  
SAM88RCRI CPU core  
Compatible to USB low speed (1.5 Mbps) device  
1.1 specification.  
Memory  
Serial bus interface engine (SIE)  
4-K byte internal program memory  
— Packet decoding/generation  
208-byte general purpose register area  
16 bytes of working register  
— CRC generation and checking  
— NRZI encoding/decoding and bit-stuffing  
Two 8-byte receive/transmit USB buffer  
Instruction Set  
41 instructions  
A/D Converter  
IDLE and STOP instructions added for power-  
down modes  
Six analog input pins  
10-bit conversion resolution  
Instruction Execution Time  
0.66 ms at 6 MHz fOSC  
Low Voltage Reset  
Low voltage reset  
Power on Reset  
Interrupts  
28 interrupt sources and one vector (24 pins)  
Sub Oscillator  
24 interrupt sources and one vector (20 pin)  
One interrupt level  
Internal RC sub oscillator  
Auto interrupt wake-up  
General I/O  
Oscillator Frequency  
Three I/O ports (total 18 I/O pins at 24  
SOP/SDIP)  
6 MHz crystal/ceramic oscillator  
External clock source (6 MHz)  
Three I/O ports (total 14 I/O pins at 20  
SOP/DIP)  
Operating Temperature Range  
° °  
– 40 C to + 85 C  
Timer/Counter  
One 8-bit basic timer for watchdog function  
Operating Voltage Range  
4.0 V to 5.25 V  
One 8 bit timer/counter with three operating  
modes(Match, capture, PWM)  
One 8-bit Timer  
Package Types  
24-pin SOP/SDIP  
20-pin SOP/DIP  
1-2  
S3C9664/P9664 (Preliminary Spec)  
PRODUCT OVERVIEW  
BLOCK DIAGRAM  
P1.0/INT1/ADC0  
P1.1/INT1/ADC1  
P1.2/INT1/ADC2  
P1.3/INT1/ADC3  
TEST  
RESET  
Port 1/  
AD  
Converter  
Port I/O and  
Interrupt Control  
P1.4/INT1/ADC4  
P1.5/INT1/ADC5  
P1.7/INT1  
XIN  
OSC  
XOUT  
P1.8/INT1  
SUB  
OSC  
P0.0/INT0/T0  
P0.1/INT0  
P0.2/INT0  
P0.3/INT0  
P0.4/INT0  
Basic  
Timer  
SAM88RCRI CPU  
Port 0  
P0.5/INT0  
P0.6/INT0  
P0.7/INT0  
Timer 0  
Timer 1  
D+/INT2  
D-/INT2  
208 Byte  
RAM  
USB  
SIE  
4K ROM  
NOTES:  
1. 24 SOP/SDIP  
2. 20 SOP/DIP  
Figure 1-1. Block Diagram  
1-3  
PRODUCT OVERVIEW  
S3C9664/P9664 (Preliminary Spec)  
PIN ASSIGNMENTS  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VSS  
XOUT  
XIN  
1
2
3
4
5
6
7
8
9
10  
VDD  
D-/P2.0/INT2  
D+/P2.1/INT2  
P1.0/AD0/INT1  
P1.1/AD1/INT1  
P1.2/AD2/INT1  
P1.3/AD3/INT1  
P1.4/AD4/INT1  
P1.5/AD5/INT1  
P0.5/INT0  
S3C9664  
TEST  
P0.0/INT0/T0 (CAP/PWM)  
P0.1/INT0  
(20-SOP-300)  
(20-DIP-300)  
RESET  
P0.2/INT0  
P0.3/INT0  
P0.4/INT0  
Figure 1-2. Pin Assignment (20 Pin)  
VDD  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VSS  
XOUT  
XIN  
1
2
3
4
5
6
7
8
D-/P2.0/INT2  
D+/P2.1/INT2  
P1.0/AD0/INT1  
P1.1/AD1/INT1  
P1.2/AD2/INT1  
P1.3/AD3/INT1  
P1.4/AD4/INT1  
P1.5/AD5/INT1  
P0.5/INT0  
TEST  
S3C9664  
P0.0/INT0/T0 (CAP/PWM)  
P0.1/INT0  
RESET  
P0.2/INT0  
P0.3/INT0  
P0.4/INT0  
P0.6/INT0  
P0.7/INT0  
(24-SOP-300)  
(24-SDIP-300)  
9
10  
11  
12  
P1.6/INT1  
P1.7/INT1  
Figure 1-3. Pin Assignment (24 Pin)  
1-4  
S3C9664/P9664 (Preliminary Spec)  
PRODUCT OVERVIEW  
Table 1-1. Pin Descriptions  
Pin  
Name  
In/Out  
Pin  
Description  
Pin  
Type  
Pin  
Numbers  
Share  
Pins  
P0.0–  
P0.7  
I/O  
Bit-programmable I/O port for Schmitt trigger input ,  
push-pull output and N-Ch open drain output.  
Pull-up/ pull-down resistors are assignable by  
software. Port1 pins can also be used as external  
interrupt.  
G
5,6,8–11  
T0, INT0  
(5,6,8–12,15)  
F
P1.0-  
P1.5  
I/O  
Bit-programmable I/O port for Schmitt trigger input,  
Schmitt trigger input with pull-up and N-Ch open  
drain output.  
12–17  
AD0–5  
INT1  
(16–21)  
Port1 pins can also be used as A/D converter  
Channel.  
P1.6-  
P1.7  
I/O  
I/O  
Bit-programmable I/O port for Schmitt trigger input ,  
Schmitt trigger input with pull-up and N-Ch open  
drain output and Push-pull output.  
E
E
(13–14)  
INT1  
INT2  
P2.0/D–  
Bit-programmable I/O port for Schmitt trigger input ,  
Schmitt trigger input with pull-up and N-Ch open  
drain output and Push-pull output. Port 2 can be  
individually configured as external interrupt inputs.  
Also it can be configured as an USB ports  
18–19  
(22–23)  
P2.1/D+  
XIN,  
Crystal/ceramic oscillator signal for system clock.  
2–3 (2–3)  
XOUT  
I
I
System reset signal input pin.  
B
7 (7)  
4 (4)  
RESET  
TEST  
Test signal input pin(for factory use only; muse be  
connected to VSS  
)
VDD  
Voltage input pin and ground  
1,20 (1,24)  
,VSS  
T0  
I/O  
I
Timer 0 capture input or PWM output pin  
External interrupt input  
G
G
6 (6)  
5,6,8–11  
P0.0  
INT0  
P0.0–P0.7  
(5,6,8–12,15)  
12–17  
INT1  
I
External interrupt input  
F,E  
P1.0–P1.7  
(13–14, 16–21)  
18–19  
INT2  
I
I
External interrupt input  
A/D converter input  
E
F
P2.0–P2.1  
P1.0–P1.5  
AD0–  
AD5  
12–17  
(16–21)  
NOTE: Pin numbers show in parentheses "( )" are for the 24-pin package  
1-5  
PRODUCT OVERVIEW  
S3C9664/P9664 (Preliminary Spec)  
VDD  
V
DD  
Pull-up  
Enable  
P-Channel  
Out  
Data  
Data  
Circuit  
Type C  
I/O  
N-Channel  
Output  
Output  
DIsable  
DIsable  
Data  
Figure 1-5. Pin Circuit Type D  
Figure 1-4. Pin Circuit Type C  
VDD  
VDD  
47 K  
47 K  
PNE  
VDD  
Pull-up  
Enable  
Pull-up  
Enable  
Data  
Circuit  
Type C  
In/Out  
Data  
Output  
DIsable  
In/Out  
Output  
Disable  
Data  
To ADC  
Figure 1-7. Pin Circuit Type F  
Figure 1-6. Pin Circuit Type E  
1-6  
S3C9664/P9664 (Preliminary Spec)  
PRODUCT OVERVIEW  
VDD  
47 K  
PNE  
VDD  
Pull-up  
Enable  
In/Out  
Data  
Output  
Disable  
Pull-down  
Enable  
47 K  
Figure 1-8. Pin Circuit Type G  
1-7  
S3C9664/P9664 (Preliminary Spec)  
ADDRESS SPACES  
2
ADDRESS SPACES  
OVERVIEW  
The S3C9664 microcontroller has two kinds of address space:  
— Program memory (ROM)  
— Internal register file  
A 13-bit address bus supports both program memory. Special instructions and related internal logic determine  
when the 13-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and  
data between the CPU and the internal register file.  
The S3C9664 has 4 K bytes of mask-programmable program memory on-chip. The S3C9664 microcontroller has  
192 bytes general-purpose registers in its internal register file. Forty-nine bytes in the register file are mapped for  
system and peripheral control functions.  
2-1  
ADDRESS SPACES  
S3C9664/P9664 (Preliminary Spec)  
PROGRAM MEMORY (ROM)  
NORMAL OPERATING MODE (INTERNAL ROM)  
The S3C9664 has 4 K bytes of internal mask-programmable program memory.  
The first 2 bytes of the ROM (0000H–0001H) are an interrupt vector address.  
The program reset address in the ROM is 0100H.  
1000H  
4,096  
4 K byte  
Internal  
Program  
Memory  
Area  
256  
Program Start  
0100H  
2
1
0
0002H  
0001H  
0000H  
Interrupt  
Vector  
S3C9664  
Figure 2-1. S3C9664 Program Memory Address Space  
2-2  
S3C9664/P9664 (Preliminary Spec)  
ADDRESS SPACES  
REGISTER ARCHITECTURE  
The upper 64 bytes (page 0) and the expanded one byte (FFH, page 1) of the S3C9664's internal register file are  
addressed as working registers, system control registers and peripheral control registers. The lower 192 bytes of  
internal register file (00H–BFH) is called the general purpose register space.  
For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by  
the additional of one or more register pages at general purpose register space (00H–BFH). This register file  
expansion is not implemented in the S3C9664.  
Page 0  
Page 0  
FFH  
FEH  
Peripheral Control  
Registers  
(Expanded Peripheral  
Control Register)  
E0H  
DFH  
64 Bytes of  
Common Area  
System Control  
Registers  
D0H  
CFH  
Working Registers  
C0H  
BFH  
General Purpose  
Register File  
and Stack Area  
192 Bytes  
00H  
Figure 2-2. Internal Register File Organization  
2-3  
ADDRESS SPACES  
S3C9664/P9664 (Preliminary Spec)  
COMMON WORKING REGISTER AREA (C0H–CFH)  
The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full  
advantage of shorter instruction formats to reduce execution time.  
This16-byte address range is called common area. That is, locations in this area can be used as working registers  
by operations that address any location on any page in the register file. Typically, these working registers serve  
as temporary buffers for data operations between different pages. However, because the S3C9664 uses only  
page 0, you can use the common area for any internal data operation.  
The Register (R) addressing mode can be used to access this area  
Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the  
address of the first 8-bit register is always an even number and the address of the next register is an odd number.  
The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant  
byte is always stored in the next (+ 1) odd-numbered register.  
MSB  
Rn  
LSB  
n = Even address  
Rn + 1  
Figure 2-3. 16-Bit Register Pairs  
+
PROGRAMMING TIP — Addressing the Common Working Register Area  
As the following examples show, you should access working registers in the common area, locations C0H–CFH,  
using working register addressing mode only.  
Examples:  
1. LD  
0C2H,40H  
; Invalid addressing mode!  
Use working register addressing instead:  
LD  
R2,40H  
; R2 (C2H) ¬ the value in location 40H  
2. ADD 0C3H,#45H  
; Invalid addressing mode!  
Use working register addressing instead:  
ADD R3,#45H ; R3 (C3H) ¬ R3 + 45H  
2-4  
S3C9664/P9664 (Preliminary Spec)  
ADDRESS SPACES  
SYSTEM STACK  
S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH  
and POP instructions are used to control system stack operations. The S3C9664 architecture supports stack  
operations in the internal register file.  
STACK OPERATIONS  
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are  
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents  
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to  
their original locations. The stack address is always decremented before a push operation and incremented after  
a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown  
in Figure 2-4.  
High Address  
PCL  
PCL  
PCH  
Top of  
stack  
PCH  
Top of  
stack  
Flags  
Stack contents  
after a call  
instruction  
Stack contents  
after an  
Low Address  
interrupt  
Figure 2-4. Stack Operations  
STACK POINTER (SP)  
Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,  
the SP value is undetermined.  
Because only internal memory space is implemented in the KS86C6504/P6504, the SP must be initialized to an  
8-bit value in the range 00H–BFH.  
NOTE  
In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This  
means that a Stack Pointer access invalid stack area.  
2-5  
ADDRESS SPACES  
S3C9664/P9664 (Preliminary Spec)  
+
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP  
The following example shows you how to perform stack operations in the internal register file using PUSH and  
POP instructions:  
LD  
SP,#0C0H  
; SP ¬ C0H (Normally, the SP is set to 0C0H by the  
; initialization routine)  
PUSH  
PUSH  
PUSH  
SYM  
20H  
R3  
; Stack address 0BFH ¬ SYM  
; Stack address 0BDH ¬ 20H  
; Stack address 0BCH ¬ R3  
POP  
POP  
POP  
R3  
20H  
SYM  
; R3 ¬ Stack address 0BCH  
; 20H ¬ Stack address 0BDH  
; SYM ¬ Stack address 0BFH  
2-6  
S3C9664/P9664 (Preliminary Spec)  
ADDRESSING MODES  
3
ADDRESSING MODES  
OVERVIEW  
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions  
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to  
determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition  
codes, immediate data, or a location in the register file, program memory, or data memory.  
The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are  
available for each instruction. The addressing modes and their symbols are as follows:  
— Register (R)  
— Indirect Register (IR)  
— Indexed (X)  
— Direct Address (DA)  
— Relative Address (RA)  
— Immediate (IM)  
3-1  
ADDRESSING MODES  
S3C9664/P9664 (Preliminary Spec)  
REGISTER ADDRESSING MODE (R)  
In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register  
addressing differs from Register addressing because it uses a 16-byte working register space in the register file  
and a 4-bit register within that space (see Figure 3-2).  
Program Memory  
Register File  
OPERAND  
8-bit Register  
File Address  
dst  
Point to One  
Rigister in Register  
File  
OPCODE  
One-Operand  
Instruction  
(Example)  
Value used in  
Instruction Execution  
Sample Instruction:  
DEC CNTR  
;
Where CNTR is the label of an 8-bit register address  
Figure 3-1. Register Addressing  
Register File  
CFH  
.
.
.
.
Program Memory  
4-Bit  
Working Register  
4 LSBs  
dst  
src  
OPERAND  
Point to the  
Woking Register  
(1 of 16)  
OPCODE  
Two-Operand  
Instruction  
(Example)  
C0H  
Sample Instruction:  
ADD R1, R2  
;
Where R1 = C1H and R2 = C2H  
Figure 3-2. Working Register Addressing  
3-2  
S3C9664/P9664 (Preliminary Spec)  
ADDRESSING MODES  
INDIRECT REGISTER ADDRESSING MODE (IR)  
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of  
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to  
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).  
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to  
indirectly address another memory location.  
Program Memory  
Register File  
ADDRESS  
8-Bit Register  
File Address  
dst  
Point to One  
Rigister in Register  
File  
OPCODE  
One-Operand  
Instruction  
(Example)  
Address of Operand  
used by Instruction  
OPERAND  
Value used in  
Instruction Execution  
Sample Instruction:  
RL  
@SHIFT  
;
Where SHIFT is the label of an 8-Bit register address  
Figure 3-3. Indirect Register Addressing to Register File  
3-3  
ADDRESSING MODES  
S3C9664/P9664 (Preliminary Spec)  
INDIRECT REGISTER ADDRESSING MODE (Continued)  
Register File  
Program Memory  
Example  
REGISTER  
PAIR  
dst  
Instruction  
References  
Program  
Points to  
Rigister Pair  
OPCODE  
16-Bit  
Memory  
Address  
Points to  
Program  
Memory  
Program Memory  
OPERAND  
Sample Instructions:  
Value used in  
Instruction  
CALL @RR2  
JP @RR2  
Figure 3-4. Indirect Register Addressing to Program Memory  
3-4  
S3C9664/P9664 (Preliminary Spec)  
ADDRESSING MODES  
INDIRECT REGISTER ADDRESSING MODE (Continued)  
Register File  
CFH  
.
.
.
.
Program Memory  
4-Bit  
4 LSBs  
Working  
Register  
Address  
OPERAND  
dst  
src  
Point to the  
Woking Register  
(1 of 16)  
OPCODE  
C0H  
Sample Instruction:  
OR R6, @R2  
Value used in  
Instruction  
OPERAND  
Figure 3-5. Indirect Working Register Addressing to Register File  
3-5  
ADDRESSING MODES  
S3C9664/P9664 (Preliminary Spec)  
INDIRECT REGISTER ADDRESSING MODE (Concluded)  
Register File  
CFH  
.
.
.
.
Program Memory  
4-Bit Working  
Register Address  
dst  
src  
Register  
Pair  
Next 3 Bits Point  
to Working  
Register Pair  
(1 of 8)  
OPCODE  
Example Instruction  
References either  
Program Memory or  
Data Memory  
C0H  
16-Bit  
address  
points to  
program  
memory  
or data  
Program Memory  
or  
Data Memory  
LSB Selects  
memory  
Value used in  
Instruction  
OPERAND  
Sample Instructions:  
LCD  
LDE  
LDE  
R5,@RR6  
R3,@RR14  
@RR4, R8  
; Program memory access  
; External data memory access  
; External data memory access  
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory  
3-6  
S3C9664/P9664 (Preliminary Spec)  
INDEXED ADDRESSING MODE (X)  
ADDRESSING MODES  
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to  
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access  
locations in the internal register file or in external memory.  
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of  
–128 to +127. This applies to external memory accesses only (see Figure 3-8).  
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained  
in a working register. For external memory accesses, the base address is stored in the working register pair  
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address  
(see Figure 3-9).  
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction  
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external  
program memory, and for external data memory, when implemented.  
Register File  
~
~
~
~
Value used in  
Instruction  
OPERAND  
+
Program Memory  
Base Address  
4 LSBs  
dst  
src  
INDEX  
Two-Operand  
Instruction  
Example  
Point to One of the  
Woking Register  
(1 of 16)  
OPCODE  
Sample Instruction:  
LD R0, #BASE[R1]  
;
Where BASE is an 8-bit immediate value  
Figure 3-7. Indexed Addressing to Register File  
3-7  
ADDRESSING MODES  
S3C9664/P9664 (Preliminary Spec)  
INDEXED ADDRESSING MODE (Continued)  
Program Memory  
Register File  
XS (OFFSET)  
4-Bit Working  
NEXT 3 Bits  
dst  
src  
Register  
Pair  
Register Address  
Point to Working  
Register Pair  
(1 of 8)  
OPCODE  
16-Bit  
address  
added to  
offset  
LSB Selects  
+
16-Bits  
8-Bits  
Program Memory  
or  
Datamemory  
Value used in  
Instruction  
OPERAND  
16-Bits  
Sample Instructions:  
LDC  
LDE  
R4, #04H[RR2]  
R4,#04H[RR2]  
; The values in the program address (RR2 + #04H)  
are loaded into register R4.  
; Identical operation to LDC example, except that  
external program memory is accessed.  
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset  
3-8  
S3C9664/P9664 (Preliminary Spec)  
ADDRESSING MODES  
INDEXED ADDRESSING MODE (Concluded)  
Program Memory  
Register File  
XL  
XL  
H
L
(OFFSET)  
(OFFSET)  
src  
Register  
Pair  
NEXT 3 Bits  
4-Bit Working  
Register Address  
dst  
Point to Working  
Register Pair  
(1 of 8)  
OPCODE  
16-Bit  
address  
added to  
offset  
LSB Selects  
+
16-Bits  
8-Bits  
Program Memory  
or  
Datamemory  
Value used in  
Instruction  
OPERAND  
16-Bits  
Sample Instructions:  
LDC  
LDE  
R4, #1000H[RR2]  
R4, #1000H[RR2]  
;
;
The values in the program address (RR2 + #1000H)  
are loaded into register R4.  
Identical operation to LDC example, except that  
external program memory is accessed.  
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset  
3-9  
ADDRESSING MODES  
S3C9664/P9664 (Preliminary Spec)  
DIRECT ADDRESS MODE (DA)  
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call  
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC  
whenever a JP or CALL instruction is executed.  
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for  
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.  
Program or  
Data Memory  
Memory  
Address  
Program Memory  
Used  
Upper Address Byte  
Lower Address Byte  
LSB Selects Program  
dst/src "0" or "1"  
OPCODE  
Memory or Data Memory:  
"0" = Program Memory  
"1" = Data Memory  
Sample Instructions:  
LDC  
LDE  
R5,1234H  
R5,1234H  
;
;
The values in the program address (1234H)  
are loaded into register R5.  
Identical operation to LDC example, except that  
external program memory is accessed.  
Figure 3-10. Direct Addressing for Load Instructions  
3-10  
S3C9664/P9664 (Preliminary Spec)  
ADDRESSING MODES  
DIRECT ADDRESS MODE (Continued)  
Program Memory  
Next OPCODE  
Program  
Memory  
Address  
Used  
Lower Address Byte  
Upper Address Byte  
OPCODE  
Sample Instructions:  
JP  
C,JOB1  
;
;
Where JOB1 is a 16-bit immediate address  
Where DISPLAY is a 16-bit immediate address  
CALL DISPLAY  
Figure 3-11. Direct Addressing for Call and Jump Instructions  
3-11  
ADDRESSING MODES  
S3C9664/P9664 (Preliminary Spec)  
RELATIVE ADDRESS MODE (RA)  
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified  
in the instruction. The displacement value is then added to the current PC value. The result is the address of the  
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction  
immediately following the current instruction.  
The instructions that support RA addressing is JR.  
Program Memory  
Next OPCODE  
Program Memory  
Address Used  
Current  
PC Value  
+
Displacement  
OPCODE  
Current Instruction  
Sample Instructions:  
Signed  
Displacement Value  
JR  
ULT,$ + OFFSET  
;
Where OFFSET is a value in the range + 127 to - 128  
Figure 3-12. Relative Addressing  
IMMEDIATE MODE (IM)  
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the  
operand field itself. Immediate addressing mode is useful for loading constant values into registers.  
Program Memory  
OPERAND  
OPCODE  
(The Operand value is in the instruction)  
Sample Instruction:  
LD  
R0,#0AAH  
Figure 3-13. Immediate Addressing  
3-12  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
4
CONTROL REGISTERS  
OVERVIEW  
In this section, detailed descriptions of the S3C9664 control registers are presented in an easy-to-read format.  
These descriptions will help familiarize you with the mapped locations in the register file. You can also use them  
as a quick-reference source when writing application programs.  
System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the  
standard register description format.  
Control register descriptions are arranged in alphabetical order according to register mnemonic. More information  
about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this  
manual.  
4-1  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
Table 4-1. Register Map and Reset Status (Page 0)  
Register Name  
Mnemonic  
Hex  
00-BFH  
C0H-CFH  
D0H  
R/W  
R/W  
R/W  
R
General purpose register file & Stack area  
Working register area  
Timer 0 counter register  
T0CNT  
Timer 0 data register  
T0DATA  
D1H  
R/W  
R/W  
R/W  
R/W  
R/W  
R
Timer 0 control register  
T0CON  
D2H  
Timer 0 interrupt control register  
Clock control register  
T0INT  
D3H  
CLKCON  
D4H  
System flags register  
FLAGS  
D5H  
A/D converter data register (Low byte)  
A/D converter data register (High byte)  
A/D control register  
ADDATAL  
D6H  
ADDATAH  
D7H  
R
ADCON  
D8H  
R/W  
R/W  
R/W  
Stack Pointer Register  
SP  
D9H  
Port 2 data register  
P2  
DAH  
Location DBH is not mapped.  
Basic timer control register  
Basic timer counter  
BTCON  
DCH  
DDH  
R/W  
R
BTCNT  
Location DEH is not mapped.  
System Mode Register  
SYM  
P0  
DFH  
E0H  
E1H  
E2H  
E3H  
E4H  
E5H  
E6H  
E7H  
E8H  
E9H  
EAH  
EBH  
ECH  
EDH  
EEH  
EFH  
R/W  
R/W  
R/W  
R
Port 0 data register  
Port 1 data register  
P1  
Timer 1 counter register  
T1CNT  
T1CON  
P0PURL  
P0PURH  
P0CONL  
P0CONH  
P1CONL  
P1CONH  
P0INT  
Timer 1 control register  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Port 0 pull-up/down register (low byte)  
Port 0 pull-up/down register (high byte)  
Port 0 control register (low byte)  
Port 0 control register (high byte)  
Port 1 control register (low byte)  
Port 1 control register (high byte)  
Port 0 interrupt enable register  
Port 0 interrupt pending register  
Port 1 interrupt enable register  
Port 1 interrupt pending register  
Timer 1 data register  
P0PND  
P1INT  
P1PND  
T1DATA  
Port 2 control/interrupt and Pending register  
P2CONINT  
4-2  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
Table 4-1. Register Map and Reset Status (Page 0) (Continued)  
Register Name  
USB function address register  
Mnemonic  
FADDR  
Hex  
F0H  
F1H  
F2H  
F3H  
F4H  
F5H  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
FCH  
FDH  
FEH  
FFH  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
USB control endpoint status register  
USB interrupt endpoint 1 status register  
USB control endpoint byte count register  
USB control endpoint FIFO register  
USB interrupt endpoint 1 FIFO register  
USB interrupt pending register  
EP0CSR  
EP1CSR  
EP0BCNT  
EP0FIFO  
EP1FIFO  
USBPND  
USBINT  
USB interrupt enable register  
USB power management register  
USB interrupt endpoint 2 status register  
USB interrupt endpoint 2 FIFO register  
Endpoint mode register  
PWRMGR  
EP2CSR  
EP2FIFO  
EPMODE  
EP1BCNT  
EP2BCNT  
USBCON  
SUBCON  
USB interrupt endpoint 1 byte count register  
USB interrupt endpoint 2 byte count register  
USB control register  
Sub control register  
Table 4-2. Register Map and Reset Status (Page 1)  
Register Name  
Mnemonic  
Hex  
R/W  
XCON register  
XCON  
FEH  
W
4-3  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
Bit number(s) that is/are appended to the  
register name for bit addressing  
Name of individual  
bit or bit function  
Register address  
(hexadecimal)  
Register  
Full Register name  
mnemonic  
D5H  
FLAGS - System Flags Register  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
Bit Identifier  
RESET Value  
Read/Write  
x
R/W  
x
R/W  
x
R/W  
x
R/W  
x
R/W  
x
R/W  
0
R/W  
0
R/W  
.7  
Carry Flag (C)  
0
1
Operation dose not generate a carry or borrow condition  
Operation generates carry-out or borrow into high-order bit7  
.6  
Zero Flag  
0
1
Operation result is a non-zero value  
Operation result is zero  
.5  
Sign Flag  
0
1
Operation generates positive number (MSB = "0")  
Operation generates negative number (MSB = "1")  
R = Read-only  
W = Write-only  
R/W = Read/write  
' - ' = Not used  
Description of the  
effect of specific  
bit settings  
RESET value notation:  
'-' = Not used  
'x' = Undetermind value  
'0' = Logic zero  
'1' = Logic one  
Addressing mode or  
modes you can use to  
modify register values  
Bit number:  
MSB = Bit 7  
LSB = Bit 0  
Figure 4-1. Register Description Format  
4-4  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
ADCON— A/D Converter Control Register  
Page 0, D8H  
Bit Identifier  
.7  
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
Not used for the S3C9664/P9664  
.6–.4  
Analog Input Pin Selection Bits  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC0 (P1.0)  
ADC1 (P1.1)  
ADC2 (P1.2)  
ADC3 (P1.3)  
ADC4 (P1.4)  
ADC5 (P1.5)  
Not used for the S3C9664/P9664  
Not used for the S3C9664/P9664  
.3  
End-of-Conversion Status Bit  
0
1
A/D conversion not complete (when read)  
A/D conversion is complete (when read)  
.2–.1  
Conversion Speed Selection Bits  
fOSC/16  
fOSC/8  
fOSC/4  
fOSC  
0
0
1
1
0
1
0
1
.0  
Conversion Start Bit  
0
1
Automatically reset after conversion starting  
Starting  
NOTE: To configure an A/D converter input channel, you must also make the proper setting in the port 1 control  
register, P1CONL (ADC0–ADC3) or P1CONH (ADC4–ADC5). Only one input can be configured at one time.  
4-5  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
BTCON— Basic Timer Control Register  
Page 0, DCH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 – .4  
.3 – .2  
Watchdog Timer Enable Bits  
1
0
1
0
Disable watchdog function  
Enable watchdog function  
Any other value  
Basic Timer Input Clock Selection Bits  
fOSC/4096  
0
0
1
1
0
1
0
1
fOSC/1024  
fOSC/128  
Non divided (fOSC  
)
(note)  
(note)  
.1  
.0  
Basic Timer Counter Clear Bit  
0
1
No effect  
Clear BTCNT  
Basic Timer Divider Clear Bit  
0
1
No effect  
Clear both dividers  
NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit  
is then cleared automatically to "0".  
4-6  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
CLKCON— System Clock Control Register  
Page 0, D4H  
Bit Identifier  
.7  
0
.6  
.5  
.4  
0
.3  
0
.2  
.1  
.0  
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
.7  
Oscillator IRQ Wake-up Function Bit  
0
1
Enable IRQ for main system oscillator wake-up in power down mode  
Disable IRQ for main system oscillator wake-up in power down mode  
.6 and .5  
.4 and .3  
Not used for S3C9664  
CPU Clock (System Clock) Selection Bits  
Divide by 16 (fOSC/16)  
Divide by 8 (fOSC/8)  
Divide by 2 (fOSC/2)  
Non-divided clock (fOSC  
0
0
1
1
0
1
0
1
)
.2 – .0  
Not used for S3C9664  
4-7  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
EP0BCNT— Endpoint 0 Write Counter register  
Page 0, F3H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R
R
R
R
R/W  
R
R
R
.7  
Data Toggle check bit  
0
1
Data 0 transaction toggle  
Data 1 transaction toggle  
.6  
.5  
Reserved  
Over 8 bytes Received bit  
0
1
Normal Operation  
Indicates over 8 bytes received  
.4  
Enable Bit  
0
1
Disable endpoint 0  
Enable endpoint 0  
.3 – .0  
The Byte Counter of Data stored in endpoint 0  
0
1
0
0
0
0
0
0
Minimum bytes stored in endpoint 0  
Maximum bytes stored in endpoint 0  
4-8  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
EP1BCNT— Endpoint 1 Write Counter register  
Page 0, FCH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R
R
R
R
R/W  
R
R
R
.7  
Data Toggle check bit  
0
1
Data 0 transaction toggle  
Data 1 transaction toggle  
.6  
.5  
Reserved  
Over 8 bytes Received bit  
0
1
Normal Operation  
Indicates over 8 bytes received  
.4  
Enable Bit  
0
1
Disable endpoint 1  
Enable endpoint 1  
.3 – .0  
The Byte Counter of Data stored in endpoint 1  
0
1
0
0
0
0
0
0
Minimum bytes can be stored in endpoint 1  
Maximum bytes can be stored in endpoint 1  
4-9  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
EP2BCNT— Endpoint 2 Write Counter register  
Page 0, FDH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R
R
R
R
R/W  
R
R
R
.7  
Data Toggle check bit  
0
1
Data 0 transaction toggle  
Data 1 transaction toggle  
.6  
.5  
Reserved  
Over 8 bytes Received bit  
0
1
Normal Operation  
Indicates over 8 bytes received  
.4  
Enable Bit  
0
1
Disable endpoint 2  
Enable endpoint 2  
.3 – .0  
The Byte Counter of Data stored in endpoint 2  
0
1
0
0
0
0
0
0
Minimum bytes can be stored in endpoint 2  
Maximum bytes can be stored in endpoint 2  
4-10  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
EP0CSR — Control Endpoint Status Register  
Page 0, F1H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
.5  
.4  
.3  
SETUP_END Clear Bit  
0
1
No effect (when write)  
Clear SETUP_END (bit4) bit  
OUT_PKT_RDY Clear Bit  
0
1
No effect (when write)  
Clear OUT_PKT_RDY (bit0) bit  
STALL Signal Sending Bit  
0
1
No effect (when write)  
Send STALL signal to host  
Setup Transfer End Bit  
0
1
No effect (when write)  
SIE sets this bit when a control transfer ends before DATA_END (bit3) is set  
Setup Data End Bit  
0
1
No effect (when write)  
MCU set this bit after loading or unloading the last packet data into the FIFO  
.2  
.1  
.0  
STALL Signal Receive Bit  
0
1
MCU clear this bit to end the STALL condition  
SIE sets this bit if a control transaction is ended due to a protocol violation  
In Packet Ready Bit  
0
1
SIE clear this bit once the packet has been successfully sent to the host  
MCU sets this bit after writing a packet of data into Endpoint0 FIFO  
Out Packet Ready Bit  
0
1
No effect (when write)  
SIE sets this bit once a valid token is written to the FIFO  
4-11  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
EP1CSR — Interrupt Endpoint Status Register  
Page 0, F2H  
Bit Identifier  
.7  
0
.6  
1
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
a) The belows are configured as IN mode.  
.7  
DATA_TOGGLE Clear Bit  
0
1
No effect (when write)  
Clears the data toggle sequence bit  
.6 – .3  
Maximum Packet Size Bits  
0
1
No effect (when write)  
Indicates the maximum packet size for interrupt endpoint  
.2  
FIFO Flush Bit  
0
1
No effect (when write)  
FIFO is flushed, and IN_PKT_RDY cleared  
.1  
Force STALL Bit  
0
1
MCU clears this bit to end the STALL condition  
Issues a STALL handshake to USB  
.0  
In Packet Ready Bit  
0
1
SIE clear this bit once the packet has been successfully sent to the host  
MCU sets this bit after writing a packet of data into Endpoint 1 FIFO  
4-12  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
EP1CSR — Interrupt Endpoint Status Register  
Page 0, F2H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
b) The belows are configured as OUT mode.  
.7  
Reserved  
.6  
OUT_PKT_RDY Clear Bit  
0
1
No effect (when write)  
Clear OUT_PKT_RDY (bit0) bit  
.5-.4  
.3  
Reserved  
STALL Signal Receive Bit  
0
1
MCU can clear this bit  
SIE sets this bit after sending stall packet  
.2  
.1  
FIFO Flush Bit  
0
1
No effect (when write)  
FIFO is flushed, and IN_PKT_RDY cleared  
Force STALL Bit  
0
1
MCU clears this bit to end the STALL condition  
Issues a STALL handshake to USB  
.0  
Out Packet Ready Bit  
0
1
No effect (when write)  
SIE sets this bit once a valid data is written to the FIFO  
4-13  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
EP2CSR — Interrupt Endpoint Status Register  
Page 0, F9H  
Bit Identifier  
.7  
0
.6  
1
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
a) The belows are configured as IN mode.  
.7  
DATA_TOGGLE Clear Bit  
0
1
No effect (when write)  
Clears the data toggle sequence bit  
.6 – .3  
Maximum Packet Size Bits  
0
1
No effect (when write)  
Indicates the maximum packet size for interrupt endpoint  
.2  
FIFO Flush Bit  
0
1
No effect (when write)  
FIFO is flushed, and IN_PKT_RDY cleared  
.1  
Force STALL Bit  
0
1
MCU clears this bit to end the STALL condition  
Issues a STALL handshake to USB  
.0  
In Packet Ready Bit  
0
1
SIE clear this bit once the packet has been successfully sent to the host  
MCU sets this bit after writing a packet of data into Endpoint 2 FIFO  
4-14  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
EP2CSR — Interrupt Endpoint Status Register  
Page 0, F9H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
b) The belows are configured as OUT mode.  
.7  
Reserved  
.6  
OUT_PKT_RDY Clear Bit  
0
1
No effect (when write)  
Clear OUT_PKT_RDY (bit0) bit  
.5-.4  
.3  
Reserved  
STALL Signal Receive Bit  
0
1
MCU can clear this bit  
SIE sets this bit after sending stall packet  
.2  
.1  
FIFO Flush Bit  
0
1
No effect (when write)  
FIFO is flushed, and IN_PKT_RDY cleared  
Force STALL Bit  
0
1
MCU clears this bit to end the STALL condition  
Issues a STALL handshake to USB  
.0  
Out Packet Ready Bit  
0
1
No effect (when write)  
SIE sets this bit once a valid data is written to the FIFO  
4-15  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
EPMODE— Endpoint Mode register  
Page 0, E7H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
Reset Length  
0
0
1
1
0
1
0
1
22.4 ms + a  
12.0 ms + a  
6.0 ms + a  
4.0 ms + a  
NOTE: a @ ± 0.66 ms  
.5 - .2  
.1  
Reserved  
Endpoint 2 Mode  
0
1
Endpoint 2 acts as an IN interrupt endpoint  
Endpoint 2 acts as an OUT interrupt endpoint  
.0  
Endpoint 1 Mode  
0
1
Endpoint 1acts as an IN interrupt endpoint  
Endpoint 1 acts as an OUT interrupt endpoint  
4-16  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
FLAGS— System Flags Register  
Page 0, D5H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
.2  
.1  
.0  
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
Carry Flag (C)  
Operation does not generate a carry or borrow condition  
0
Zero Flag (Z)  
0
1
Operation result is a non-zero value  
Operation result is zero  
.5  
Sign Flag (S)  
0
1
Operation generates a positive number (MSB = "0")  
Operation generates a negative number (MSB = "1")  
.4  
Overflow Flag (V)  
0
1
Operation result is £ +127 or ³ –128  
Operation result is ³ +127 or £ –128  
.3 – .0  
Not used for S3C9664  
4-17  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
P0CONH — Port 0 Control High Byte Register  
Page 0, E7H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
.5 and .4  
.3 and .2  
.1 and .0  
Port 0, P0.7/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
Port 0, P0.6/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
Port 0, P0.5/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
Port 0, P0.4/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
4-18  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
P0CONL Port 0 Control Low Byte Register  
Page 0, E6H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
.5 and .4  
.3 and .2  
.1 and .0  
Port 0, P0.3/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
Port 0, P0.2/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
Port 0, P0.1/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Push-pull output  
Port 0, P0.0/INT0 Configuration Bits  
0
0
1
1
0
1
0
1
Schmitt trigger input; interrupt on falling edges (or capture input)  
Schmitt trigger input; interrupt on rising edges  
N-CH open drain output  
Alternative Function (T0 out : match or PWM)  
4-19  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
P0INT — Port 0 Interrupt Enable Register  
Page 0, EAH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
P0.7/INT0 Interrupt Enable Bit  
0
1
Disable P0.7 interrupt  
Enable P0.7 interrupt  
P0.6/INT0 Interrupt Enable Bit  
0
1
Disable P0.6 interrupt  
Enable P0.6 interrupt  
P0.5/INT0 Interrupt Enable Bit  
0
1
Disable P0.5 interrupt  
Enable P0.5 interrupt  
P0.4/INT0 Interrupt Enable Bit  
0
1
Disable P0.4 interrupt  
Enable P0.4 interrupt  
P0.3/INT0 Interrupt Enable Bit  
0
1
Disable P0.3 interrupt  
Enable P0.3 interrupt  
P0.2/INT0 Interrupt Enable Bit  
0
1
Disable P0.2 interrupt  
Enable P0.2 interrupt  
P0.1/INT0 Interrupt Enable Bit  
0
1
Disable P0.1 interrupt  
Enable P0.1 interrupt  
P0.0/INT0 Interrupt Enable Bit  
0
1
Disable P0.0 interrupt  
Enable P0.0 interrupt  
4-20  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
P0PND — Port 0 interrupt Pending Register  
Page 0, EBH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write (note)  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
P0.7/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.6/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.5/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.4/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.3/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.2/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.1/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P0.0/INT0 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
NOTE: To clear a port 0 interrupt pending condition, write a "0" to the corresponding P0PND register bit location.  
4-21  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
P0PURH — Port0 Pull-up/down Enable Register (High Byte)  
Page 0, E5H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
.0  
0
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
.5 and .4  
.3 and .2  
.1 and .0  
Port 0.7 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
Port 0.6 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
Port 0.5 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
Port 0.4 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
NOTE: Pull –up/down resister is to be automatically disabled on Push-Pull Output mode and Open-Drain output mode.  
Otherwise, which can be enabled in all input modes  
4-22  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
P0PURL — Port 0 Pull-up/down Enable Register (Low byte)  
Page 0, E4H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
.5 and .4  
.3 and .2  
.1 and .0  
Port 0.3 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
Port 0.2 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
Port 0.1 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
Port 0.0 Pull-up/down bits  
0
0
1
1
0
1
0
1
Enable Pull-up  
Enable Pull-down  
Disable Pull-up/down  
Disable Pull-up/down  
NOTE: Pull –up/down resister is to be automatically disabled on Push-Pull Output mode and Open drain Output mode .  
Otherwise, which can be enabled in all input modes.  
4-23  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
P1CONH— Port 1 Control High Byte Register  
Page 0, E9H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
.5 and .4  
.3 and .2  
Port 1, P1.7/INT1 Configuration Bits  
0
0
1
1
0
1
0
1
input, falling edge external interrupt with pull-up resistor  
Input, rising edge external interrupt  
N-CH open drain out  
Push-pull output  
Port 1, P1.6/INT1 Configuration Bits  
0
0
1
1
0
1
0
1
input, falling edge external interrupt with pull-up resistor  
Input ,rising edge external interrupt  
N-CH open drain out  
Push-pull output  
Port 1, P1.5/AD5 /INT1 Configuration Bits  
0
0
input, falling edge external interrupt pull-up resistor enabled; A/D  
converter off  
0
1
1
1
0
1
input; A/D converter off, rising edge external interrupt  
A/D converter input (AD5); input off  
Push-pull output  
.1 and .0  
Port 1, P1.4/AD4/INT1 Configuration Bits  
0
0
input, falling edge external interrupt pull-up resistor enabled; A/D  
converter off  
0
1
1
1
0
1
input; A/D converter off, rising edge external interrupt  
A/D converter input (AD4); input off  
Push-pull output  
4-24  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
P1CONL— Port 1 Control Low Byte Register  
Page 0, E8H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
.5 and .4  
.3 and .2  
.1 and .0  
Port 1, P1.3/AD3/INT1 Configuration Bits  
0
0
Input, falling edge external interrupt pull-up resistor enabled; A/D  
converter off  
0
1
1
1
0
1
Input; A/D converter off, rising edge external interrupt  
A/D converter input (AD3); input off  
Push-pull output  
Port 1, P1.2/AD2 /INT1 Configuration Bits  
0
0
Input, falling edge external interrupt pull-up resistor enabled; A/D  
converter off  
0
1
1
1
0
1
Input; A/D converter off, rising edge external interrupt  
A/D converter input (AD2); input off  
Push-pull output  
Port 1, P1.1/AD1/INT1 Configuration Bits  
0
0
Input, falling edge external interrupt pull-up resistor enabled; A/D  
converter off  
0
1
1
1
0
1
Input; A/D converter off ,rising edge external interrupt  
A/D converter input (AD1); input off  
Push-pull output  
Port 1, P1.0/AD0/INT1 Configuration Bits  
0
0
input, falling edge external interrupt pull-up resistor enabled; A/D  
converter off  
0
1
1
1
0
1
input; A/D converter off, rising edge external interrupt  
A/D converter input (AD0); input off  
Push-pull output  
4-25  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
P1INT — Port 1 Interrupt Enable Register  
Page 0, ECH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
P1.7/INT1 Interrupt Enable Bit  
0
1
Disable P1.7 interrupt  
Enable P1.7 interrupt  
P1.6/INT1 Interrupt Enable Bit  
0
1
Disable P1.6 interrupt  
Enable P1.6 interrupt  
P1.5/INT1 Interrupt Enable Bit  
0
1
Disable P1.5 interrupt  
Enable P1.5 interrupt  
P1.4/INT1 Interrupt Enable Bit  
0
1
Disable P1.4 interrupt  
Enable P1.4 interrupt  
P1.3/INT1 Interrupt Enable Bit  
0
1
Disable P1.3 interrupt  
Enable P1.3 interrupt  
P1.2/INT1 Interrupt Enable Bit  
0
1
Disable P1.2 interrupt  
Enable P1.2 interrupt  
P1.1/INT1 Interrupt Enable Bit  
0
1
Disable P1.1 interrupt  
Enable P1.1 interrupt  
P1.0/INT1 Interrupt Enable Bit  
0
1
Disable P1.0 interrupt  
Enable P1.0 interrupt  
4-26  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
P1PND — Port 1Interrupt Pending Register  
Page 0, EDH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write (note)  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
P1.7/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.6/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.5/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.4/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.3/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.2/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.1/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
P1.0/INT1 Interrupt Pending Bit  
0
1
No interrupt pending (when bit is read)  
Interrupt is pending (when bit is read)  
NOTE: To clear a port 1 interrupt pending condition, write a "0" to the corresponding P1PND register bit location.  
4-27  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
P2CONINT— Port 2 Control/Interrupt Register  
Page 0, EFH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
Port 2, P2.1/INT2Configuration Bits  
0
0
1
1
0
1
0
1
Input, rising edge external interrupt  
Input, falling edge external interrupt with pull-up resister  
N-CH open drain out  
Push-pull output  
.5 and .4  
Port 2, P2.0/INT2 Configuration Bits  
0
0
1
1
0
1
0
1
Input, rising edge external interrupt  
Input, falling edge external interrupt with pull-up resister  
N-CH open drain out  
Push-pull output  
.3 and .2  
.1 and .0  
P2.0-P2.1 Interrupt enable Bits  
0
1
External interrupt disable  
External interrupt enable  
P2.0-P2.1 Interrupt Pending Bits  
0
1
No pending (when read)/clear pending bit  
Pending (when read)/No effect (When write)  
4-28  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
PWRMGR — USB Power Management Register  
Page 0, F8H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 – .5  
.4  
Reserved  
VPIN Value Bit  
0
1
Indicates the value of VPIN is low  
Indicates the value of VPIN is high  
.3  
.2  
.1  
VMIN Value Bit  
0
1
Indicates the value of VMIN is low  
Indicates the value of VMIN is high  
Clear Suspend Counter  
0
1
No effect  
Clear suspend counter  
RESUME Signal Sending Bit  
0
1
RESUME signal is ended  
While in suspend state, if the MCU wants to initiate a resume, it writes a 1 to  
this register for 10 ms (maximum of 15 ms), and clears this register. In  
suspend mode, if this bit is set to "1", USB generates resume signaling.  
.0  
SUSPEND Status Bit  
0
Cleared automatically when MCU writes a zero to RESUME signal sending bit  
or when function receives resume signal from the host while in suspend mode  
1
This bit is set when SUSPEND interrupt occur  
4-29  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
SUBCON — SUB_Oscillator Control  
Page 0, EFH  
Bit Identifier  
.7  
0
.6  
0
.5  
.4  
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7  
.6  
.5  
Sub_Oscillator Interrupt Enable Bit  
0
1
Sub_oscillator interrupt disable  
Sub_oscillator interrupt enable  
Sub_Oscillator Interrupt Pending Bit  
0
1
No pending (when read)/clear pending (when write)  
Pending (when read)/no effect (when write)  
Sub_Oscillator Counter clear Bit  
0
1
No effect/ after counter cleared ,automatically this bit is then cleared to “0”  
Clear Sub_Oscillator counter clear  
Sub_Oscillator Enable Bit  
.4  
0
1
Sub_oscillator disable  
Sub_oscillator enable  
Sub_Oscillator Counter Input Clock Selection Bits  
f
OSC
/2048  
.3 and .1  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
f
OSC
/3072  
f
OSC
/4096  
f
OSC
/6144  
f
OSC
/8192  
f
OSC
/12288  
f
OSC
/16384  
fOSC/24576  
.0  
Not used for S3C9664  
= 158.86 kHz (± 10 %)  
NOTE: f  
OSC  
4-30  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
SYM— System Mode Register  
Page 0, DFH  
Bit Identifier  
.6  
.5  
.4  
.3  
0
.2  
0
.1  
0
.0  
0
.7  
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
.7 – .4  
.3  
Not used for S3C9664  
Global Interrupt Enable Bit  
0
1
Global interrupt processing disable  
Global interrupt processing enable  
.2 and .0  
Page Select Bit  
0
0
0
0
0
0
1
0
0
1
0
1
Page 0  
Page 1  
Page 2 (Not allowed in S3C9664)  
Page 3 (Not allowed in S3C9664)  
4-31  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
T0CON— Timer 0 Control Register  
Page 0, D2H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
.1  
.0  
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
.7 and .6  
T0 Counter Input Clock Selection Bits  
fOSC/4096  
fOSC/256  
fOSC/8  
0
0
1
1
0
1
0
1
fOSC/1  
.5 and .4  
T0 Operating Mode Selection Bits  
0
0
1
1
0
1
0
1
Interval timer mode  
Capture mode (capture on falling edge, counter running, OVF)  
Capture mode (capture on rising edge, counter running, OVF)  
PWM mode (OVF interrupt can occur)  
.3  
T0 Counter Clear Bit  
0
1
No effect  
Clear the timer 0 counter (when write)  
.2 and .0  
Not used for S3C9664  
4-32  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
T0INT— Timer 0 Interrupt Control Register  
Page 0, D3H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R
R
R
R
R/W  
R/W  
R/W  
R/W  
.7 and .4  
.3  
Not used for S3C9664  
T0 Overflow interrupt  
0
1
Disable T0OVF interrupt  
Enable TOOVF interrupt  
.2  
.1  
T0 match/capture interrupt Enable Bit  
0
1
Disable T0INT interrupt  
Enable T0INT interrupt  
T0 Overflow Interrupt Pending Bit  
0
0
1
No interrupt pending  
Clear this pending bit (write)  
Interrupt is pending  
.0  
T0 Interrupt Pending Bit (Capture or Match Interrupt)  
0
0
1
No interrupt pending  
Clear this pending bit (write)  
Interrupt is pending  
4-33  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
T1CON— Timer 1 Control Register  
Page 0, E3H  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R
R
R/W  
R/W  
R/W  
R/W  
.7 and .6  
T1 Input Clock Selection Bits  
fOSC/10246  
fOSC/256  
fOSC/64  
0
0
1
1
0
1
0
1
fOSC/8  
.5 and .4  
.3  
Not used for S3C9664  
T1 Counter Clear Bit  
0
1
No effect  
Clear the timer 0 counter (when write)  
.2  
.1  
.0  
T1 Counter Enable Bit  
0
1
Disable counting operation  
Enable counting operation  
T1 Interrupt Enable Bit  
0
1
Disable interrupt  
Enable interrupt  
T1 Interrupt Pending Bit  
0
0
1
No interrupt pending  
Clear this pending bit (write)  
Interrupt is pending  
4-34  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
USBCON — USB Control Register  
Page 0, FEH  
Bit Identifier  
.7  
0
.6  
0
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
.7- .6  
.5  
Reserved  
DP/DM Control Bit  
0
1
DP/DM can not be individually controlled by MCU  
DP/DM can be individually controlled by MCU to set USBCON.4 and  
USBCON.3  
.4  
.3  
DP Status Bit  
0
1
DP is Low  
DP is High  
DM Status Bit  
0
1
DM is Low  
DM is High  
.2  
.1  
.0  
USB Reset MCU Bit  
0
1
USB which is been on reset can not make MCU reset  
USB which is been on reset can be able to reset MCU  
MCU reset USB Bit  
0
1
No effect  
MCU forces USB be reset  
USB Reset Signal Receive Bit  
0
1
Clear reset signal Bit  
This bit is set when host send USB rest signal  
4-35  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
USBINT — USB Interrupt Enable Register  
Page 0, F7H  
Bit Identifier  
.7  
.6  
.5  
.4  
0
.3  
1
.2  
0
.1  
1
.0  
1
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
R/W  
.7–.5  
.4  
Not used for S3C9664  
USB Reset Interrupt Enable Bit  
0
1
Disable USB reset interrupt  
Enable USB reset interrupt  
.3  
.2  
.1  
.0  
Endpoint 2 Interrupt Enable Bit  
0
1
Disable Endpoint 2 interrupt  
Enable Endpoint 2 interrupt (default)  
SUSPEND/RESUME Interrupt Enable Bit  
0
1
Disable SUSPEND and RESUME interrupt (default)  
Enable SUSPEND and RESUME interrupt  
ENDPOINT1 Interrupt Enable Bit  
0
1
Disable ENDPOINT 1 interrupt  
Enable ENDPOINT 1 interrupt (default)  
ENDPOINT0 Interrupt Enable Bit  
0
1
Disable ENDPOINT 0 interrupt  
Enable ENDPOINT 0 interrupt (default)  
4-36  
S3C9664/P9664 (Preliminary Spec)  
CONTROL REGISTERS  
USBPND — USB Interrupt Pending Register  
Page 0, F6H  
Bit Identifier  
.7  
.6  
.5  
.4  
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
R/W  
R/W  
R/W  
R/W  
.7–.6  
.5  
Not used for S3C9664  
USB Reset Interrupt Pending Bit  
0
1
No effect (once read, this bit is cleared automatically)  
This bit is set, when USB reset need to served  
.4  
.3  
.2  
.1  
.0  
Endpoint Interrupt Pending Bit  
0
1
No effect (once read, this bit is cleared automatically)  
This bit is set, when endpoint 2 need to served  
RESUME Interrupt Pending Bit  
0
1
No effect (once read, this bit is cleared automatically)  
This bit is set, if RESUME signaling is received while in SUSPEND mode  
SUSPEND Interrupt Pending Bit  
0
1
No effect (once read, this bit is cleared automatically)  
This bit is set, when suspend signaling is received  
ENDPOINT1 Interrupt Pending Bit  
0
1
No effect (once read, this bit is cleared automatically)  
This bit is set, when endpoint1 needs to be serviced  
ENDPOINT0 Interrupt Pending Bit  
0
1
No effect (once read, this bit is cleared automatically)  
This bit is set, while endpoint 0 needs to serviced. It is set under the following  
conditions:  
OUT_PKT_RDY is set  
IN_PKT_RDY get cleared  
SENT_STALL gets set  
DATA_END gets cleared  
SETUP_END gets set  
4-37  
CONTROL REGISTERS  
S3C9664/P9664 (Preliminary Spec)  
XCON— USB Signal Control Register  
Page 1, FEH  
Bit Identifier  
.7  
.6  
.5  
0
.4  
0
.3  
0
.2  
0
.1  
0
.0  
0
RESET Value  
Read/Write  
W
W
W
W
W
W
.7  
Pull-Up resister at (D- ) enable bit  
0
1
Pull-Up resister at (D-) disable  
Pull-Up resister at (D+) enable  
.6  
GPIO or USB Port Select bit  
0
1
General in/out port enable  
USB port enable  
.6 – .5  
This register will be used to control the USB signal quality.  
The USB signal (D+/D-) of transceiver can be changed by setting this register.  
DM  
4
DP  
1
Bit  
X
X
X
5
3
2
0
X
Edge Control  
Bit 5, 2  
0
Bit 4, 1  
Bit 3, 0  
DLY Value  
Unit  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DLY 0  
DLY 1  
DLY 2  
DLY 4  
DLY 0  
DLY 1  
DLY 2  
DLY 4  
Rise edge  
Fall edge  
About 2.5 nsec  
1
NOTE:  
DLY means delay time of rising/fallling  
time.  
Result, DM DP DM DP  
x - point 1 x - point  
(VDD = 5.12 V)  
NUM  
HEX Value  
2
1
2
3
4
5
0x00  
0x38  
0x3C  
0x3D  
0x3E  
Default value, 0.88 V, 1.19 V  
1.58 V, 1.55 V  
1.50 V, 1.50 V  
1.65 V, 1.65 V  
1.80 V, 1.80 V  
Good  
NOTE:  
This value is only for OTP products. XCON is a write-only register and  
can be accessed through page 1.  
4-38  
S3C9664/P9664 (Preliminary Spec)  
INTERRUPT STRUCTURE  
5
INTERRUPT STRUCTURE  
OVERVIEW  
The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt  
sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H.  
VECTOR  
SOURCES  
S1  
S2  
S3  
Sn  
0000H  
0001H  
NOTES:  
1. The SAM88RCRI interrupt has only one vector address (0000H-0001H).  
2. The number of Sn value is expandable.  
Figure 5-1. S3C9-Series Interrupt Type  
INTERRUPT PROCESSING CONTROL POINTS  
Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The system-  
level control points in the interrupt structure are therefore:  
— Global interrupt enable and disable (by EI and DI instructions)  
— Interrupt source enable and disable settings in the corresponding peripheral control register(s)  
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)  
The system mode register, SYM (DFH), is used to enable and disable interrupt processing.  
SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An  
Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order  
to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts  
during normal operation, we recommend that you use the EI and DI instructions for this purpose.  
5-1  
INTERRUPT STRUCTURE  
S3C9664/P9664 (Preliminary Spec)  
INTERRUPT PENDING FUNCTION TYPES  
When the interrupt service routine has executed, the application program's service routine must clear the  
appropriate pending bit before the return from interrupt subroutine (IRET) occurs.  
INTERRUPT PRIORITY  
Because there is not a interrupt priority register in SAM87RI, the order of service is determined by a sequence of  
source which is executed in interrupt service routine.  
"EI" Instruction  
S
R
Q
Interrupt Pending  
Register  
Execution  
RESET  
Source  
Interrupts  
Vector  
Interrupt  
Cycle  
Interrpt priority  
is determind by  
software polling  
method  
Source  
Interrupt  
Enable  
Global Interrupt  
Control (EI, Di instruction)  
Figure 5-2. Interrupt Function Diagram  
5-2  
S3C9664/P9664 (Preliminary Spec)  
INTERRUPT STRUCTURE  
INTERRUPT SOURCE SERVICE SEQUENCE  
The interrupt request polling and servicing sequence is as follows:  
1. A source generates an interrupt request by setting the interrupt request pending bit to "1".  
2. The CPU generates an interrupt acknowledge signal.  
3. The service routine starts and the source's pending flag is cleared to "0" by software.  
4. Interrupt priority must be determined by software polling method.  
INTERRUPT SERVICE ROUTINES  
Before an interrupt request can be serviced, the following conditions must be met:  
— Interrupt processing must be enabled (EI, SYM.3 = "1")  
— Interrupt must be enabled at the interrupt's source (peripheral control register)  
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.  
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:  
1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0")  
to disable all subsequent interrupts.  
2. Save the program counter and status flags to stack.  
3. Branch to the interrupt vector to fetch the service routine's address.  
4. Pass control to the interrupt service routine.  
When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores  
the PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request.  
GENERATING INTERRUPT VECTOR ADDRESSES  
The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt  
processing follows this sequence:  
1. Push the program counter's low-byte value to stack.  
2. Push the program counter's high-byte value to stack.  
3. Push the FLAGS register values to stack.  
4. Fetch the service routine's high-byte address from the vector address 0000H.  
5. Fetch the service routine's low-byte address from the vector address 0001H.  
6. Branch to the service routine specified by the 16-bit vector address.  
5-3  
INTERRUPT STRUCTURE  
S3C9664/P9664 (Preliminary Spec)  
S3C9664 INTERRUPT STRUCTURE  
The S3C9664 microcontroller has thirteen peripheral interrupt sources:  
— Timer 0 match interrupt  
— Timer 0 overflow interrupt  
— Timer 1 match interrupt  
— Suspend interrupt  
— Resume interrupt  
— Internal RC interrupt  
— USB reset interrupt  
— Three Endpoint interrupts for Endpoint 0, Endpoint 1 and Endpoint 2  
— Eight external interrupts for port 0, P0.0–P0.7  
— Eight external interrupts for port 1, P1.1–P1.7  
— Two external interrupts for port 2, P2.0–P2.1  
5-4  
S3C9664/P9664 (Preliminary Spec)  
INTERRUPT STRUCTURE  
Match/Capture Interrupt  
T0INT.1  
T0INT.0  
T0INT.3  
Overflow Interrupt  
Internal RC Interrupt  
P0.0-P0.7 Interrupt  
P1.0-P1.7 Interrupt  
Endpoint 0 interrupt  
Endpoint 1 interrupt  
Endpoint 2 interrupt  
USB_RST interrupt  
T0INT.2  
SUBCON.6  
P0PND.0-7  
P1PND.0-7  
EP0_PND  
EP1_PND  
EP2_PND  
USB_RST  
SUBCON.7  
P0INT.X  
Vector  
0000H  
SYM.3  
(EI, DI)  
P1INT.X  
Enable_EP0  
Enable_EP1  
Enable_EP2  
Enable_USB_RST  
Suspend Interrupt  
Suspend_  
PND  
Resume Interrupt  
Suspend/Resume  
Interrupt Enable  
Resume_  
PND  
Timer 1 Match Interrupt  
T1CON.0  
T1CON.1  
P2.0-P2.1 Interrupt  
P2CONINT  
.2-.3  
P2CONINT.0-.1  
Figure 5-3. S3C9664 Interrupt Structure  
5-5  
S3C9664/P9664 (Preliminary Spec)  
CLOCK CIRCUIT  
7
CLOCK CIRCUIT  
OVERVIEW  
The S3C9664 has two oscillation circuit options, a crystal/ceramic oscillation and an external clock source. The  
crystal or ceramic oscillation source provides a maximum 6 MHz clock. The XIN and XOUT pins connect the  
oscillation source to the on-chip clock circuit. External clock and crystal/ceramic oscillator circuits are shown in  
Figures 7-1 and 7-2.  
XIN  
XIN  
S3C9664  
S3C9664  
XOUT  
XOUT  
Figure 7-2. Main Oscillator Circuit  
(Crystal/Ceramic Oscillator)  
Figure 7-1. External Oscillator  
MAIN OSCILLATOR LOGIC  
To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator  
circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the  
CPU to efficiently process logic operations.  
CLOCK STATUS DURING POWER-DOWN MODES  
The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:  
— In Stop mode, the main oscillator "freezes," halting the CPU and peripherals. The contents of the register file  
and current system register values are retained. RESET operation releases the Stop mode, and starts the  
oscillator.  
— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The  
current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file  
is retained. Idle mode is released by a RESET or by an interrupt (external or internally-generated).  
7-1  
CLOCK CIRCUIT  
S3C9664/P9664 (Preliminary Spec)  
SYSTEM CLOCK CONTROL REGISTER (CLKCON)  
The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the  
following functions:  
— Oscillator IRQ wake-up function enable/disable (CLKCON.7)  
— Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3)  
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release  
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.  
After a RESET, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and  
the f  
/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the  
OSC  
CPU clock speed to fOSC, fOSC/2 or fOSC/8.  
System Clock Control Register (CLKCON)  
D4H, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Oscillator IRQ wake-up enable bit:  
0 = Enable IRQ for main system  
oscillator wake-up function  
1 = Disable IRQ for main system  
oscillator wake-up function  
No effect  
Divide-by selection bits for  
CPU clock frequency:  
00 = fosc/16  
01 = fosc/8  
10 = fosc/2  
11 = fosc(non-divided)  
No effect  
Figure 7-3. System Clock Control Register (CLKCON)  
7-2  
S3C9664/P9664 (Preliminary Spec)  
CLOCK CIRCUIT  
Stop  
Instruction  
CLKCON.4-.3  
Oscillator  
Stop  
1/2  
1/8  
M
U
X
Main  
OSC  
CUP Clock  
Oscillator  
Wake-up  
1/16  
Noise  
Filter  
CLKCON.7  
INT Pin  
Figure 7-4. System Clock Circuit Diagram  
7-3  
S3C9664/P9664 (Preliminary Spec)  
RESET and POWER-DOWN  
8
RESET and POWER-DOWN  
SYSTEM RESET  
OVERVIEW  
Reference  
Voltage  
Start Up  
Generator  
Glitch Filter  
RESET  
Comparator  
Voltage  
Divider  
NOTES:  
1. Start Up Circuit: Start up reference voltage generator circuit when device powered.  
2. Reference Voltage Generator: Supply voltage independent reference voltage generator.  
(Supply voltage must great then 2.5 V)  
3. Voltage Divider: Divide supply voltage by "N" (N: integer, 2).  
4. Comparator: Compare reference voltage and divided voltage.  
5. Glitch Filter: Remove glitch and noise signal.  
Figure 8-1. LVD Characteristcs  
8-1  
RESET and POWER-DOWN  
S3C9664/P9664 (Preliminary Spec)  
Vc (Compare Voltage)  
Divide Voltage  
NOTES:  
1. LVD Operation Voltage Range: 2.3 V-6.0 V  
2. LVD Detection Voltage Range: 3.4 V  
3. LVD Current Consumption:  
± 0.4 V  
Reference Voltage  
Less then 10 uA (normally 5 uA)  
4. LVD Powered Reset Release Time:  
more then 500 usec (LVD only, typical)  
5. LVD Simulation Conditions (Hspice Simulation)  
Temp: -40 - 80 C  
Process Veriation: Worst to best conditions  
Test Voltage: 0.0 V-7.0 V  
Powered Slew Rate: 5 V/1 usec- 5 V/10 msec  
VDD (Supply Voltage)  
Normal Operation  
Reset Operation  
by LVD  
Figure 8-2. LVD Architecture  
The following sequence of events occur during a reset operation:  
— All interrupts are disabled.  
— The watchdog function (basic timer) is enabled.  
— Ports 0 and 1 are set to Schmitt trigger input mode and all pull-up resistors are disabled.  
— Peripheral control and data registers are disabled and reset to their initial values.  
— The program counter is loaded with the ROM reset address, 0100H.  
— When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location  
0100H (and 0101H) is fetched and executed.  
NOTE  
To program the duration of the oscillation stabilization interval, you must make the appropriate settings to  
the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the  
basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs),  
you can disable it by writing '1010B' to the upper nibble of BTCON.  
8-2  
S3C9664/P9664 (Preliminary Spec)  
RESET and POWER-DOWN  
POWER-DOWN MODES  
STOP MODE  
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all  
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than  
120 µA. All system functions are halted when the clock "freezes," but data stored in the internal register file is  
retained. Stop mode can be released in one of two ways: by a RESET signal or by an external interrupt.  
Using RESET to Release Stop Mode  
Stop mode is released when the RESET signal is released and returns to High level. All system and peripheral  
control registers are then reset to their default values and the contents of all data registers are retained. RESET  
operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'.  
After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by  
fetching the 16-bit address stored in ROM locations 0100H and 0101H.  
Using an External Interrupt to Release Stop Mode  
Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related  
external interrupts cannot be used). External interrupts in the KS86C6504/6508 interrupt structure does not meet  
this criteria.  
Note that when Stop mode is released by an external interrupt, the current values in system and peripheral  
control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and  
CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an  
external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization  
interval. To do this, you must make the appropriate control and clock settings before entering Stop mode.  
The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service  
routine, the instruction immediately following the one that initiated Stop mode is executed.  
NOTE  
Do not use the STOP mode when external clock source is being used as the oscillation circuit option.  
IDLE MODE  
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select  
peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt  
logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.  
There are two ways to release Idle mode:  
1. Execute RESET. All system and peripheral control registers are reset to their default values and the contents  
of all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and  
CLKCON.4 are cleared to '00B'. If interrupts are masked, RESET is the only way to release Idle mode.  
2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle  
mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock  
value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction  
immediately following the one that initiated Idle mode is executed.  
NOTE  
Only external interrupts that are not clock-related can be used to release Stop mode. To release Idle  
mode, however, any type of interrupt (that is, internal or external) can be used.  
8-3  
RESET and POWER-DOWN  
S3C9664/P9664 (Preliminary Spec)  
HARDWARE RESET VALUES  
Tables 8-1 through 8-3 list the values for CPU and system registers, peripheral control registers, and peripheral  
data registers following a reset operation in normal operating mode. The following notation is used in these tables  
to represent specific reset values:  
— A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively.  
— An 'x' means that the bit value is undefined following RESET.  
— A dash ('–') means that the bit is either not used or not mapped.  
Table 8-1. Register Map and Reset Status (Page 0)  
Register Name  
Mnemonic  
Address  
Bit Values After RESET  
7
6
5
4
3
2
1
0
General purpose register file & stack  
area  
00–7FH  
x
x
x
x
x
x
x
x
Working register area  
C0H–CFH  
D0H  
x
0
1
0
0
0
0
x
x
0
x
0
1
0
0
0
0
x
0
x
0
x
0
1
0
0
0
0
x
0
x
0
x
0
1
0
0
0
0
x
0
x
0
x
0
1
0
0
0
x
0
x
0
x
0
1
0
0
0
x
0
x
0
x
0
1
0
0
0
x
x
0
x
0
x
0
1
0
0
0
x
x
0
x
0
Timer 0 Counter Register  
Timer 0 Data Register  
T0CNT  
T0DATA  
T0CON  
T0INT  
D1H  
Timer 0 Control Register  
Timer 1 Interrupt Control Register  
Clock Control Register  
D2H  
D3H  
CLKCON  
FLAGS  
ADDATAH  
ADDATAL  
ADCON  
SP  
D4H  
System Flags Register  
D5H  
A/D converter data register(High byte)  
A/D converter data register (Low byte)  
A/D control register  
D6H  
D7H  
D8H  
Stack Pointer Register  
D9H  
Port 2 Data Register  
P2  
DAH  
Location DBH is not mapped.  
Basic Timer Control Register  
Basic Timer Counter  
BTCON  
BTCNT  
DCH  
DDH  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Location DEH is not mapped.  
SYM DFH  
System Mode Register  
0
0
0
0
NOTE: – : Not mapped, x: Undefined  
8-4  
S3C9664/P9664 (Preliminary Spec)  
RESET and POWER-DOWN  
Table 8-1. Register Map and Reset Status (Page 0) (Continued)  
Register Name  
Mnemonic  
Address  
Bit Values After RESET  
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Port 0 data register  
P0  
E0H  
E1H  
E2H  
E3H  
E4H  
E5H  
E6H  
E7H  
E8H  
E9H  
EAH  
EBH  
ECH  
EDH  
EEH  
EFH  
F0H  
F1H  
F2H  
F3H  
Port 1 data register  
P1  
Timer 1 Counter Register  
T1CNT  
Timer 1 Control Register  
T1CON  
P0PURL  
P0PURH  
P0CONL  
P0CONH  
P1CONL  
P1CONH  
P0INT  
Port 0 Pull-up/down register (low byte)  
Port 0 Pull-up/down register (high byte)  
Port 0 control register (low byte)  
Port 0 control register (high byte)  
Port 1 control register (low byte)  
Port 1 control register (high byte)  
Port 0 interrupt enable register  
Port 0 interrupt pending register  
Port 1 interrupt enable register  
Port 1 interrupt pending register  
Timer 1 DATA register  
P0PND  
P1INT  
P1PND  
T1DATA  
P2CONINT  
FADDR  
EP0CSR  
Port 2 control/interrupt register  
USB function address register  
USB control endpoint status register  
USB interrupt endpoint 1 status register EP1CSR  
USB control endpoint byte count  
register  
EP0BCNT  
USB control endpoint FIFO register  
USB interrupt endpoint 1 FIFO register  
USB interrupt pending register  
USB interrupt enable register  
EP0FIFO  
EP1FIFO  
USBPND  
USBINT  
F4H  
F5H  
F6H  
F7H  
F8H  
F9H  
FAH  
FBH  
FCH  
x
x
0
0
0
0
x
0
0
x
x
0
0
0
1
x
0
0
x
x
0
0
0
0
x
0
0
x
x
0
0
0
0
x
0
0
x
x
0
1
0
0
x
0
0
x
x
0
0
0
0
x
0
0
x
x
0
1
0
0
x
0
0
x
x
0
1
0
0
x
0
0
USB power management register  
PWRMGR  
USB interrupt endpoint 2 status register EP2CSR  
USB interrupt endpoint 2 FIFO register  
Endpoint mode register  
EP2FIFO  
EPMODE  
EP1BCNT  
USB interrupt endpoint 1 byte count  
register  
USB control endpoint 2 byte count  
register  
EP2BCNT  
FDH  
0
0
0
0
0
0
0
0
USB control register  
USBCON  
SUBCON  
FEH  
FFH  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sub oscillator control register  
8-5  
RESET and POWER-DOWN  
S3C9664/P9664 (Preliminary Spec)  
Table 8-2. Register Map and Reset Status (Page 1)  
Register Name  
Mnemonic  
Address  
Bit Values After RESET  
7
6
5
4
3
2
1
0
USB signal control register  
XCON  
FEH  
0
0
0
0
0
0
0
0
8-6  
S3C9664/P9664 (Preliminary Spec)  
I/O PORTS  
9
I/O PORTS  
OVERVIEW  
The S3C9664 has three I/O ports (Port 0, Port 1, Port2 only on USB disabled), 18 pins total. You can access  
these ports directly by writing or reading port data register addresses.  
Table 9-1. S3C9664 Port Configuration Overview  
Port  
Function Description  
Programmability  
P0.0-P0.7  
Bit-programmable I/O port for schmitt trigger input, push-pull output and  
N-Ch open drain output. Pull-up/pull-down resistors are assignable by  
software. Port 1 pins can also be used as external interrupt.  
Bit  
P1.0 – P1.5  
P1.6 – P1.7  
Bit-programmable I/O port for schmitt trigger input, schmitt trigger input  
with pull-up and N-Ch open drain output. Port 1 pins can also be used as  
AD converter Channel.  
Bit  
Bit-programmable I/O port for schmitt trigger input, schmitt trigger input  
with pull-up and N-Ch open drain output and push-pull output.  
Bit  
Bit  
P2.0/D-  
– P2.1/D+  
Bit-programmable I/O port for schmitt trigger input, schmitt trigger input  
with pull-up and N-Ch open drain output and push-pull output. Port 2 can  
be individually configured as external interrupt inputs. Also it can be  
configured as an USB ports.  
9-1  
I/O PORTS  
S3C9664/P9664 (Preliminary Spec)  
PORT DATA REGISTERS  
Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics.  
Data registers for ports 0 and 1 have the structure shown in Figure 9-1.  
Table 9-2. Port Data Register Summary  
Register Name  
Port 0 data register  
Port 1 data register  
Port 2 data register  
Mnemonic  
Hex  
E0H  
E1H  
FAH  
R/W  
R/W  
R/W  
R/W  
P0  
P1  
P2  
I/O Port n DATA Register (N = 0-2)  
.7  
.6  
MSB  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Pn.0  
Pn.1  
P0.2  
P1.2  
P0.3  
P1.3  
P0.4  
P1.4  
P0.5  
P1.5  
P0.6  
P1.6  
P0.7  
P1.7  
Figure 9-1. Port Data Register Format  
9-2  
S3C9664/P9664 (Preliminary Spec)  
PORT 0  
I/O PORTS  
Port 0 is bit-programmable, general-purpose, I/O ports. You can configure schmitt trigger input mode with rising  
edge external interrupt or falling edge external interrupt mode, N-channel open drain output and push pull output  
mode. Meanwhile, pull-up and pull-down resister can be can be configured only on input modes .  
In normal operating mode, a reset clears the port 0 control registers (P0CONH, P0CONL, P0PURH, P0PURL) to  
“00H”, configuring P0.0–P0.7 as schmitt trigger input, falling edge external interrupt with pull-up resister  
Port 0 is accessed directly by writing or reading the port 0 data register. P0 (E0H, Page 0).  
Port 0 Control Register, High Byte (P0CONH)  
P0CONH, E7H, R/W (Page 0)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P0.4  
P0.7  
P0.6  
P0.5  
P0CONH  
Port Mode Selection  
7,5,3,1 6,4,2,0  
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt.  
Schmitt trigger input, rising edge external interrupt.  
N-CH open drain output mode.  
Push-pull output mode.  
Figure 9-2. Port 0 Control Registers (P0CONH)  
Port 0 Control Register, Low Byte (P0CONL)  
P0CONL, E6H, R/W (Page 0)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P0.0  
P0.3  
P0.2  
P0.1  
P0CONL  
Port Mode Selection  
7,5,3,1 6,4,2,0  
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt. (or capture input)  
Schmitt trigger input, rising edge external interrupt.  
N-CH open drain output mode.  
Alternative Fuction (P0 output mode: match,PWM)  
Figure 9-3. Port 0 Control Registers (P0CONL)  
9-3  
I/O PORTS  
S3C9664/P9664 (Preliminary Spec)  
Port 0 Pull-Up/Down Control Registers  
P0PURH, E5H, R/W, P0PURL, E4H, R/W (Page 0)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P0.4  
P0.0  
P0.7  
P0.3  
P0.6  
P0.2  
P0.5  
P0.1  
P0PURH  
P0PURL  
7,5,3,1 6,4,2,0  
Port Mode Selection  
0
0
1
1
0
1
0
1
Enable pull-up  
Enable pull-down  
Disable pull-up/down  
Disable pull-up/down  
Figure 9-4. Port 0 Pull-Up/Down Control Registers (P0PURH/P0PURL)  
9-4  
S3C9664/P9664 (Preliminary Spec)  
PORT 1  
I/O PORTS  
Port 1 is bit-programmable, general-purpose, I/O ports. You can configure schmitt trigger input mode, rising edge  
external interrupt with pull-up or falling edge external interrupt mode, N-channel open drain output (only for P1.7,  
P1.6) A/D converter input (only for P1.1-P1.5) and push pull output mode .  
In normal operating mode, a reset clears the port 0 control registers (P1CONH, P1CONL) to “00H”, configuring  
P1.0–P1.7 as schmitt trigger input, falling edge external interrupt with pull-up resister.  
Port 1 is accessed directly by writing or reading the port 1 data register. P1 (E1H, Page 0).  
Port 1 Control Register, High Byte (P1CONH)  
P1CONH, E9H, R/W (Page 0)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P1.4  
P1.7  
P1.6  
P1.5  
P1CONH  
7,5  
0
6,4  
0
Port Mode Selection  
Schmitt trigger input, falling edge external interrupt  
with pull-up.  
Schmitt trigger input, rising edge external interrupt.  
N-CH open drain output mode.  
Push-Pull output  
0
1
1
1
0
1
Port Mode Selection  
3,1  
0
2,0  
0
Schmitt trigger input, falling edge external interrupt  
with pull-up.  
Input,A/D converter off,rising edge external interrupt.  
A/D converter input ; input off  
Push-Pull output  
0
1
1
1
0
1
Figure 9-5. Port 1 Control Register High Byte (P1CONH)  
9-5  
I/O PORTS  
S3C9664/P9664 (Preliminary Spec)  
Port 1 Control Register, Low Byte (P1CONL)  
P1CONL, E8H, R/W (Page 0)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P1.0  
P1.3  
P1.2  
P1.1  
P1CONL  
1
0
0
Port Mode Selection  
0
Schmitt trigger input, falling edge external interrupt  
with pull-up.  
0
1
1
1
0
1
Input,A/D converter off,rising edge external interrupt.  
A/D converter input ; input off  
Push-Pull output  
Figure 9-6. Port 1 Control Register Low Byte (P1CONL)  
9-6  
S3C9664/P9664 (Preliminary Spec)  
PORT 2  
I/O PORTS  
Port 2 can be configured bit-programmable, general-purpose, I/O ports, only when USB ports are disabled  
(USBSEL.0 = 0). Otherwise (USBSEL.1=1), port 2 is used for D+/D-.  
However, in general purpose I/0 port mode. You can configure schmitt trigger input mode, rising edge external  
interrupt and schmitt trigger input falling edge external interrupt mode with pull-up, N-channel open drain output  
and push pull output mode with pull-up.  
In normal operating mode, a reset clears the port 2 control registers (P2CONINT) to “00H”, configuring  
P2.0–P2.1 as schmitt trigger input, rising edge external interrupt with pull-up resister.  
Port 2 is accessed directly by writing or reading the port 2 data register. P2 (EFH, Page 0).  
Port 2 Control Registers  
P2CONINT, EFH, R/W (Page 0)  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
P2.1  
P2.0  
P2.1-P2.0  
Interrupt  
P2.1-P2.0  
Interrupt  
P2CONINT:  
enable bit  
pending bit  
7, 5 6, 4  
Port Mode Selection  
0
0
0
1
Schmitt trigger input, rising edge external interrupt.  
Schmitt trigger input, falling edge external interrupt  
with pull-up.  
1
1
0
1
N-channel open drain output mode.  
Push-Pull output mode with pull-up  
Figure 9-7. Port Control Registers (P2CONINT)  
9-7  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER and TIMER 0  
10 BASIC TIMER and TIMER 0  
MODULE OVERVIEW  
The S3C9664 has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit  
timer/counter is called timer 0.  
Basic Timer (BT)  
You can use the basic timer (BT) in two different ways:  
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction  
— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.  
The functional components of the basic timer block are:  
— Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer  
— 8-bit basic timer counter, BTCNT (DDH, read-only)  
— Basic timer control register, BTCON (DCH, read/write)  
Timer 0  
Timer 0 has three operating modes, one of which you select by the appropriate T0CON setting:  
— Interval timer mode  
— Capture mode with a rising or falling edge trigger at the T0 pin  
— PWM mode  
Timer 0 has the following functional components:  
— Clock frequency divider (fOSC divided by 4096, 256, 8, or 1) with multiplexer  
— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)  
— I/O pin (P1.0/T0) for timer 0 capture input or match output  
— Timer 0 overflow interrupt and match/capture interrupt generation  
— Timer 0 control register, T0CON  
— Timer 0 interrupt control register, T0INT  
10-1  
BASIC TIMER and TIMER 0  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER CONTROL REGISTER (BTCON)  
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer  
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,  
address D3H, and is read/write addressable using Register addressing mode.  
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of  
fOSC/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer  
register control bits BTCON.7–BTCON.4.  
The 8-bit basic timer counter, BTCNT, can be cleared at any time during the normal operation by writing a "1" to  
BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a  
"1" to BTCON.0.  
Basic Timer Control Register (BTCON)  
D3H, Set 1, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Watchdog timer enable bits:  
1010B = Disable watchdog function  
Others = Enable watchdog function  
Divider clear bit for BT and T0:  
0 = No effect  
1 = Clear both dividers  
Basic timer counter clear bits:  
0 = No effect  
1 = Clear BTCNT  
Basic timer input clock selection bits:  
00 = fOSC/4096  
01 = fOSC/1024  
10 = fOSC/128  
11 = Invalid selection  
Figure 10-1. Basic Timer Control Register (BTCON)  
10-2  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER and TIMER 0  
BASIC TIMER FUNCTION DESCRIPTION  
Watchdog Timer Function  
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to  
any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to  
"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by  
the current CLKCON register setting) divided by 4096 as the Basic timer clock.  
A reset whenever a basic timer counter overflow occurs. During the normal operation, the application program  
must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value  
must be cleared (by writing a "1" to BTCON.1) at regular intervals.  
If a system malfunction occurs due to circuit noise or some other error condition, the Basic timer counter clear  
operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the  
normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is  
always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.  
Oscillation Stabilization Interval Timer Function  
You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when Stop  
mode has been released by an external interrupt.  
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then  
starts increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external  
interrupt). When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and  
to gate the clock signal off to the CPU so that it can resume normal operation.  
In summary, the following events occur when Stop mode is released:  
1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and  
oscillation starts.  
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fOSC/4096. If an external  
interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.  
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.  
4. When a BTCNT.4 is set, normal CPU operation resumes.  
5. Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release  
10-3  
BASIC TIMER and TIMER 0  
S3C9664/P9664 (Preliminary Spec)  
Oscillation Stabilization  
Normal Operating mode  
0.8 VDD  
VDD  
Reset ReleaseVoltage  
RESET  
Internal  
Reset  
Release  
0.8 VDD  
Oscillator  
(XOUT)  
Oscillator Stabilization Time  
BTCNT  
clock  
10000B  
BTCNT  
value  
00000B  
tWAIT = 4096x16x1/fOSC  
Basic timer increment and  
CPU operations are IDLE mode  
NOTE:  
During of the oscillator stabilization wait time, tWAIT, when it is released  
by a Power-on-reset is 4096x16/fosc.  
Figure 10-2. Oscillation Stabilization Time on RESET  
10-4  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER and TIMER 0  
Normal  
Operating  
Mode  
STOP Mode  
Oscillation Stabilization Time  
Normal  
Operating  
Mode  
VDD  
STOP  
Instruction  
Execution  
STOP Mode  
Release Signal  
External  
Interrupt  
RESET  
STOP  
Release  
Signal  
Oscillator  
(XOUT)  
BTCNT  
clock  
10000B  
BTCNT  
Value  
00000B  
tWAIT  
Basic Timer Increment  
NOTE:  
Duration of the oscillator stabilzation wait time, tWAIT, it is released by an  
interrupt is determined by the setting in basic timer control register, BTCON.  
BTCON.3  
BTCON.2  
tWAIT  
tWAIT (When fOSC is 10 MHz)  
0
0
1
1
0
1
0
0
4096 x 16/fosc  
1024 x 16/fosc  
128 x 16/fosc  
Invalid setting  
6.55 ms  
1.64 ms  
0.2 ms  
Figure 10-3. Oscillation Stabilization Time on STOP Mode Release  
10-5  
BASIC TIMER and TIMER 0  
S3C9664/P9664 (Preliminary Spec)  
TIMER 0 CONTROL REGISTER (T0CON) AND INTERRUPT CONTROL REGISTER(T0INT)  
You use the timer 0 control register (T0CON) and the timer 0 interrupt control register (T0INT), to  
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)  
— Select the timer 0 input clock frequency  
— Clear the timer 0 counter, T0CNT  
— Enable the timer 0 overflow interrupt and timer 0 match/capture interrupts  
— Clear timer 0 match/capture interrupt pending conditions  
T0CON is located at address D2H and T0INT at address D3H, both are read/write addressable using Register  
addressing mode.  
A reset clears T0CON and T0INT to "00H". This sets timer 0 to normal interval timer mode, selects an input clock  
frequency of fOSC/4096, and disables the timer 0 overflow interrupt and match/capture interrupts. You can clear  
the timer 0 counter at any time during the normal operation by writing a "1" to T0CON.3.  
When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is to be cleared by  
Software. To enable the timer 0 match/capture interrupt, you must write T0INT.2 to "1". To detect an interrupt  
pending condition, the application program polls T0INT.0. When a "1" is detected, a timer 0 match/capture  
interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by  
software by writing a "0" to the timer 0 interrupt pending bit, T0INT.0.  
For a timer 0 overflow interrupt, like the way of handing timer 0 match/capture interrupt, you have to write  
T0INT.3 to “1” to be enabled. timer 0 overflower pending condition can be detected on the condition of TOINT.1  
being set to “1” when the application program polls T0INT.1.and the pending condition must be cleared by  
software by writing T0INT.1 a “0” when the interrupt request has been serviced.  
10-6  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER and TIMER 0  
Timer 0 Control Register (T0CON)  
D2H, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Timer 0 input clock selection bits:  
00 = fOSC/4096  
Not used S3C9664.  
01 = fOSC/256  
10 = fOSC/8  
11 = fOSC/1  
Timer 0 operating mode selection bits:  
00 = Interval mode  
01 = Capture mode (capture on falling edge,  
counter running, OVF can occur)  
10 = Capture mode (capture on rising edge,  
counter running, OVF can occur)  
11 = PWM output (OVF interrupt can occur)  
Timer 0 counter clear bit:  
0 = No effect  
1 = Clear the timer 0 counter (when write)  
Figure 10-4. Timer 0 Control Register (T0CON)  
Timer 0 Interrupt Control Register (T0INT)  
D3H, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used for S3C9664.  
Timer 0 interrupt (T0INT) pending bit:  
0 = No interrupt  
0 = Clear pending bit (when write)  
1 = Interrupt is pending  
T0OVF enable bit:  
0 = Disable overflow  
1 = Enable overflow  
Timer 0 overflow interrupt  
(T0OVF) pending bit:  
0 = No interrupt  
0 = Clear pending bit (when write)  
1 = Interrupt is pending  
T0INT enable bit:  
0 = Disable match/capture  
1 = Enable match/capture  
Figure 10-5. Timer 0 Interrupt Control Register (T0INT)  
10-7  
BASIC TIMER and TIMER 0  
S3C9664/P9664 (Preliminary Spec)  
TIMER 0 FUNCTION DESCRIPTION  
Timer 0 Interrupts  
The timer 0 module can generate two interrupts: the timer 0 overflow interrupt, and the timer 0 match/capture  
interrupt. A timer 0 overflow interrupt pending condition and a timer 0 match /capture interrupt pending condition  
must be cleared by software, however, by writing a "0" to the T0INT.1 and T0INT.0 pending bits.  
Interval Timer Mode  
In interval timer mode, a match signal generates a timer 0 match interrupt and clears the counter. If you write  
the value "FFH" to the timer 0 reference data register, T0DATA, the counter will increment until an overflow  
occurs. (This condition is the same as normal counter operation.)  
T0_OVF  
T0_INT  
P0.0/T0  
PND  
Interrupt  
Enable/Disable  
R (Clear)  
Counter  
(T0CNT)  
PND  
CLK  
Interrupt  
Enable/Disable  
Match  
Comparator  
CTL  
T0CON  
Data Register  
(T0DATA)  
Figure 10-6. Simplified Timer 0 Function Diagram: Interval Timer Mode  
10-8  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER and TIMER 0  
Match  
Match  
Match  
Compare Value  
(T0DATA)  
Match  
Match  
Match Match  
Up Counter Value  
(T0CNT)  
00H  
Count Start  
Clear  
Clear  
Clear  
T0CON.3  
1
T0DATA  
Value  
Change  
Counter Clear  
(T0CON.3)  
Interrupt Request  
(T0CON.0)  
Figure 10-7. Timer 0 Timing Diagram  
10-9  
BASIC TIMER and TIMER 0  
S3C9664/P9664 (Preliminary Spec)  
Pulse Width Modulation Mode  
The PWM cycle width (time) is determined the timer 0 input clock. One cycle is equal to tCLK ´ 28 (for the 8-bit  
counter). The timer 0 data register value determines the pulse modulation width. (The minimum value is Low  
level and the maximum value is High level.) A match signal generates the timer 0 interrupt (T0_INT), but it does  
not clear the timer 0 counter value.  
T0_OVF  
T0_INT  
PND  
Interrupt  
Enable/Disable  
Counter  
(T0CNT)  
PND  
CLK  
Interrupt  
Enable/Disable  
High level when  
data > counter;  
Low level when  
data < counter  
Match  
Comparator  
CTL  
T0CON  
Data Register  
(T0DATA)  
Figure 10-8. Simplified Timer 0 Function Diagram: PWM Mode  
10-10  
S3C9664/P9664 (Preliminary Spec)  
PWM FUNCTION DESCRIPTION  
BASIC TIMER and TIMER 0  
The 8-bit counter counts modulus 256, that is, from 0–255, inclusive. The value of the 8-bit counter is compared  
to the contents of the reference registers, T0DATA. When the reference register value equals the counter value,  
the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio  
(duty) of the PWM output is T0DATA/256.  
All PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value changes  
from FFH back to 00H, the PWM outputs are forced to high level. The pulse width ratio (duty cycle) is defined by  
the contents of the reference register and is programmed in increments of 1:256. The 8-bit PWM data register  
T0DATA is read and written using 8-bit register addressing mode.  
PWM output can be held at low level by continuously loading the reference register with 00H. By continuously  
loading the reference register with FFH, you can hold the PWM output to high level, except for the last pulse of  
the clock source, which sends the output low (see Figure 10-8).  
Table 10-1. PWM Reference Register Duty Values  
Reference Register Value (T0DATA)  
Duty  
0000 0000  
0000 0001  
0/256 (0 %)  
1/256 (0.39 %)  
0000 0010  
2/256 (0.78%)  
1000 0000  
128/256 (50 %)  
1000 0001  
129/256 (50.4 %)  
1111 1110  
254/256 (99.2 %)  
1111 1111  
255/256 (99.6 %)  
...  
...  
...  
...  
0
1
2
254 255  
0
1
2
254 255  
T0CNT Value  
T0DATA = 00H  
T0DATA = 01H  
T0DATA = 80H  
T0DATA = FFH  
Figure 10-9. PWM Output Waveforms  
10-11  
BASIC TIMER and TIMER 0  
Capture Mode  
S3C9664/P9664 (Preliminary Spec)  
In capture mode, the timer 0 counter increases at a rate determined by the timer clock. The trigger signal  
(a rising or falling edge) for the capture operation occurs at the T0 pin. The interrupt service routine stores the  
captured 8-bit timer 0 counter value in the timer 0 data register whenever the capture signal is detected at the  
T0 pin.  
By reading the counter value at programmed intervals, the routine can compare the differences between  
successive read values and calculate elapsed time interval. For example, if 80H is read and then 90H is read,  
this gives a difference of 10H. Depending on the clock speed, you can convert this hexadecimal value into the  
equivalent time interval (in this case, it is approximately 10 milliseconds).  
Counter  
(T0CNT)  
PND  
PND  
CLK  
T0_OVF  
T0_INT  
Interrupt  
Enable/Disable  
P0.0/T0 (CAP)  
Interrupt  
Enable/Disable  
Data Register  
(T0DATA)  
T0CON  
Figure 10-10. Simplified Timer 0 Function Diagram: Capture Mode  
10-12  
S3C9664/P9664 (Preliminary Spec)  
BASIC TIMER and TIMER 0  
Bit 1  
RESET or STOP  
Data Bus  
Bits 3, 2  
Basic Timer Control Register  
(Write '1010xxxxB' to disable.)  
Clear  
1/4096  
1/1024  
8-Bit Up Counter  
(BTCNT, Read-Only)  
RESET  
DIV  
R
XIN  
MUX  
Bits 7, 6  
MUX  
OVF  
1/128  
1/1  
When BTCNT.4 is set after releasing from  
RESET or STOP mode, CPU clock starts.  
Bit3  
Bit 0  
Data Bus  
Bit 1  
T0_OVF  
R
(Timer 0  
Overflow)  
1/4096  
1/256  
1/8  
Clear  
Bit 3  
Bit 2  
Bit 0  
8-Bit Up-Counter  
(T0CNT)  
XIN  
DIV  
R
1/1  
Match  
T0_INT  
(Timer 0  
Match)  
8-Bit Compatator  
T0 (CAP)  
T0 (PWM)  
Bits 5, 4  
Timer 0 Buffer  
Register  
Bits 5, 4  
T0CON (Counter Clear)  
Match (Interval Timer Mode)  
Overflow  
Timer 0 Data  
Register (T0DATA)  
Basic Timer Control Register  
Timer 0 Control Register  
Data Bus  
Timer 0 Interrupt Control Register  
NOTE: During a power-on reset operation, the CPU is idle during the required oscillation  
stabilization interval (until bit 4 of the basic timer counter is set).  
Figure 10-11. Basic Timer and Timer 0 Block Diagram  
10-13  
S3C9664/P9664 (Preliminary Spec)  
TIMER 1  
11 TIMER 1  
OVERVIEW  
The 8-bit timer 1 is an 8-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate  
T1CON setting.  
Timer 1 has the following functional components:  
— Clock frequency divider (fOSC divided by 1024, 256, 64 or 8 ) with multiplexer  
— 8-bit counter (T1CNT at address E2H, Page 0), 8-bit comparator, and 8-bit reference data register  
(T1DATA at address EEH, Page 0)  
— Timer 1 match interrupt generation  
— Timer 1 control register, T1CON (at address E3H read/write, Page 0)  
FUNCTION DESCRIPTION  
Interval Timer Function  
The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1_INT). The application's service  
routine can detect a pending condition of T1_INT by the software and execute it’s sub-routine. When this case is  
used, the T1_INT pending bit must be cleared by the application sub-routine by writing a "0" to the T1CON.0  
pending bit.  
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the  
T1 reference data register, T1DATA. The match signal generates a timer 1 match interrupt (TA_INT) and clears  
the counter.  
If, for example, you write the value 10H to T1DATA and 0FH to T1CON, the counter will increment until it  
reaches 10H. At this point, the Timer 1 interrupt request is generated, the counter value is reset, and counting  
resumes.  
Timer 1 Control Register (T1CON)  
You use the timer 1 control register, T1CON, to  
— Enable the timer 1 operating (interval timer)  
— Select the timer 1 input clock frequency  
— Clear the timer 1 counter, T1CNT  
— Enable the timer 1 interrupt  
— Clear timer 1 interrupt pending conditions  
11-1  
TIMER 1  
S3C9664/P9664 (Preliminary Spec)  
T1CON is located at address E3H, Page 0, and is read/write addressable using Register addressing mode.  
A reset clears T1CON to '00H'. This sets timer 1 to disable interval timer mode, selects an input clock frequency  
of fOSC/1024, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during normal  
operation by writing a "1" to T1CON.3.  
To enable the timer 1 interrupt , you must write T1CON.2 and T1CON.1 to "1". To generate the exact time  
interval, you should write T1CON.3 and .0, which cleared counter and interrupt pending bit. To detect an interrupt  
pending condition, the application program polls pending bit, T1CON.0. When a "1" is detected, a timer 0  
interrupt is pending. When the T1_INT sub-routine has been serviced, the pending condition must be cleared by  
software by writing a "0" to the timer 1 interrupt pending bit, T1CON.0.  
Timer 1 Control Register (T1CON)  
E3H, R/W, Reset: 00H, Page 0  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Timer 1 input clock selection bits:  
00 = fOSC/1024  
01 = fOSC/256  
10 = fOSC/64  
11 = fOSC/8  
Timer 1 interrupt pending bit:  
0 = No interrupt pending  
0 = Clear pending bit (when write)  
1 = Interrupt is pending  
Timer 1 interrupt enable bit:  
0 = Disable interrupt  
1 = Enable interrupt  
Not used.  
Timer 1 count enable bit:  
0 = Disable counting operation  
1 = Enable counting operation  
Timer 1 counter clear bit:  
0 = No effect  
1 = Clear the timer 0 counter (when write)  
Figure 11-1. Timer 1 Control Register (T1CON)  
11-2  
S3C9664/P9664 (Preliminary Spec)  
BLOCK DIAGRAM  
TIMER 1  
Bits 7, 6  
Data Bus  
1/1024  
1/256  
Bit 3  
DIV  
XIN  
MUX  
8-Bit Up-Counter  
(Read-Only)  
R
1/64  
1/8  
Clear  
Pending  
Bit 0  
Bit 2  
8-Bit Compatator  
Match  
T1_INT  
Bit 1  
Timer 1 Buffer  
Register  
8-bit Counter is cleared by bit 3  
Match  
Timer 1 Data  
Register  
(Read/Write)  
Data Bus  
Figure 11-2. Timer 1 Functional Block Diagram  
11-3  
S3C9664/P9664 (Preliminary Spec)  
A/D CONVERTER  
12 A/D CONVERTER  
OVERVIEW  
The A/D converter (ADC) module uses successive approximation logic to convert analog levels at one of the six  
input channels to equivalent 10-bit digital values. The analog input level must lie between the VDD and VSS  
values. The A/D converter has the following components:  
— Six multiplexed analog input pins (AD0–AD5)  
— Analog comparator with successive approximation logic  
— 10-bit A/D conversion data output registers (ADDATAH, ADDATAL)  
— ADC control register (ADCON)  
An analog-to-digital conversion procedure is initiated when the CPU writes a value to the ADCON register at  
address (D8H, Page 0) to select one of the six available input pins. You select the desired input channel by  
setting the appropriate bits in the ADCON register.  
The S3C9664/P9664 microcontroller performs 10-bit conversions for only one input channel at a time. You can  
dynamically select different analog input channels during program execution by manipulating selection bits in the  
ADCON register.  
During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the  
approximate half-way point of an 10-bit register). This register is then updated automatically during each  
conversion step. The successive approximation block performs 10-bit conversions for one input channel at a  
time. You can dynamically select different channels by mainpulating the channel selection bit value  
(ADCON.6–4) in the ADCON register. To start the A/D conversion, you should set a the enable bit, ADCON.0.  
When a conversion is completed, ACON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the  
result is dumped into the ADDATA register where it can be read. The A/D converter then enters an idle state.  
Remember to read the contents of ADDATA before another conversion starts. Otherwise, the previous result will  
be overwritten by the next conversion result.  
NOTE  
Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the  
analog level at the AD0–AD5 input pins during a conversion procedure be kept to an absolute minimum.  
Any change in the input level, perhaps due to circuit noise, will invalidate the result.  
12-1  
A/D CONVERTER  
S3C9664/P9664 (Preliminary Spec)  
INTERNAL REFERENCE VOLTAGE LEVELS  
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input  
level must remain within the range AVSS to VDD  
.
Different reference voltage levels are generated internally along the resistor tree during the analog conversion  
process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 VDD  
.
USING A/D PINS FOR STANDARD DIGITAL INPUT  
The ADC module's input pins are alternatively used as digital input in port 1. The AD0–AD5 share pin names are  
P1.0–P1.5  
A/D CONVERTER CONTROL REGISTER (ADCON)  
The A/D converter control register, ADCON, is located at address D8H, Page 0. ADCON has four functions:  
— Bits 6-4 select an analog input pin (AD0–AD51).  
— Bit 3 indicates the status of the A/D conversion.  
— Bit2-1 select clock source.  
— Bit 0 starts the A/D conversion.  
Only one analog input channel can be selected at a time. You can dynamically select any one of the six analog  
input pins (AD0–AD5) by manipulating the 3-bit value for ADCON.6–ADCON.4  
It’s recomanded that the clock source determinding the conversion speed would be less than 2.5 MHz to get  
sound results.  
12-2  
S3C9664/P9664 (Preliminary Spec)  
A/D CONVERTER  
A/D Converter Control Registers  
D8H, R/W, Page 0  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
.0  
Conversion Start Bit:  
Not used  
0
1
No effect  
A/D conversion start  
Analog Input Pin Selection Bits:  
.6 .6 .6  
Selected Input Pin  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC0 (P1.0)  
ADC1 (P1.1)  
ADC2 (P1.2)  
ADC3 (P1.3)  
ADC4 (P1.4)  
ADC5 (P1.5)  
Conversion Speed Selection Bit: (note)  
00 = fOSC/16 (fOSC 16 MHz)  
01 = fOSC/16 (fOSC < 16 MHz)  
10 = fOSC/16 (fOSC < 16 MHz)  
11 = fOSC/16 (fOSC < 16 MHz)  
<
Not used for KS86C6604  
Not used for KS86C6604  
.3  
End-of-conversion Status Bit:  
0
1
A/D conversion is in progress  
A/D conversion complete (when read)  
Figure 12-1. A/D Converter Control Register (ADCON)  
12-3  
A/D CONVERTER  
S3C9664/P9664 (Preliminary Spec)  
A/D Converter Control Register  
ADCON (D8H, Page 0)  
ADCON .6-.4  
ADCON .0 (ADEN)  
ADCON .3  
(EOC Flag)  
Control  
Circuit  
ADC0/P1.0  
ADC1/P1.1  
ADC2/P1.2  
ADC3/P1.3  
ADC4/P1.4  
ADC5/P1.5  
Successive  
Approximation  
Circuit  
+
_
Analog  
Comparator  
Conversion  
Result  
VDD  
VSS  
D/A Converter  
ADDATAL  
ADDATAH  
(D6H,Page 0)(D7H,Page 0)  
To Data Bus  
Figure 12-2. A/D Converter Circuit Diagram  
ADDATAH MSB  
ADDATAL MSB  
.9  
-
.8  
-
.7  
-
.6  
-
.5  
-
.4  
-
.3  
.1  
.2  
.0  
LSB  
LSB  
Figure 12-3. A/D Converter Data Register (ADDATA)  
12-4  
S3C9664/P9664 (Preliminary Spec)  
A/D CONVERTER  
ADCON.0 <-1  
50 ADC Clock  
Conversion  
Start  
EOC  
. . .  
ADDATA  
9
8
7
6
5
4
3
2
1
0
Valid  
Data  
Previous  
Value  
ADDATAH (8-Bit) + ADDATA (2-Bit)  
40 Clock  
Set up time  
10 clock  
Figure 12-4. A/D Converter Timing Diagram  
CONVERSION TIMING (S3C9664)  
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D  
conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: With an 10 MHz CPU  
clock frequency, one clock cycle is 400 ns (4/fOSC). If each bit conversion requires 4 clocks, the conversion rate  
is calculated as follows:  
4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks  
50 clock x 400 ns = 20 ms at 10 MHz, 1 clock time = 4/fOSC (assuming ADCON.2–.1 = 10)  
INTERNAL A/D CONVERSION PROCEDURE  
1. Analog input must remain between the voltage range of VSS and AVDD  
.
2. Configure the analog input pins to input mode by making the appropriate settings in P1CONH, P1CONL  
3. Before the conversion operation starts, you must first select one of the eight input pins (AD0–AD5) by writing  
the appropriate value to the ADCON register.  
4. When conversion has been completed, (50 CPU clocks have elapsed), the EOC flag is set to "1", so that a  
check can be made to verify that the conversion was successful.  
5. The converted digital value is loaded to the output register, ADDATAH ( High 8-bit) and ADDATAL (Low 2-  
bit), then the ADC module enters an idle state.  
The digital conversion result can now be read from the ADDATAH and ADDATA L registers.  
12-5  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
13 UNIVERSAL SERIAL BUS  
OVERVIEW  
Universal Serial Bus (USB) is a communication architecture that supports data transfer between a host computer  
and a wide range of PC peripherals. USB is actually a cable bus in which the peripherals share its bandwidth  
through a host scheduled token based protocol.  
The USB module in S3C9664 is designed to serve at a low speed transfer rate (1.5 Mbps) USB device as  
described in the Universal Serial Bus Specification Revision 1.1. S3C9664 can be briefly described as a  
microcontroller with SAM 87RCRI core with an on-chip USB peripheral as can be seen in figure 13-1.  
The S3C9664 comes equipped with Serial Interface Engine (SIE), which handles the communication protocol of  
the USB. The S3C9664 supports the following control logic: packet decoding/generation, CRC  
generation/checking, NRZI encoding/decoding, Sync detection, EOP (end of packet) detection and bit stuffing.  
S3C9664 supports two types of data transfer; control and interrupt. Three endpoints are used in this device;  
Endpoint 0, Endpoint 1, Endpoint2. Please refer to the USB specification revision 1.1 for detail description of  
USB.  
D+  
D-  
Transceiver  
Voltage Regulator  
SIE  
SAM88RCRI  
CORE  
(Serial Interface  
Engine)  
Endpoint 0 FIFO  
Endpoint 1 FIFO  
Endpoint 2 FIFO  
Data Bus  
Figure 13-1. USB Peripheral Interface  
13-1  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
Serial Bus Interface Engine (SIE)  
The Serial Interface Engine interfaces to the USB serial data and handles, deserialization/serialization of data,  
NRZI encoding/decoding, clock extraction, CRC generation and checking, bit stuffing and other specifications  
pertaining to the USB protocol such as handling inter packet time out and PID decoding.  
Control Logic  
The USB control logic manages data movements between the CPU and the transceiver by manipulating the  
transceiver and the endpoint register. This includes both transmit and receive operations on the USB. The logic  
contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use  
this to determine the number of bytes to transfer. The same buffer is used for receive transactions to count the  
number of bytes received and transfer that number to the receiver endpoint's byte count register at the end of the  
transaction.  
The control logic in S3C9664, when transmit, manages parallel to serial conversion, packet generation, CRC  
generation, NRZI encoding and bit stuffing.  
When receive, the control logic in S3C9664 handles Sync detection, packet decoding, EOP (End Of Packet)  
detection, remove bit stuffing, NRZI decoding, CRC checking and serial to parallel conversion  
Bus Protocol  
All bus transactions involve the transmission of packets. S3C9664 supports low-speed packets. Each transaction  
starts when the host controller sends a Token Packet to the USB device. The Token packets are generated by  
the USB host and decoded by the USB device. A Token Packet includes the type description, direction of the  
transaction, USB device address and the endpoint number.  
Data and Handshake packets are both decoded and generated by the USB device. In any transaction, the data is  
transferred from the host to a device or from a device to the host. The transaction source then sends a Data  
Packet or indicates that it has no data to transfer. The destination then responds with a Handshake Packet  
indicating whether the transfer was successful.  
Data Transfer Types  
USB data transfer occurs between the host software and a specific endpoint on the USB device. An endpoint  
supports a specific type of data transfer. The S3C9664 supports two types transfer endpoints: control and  
interrupt.  
Control transfer configures and assigns an address to the device when detected. Control transfer also supports  
status transaction, returning status information from device to host.  
Interrupt transfer refers to a small, spontaneous data transfer from USB device to host.  
Endpoints  
Communication flows between the host software and the endpoints on the USB device. Each endpoint on a  
device has an identifier number. In addition to the endpoint number, each endpoint supports a specific transfer  
type. S3C9664 supports three endpoints: Endpoint 0 supports control transfer, and Endpoint 1, Endpoint 2  
supports interrupt transfer.  
13-2  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
Enable  
Reference  
Voltage  
Generator  
Current  
Amplifier  
3.3 V  
A
B
NOTE:  
This block can give a explanation how it can be controlled automatically.  
When the 3.3 voltage regulator be enable by software, voltage regulator will operating  
to cover fluctuation of the line load, sometimes the line is not stabled and the driving  
ability will be dropped.  
As it operating in the normal stage without any peak, power will be supplied with 8 mA,  
and when the operating. Current consumption go to peak, it was designed to cover by  
50 mA. It meas any kind of load problem will be compensated with above design.  
Figure 13-2. Block Diagram of Voltage Regulator  
13-3  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
Pull-up Control  
R, 1.5 K  
W 5 %  
+
C
A
B
DM  
TX/RX  
D-  
DM  
DP  
V33IN  
Control  
Sinals  
Slope  
Control  
CTRL  
D+  
DP  
TX/RX  
Enable  
D
NOTE:  
We didn't used the by-pass capacitor on the 3.3 V out, since the 3.3 V regulator and clamp  
circuit will give a solution through the feedback.  
USB block was designed to cover the line load, the typical value designed is 300 pF (max: 800 pF).  
The calmp block operating after it detect the voltage variation  
(actually the current fluctuation will be feedback into voltage variation, di/dt to dt/dt variation.  
Bias control the slope.  
Control signals means NRZI, EOP, XCON, IN/OUT.  
Enable is for the Tx, Rx.  
Internal pull-up resistor will be 1.5 k  
W
10 %  
+
Figure 13-3. Block Diagram of USB Signal Transceiver  
VDD  
VDD  
DM_DRVP  
Pull-up Enable  
DM_DRVN  
DP_DRVP  
Pull-up Enable  
DP_DRVN  
DM  
GPIO  
DP  
GPIO  
NOTE:  
It explain the PS2 block.  
The pull-up resistor value will be 4.3 k  
W
20 %  
+
This block can be controlled with pull-up resistor and it was designed with totally  
different from usb.  
Figure 13-4. Block Diagram of GPIO Signal Transmitter  
13-4  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
USB FUNCTION ADDRESS REGISTER (FADDR)  
This register holds the USB address assigned by the host computer. FADDR is located at address F0H, Page 0  
and is read/write addressable.  
Bit7  
Not used (Read value will be always "0").  
Bit6–0 FADDR: MCU updates this register when it decodes a SET_ADDRESS command. MCU must write this  
register with clears OUT_PKT_RDY (bit0) and sets DATA_END (bit3) in the EP0CSR register. That is,  
MCU should write #48h to EP0CSR register after write this register. The function controller use this  
register's value to decode USB Token packet address. Reset value of this register is “0”. The new  
address will work after successful status stage.  
USB Function Address Register (FADDR)  
F0H, R/W, Page 0  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used  
7-bit programming device address. This register  
maintains the USB address assigned by the host.  
The function controller uses this register's value  
to decode USB token packet address. At reset  
when the device is not yet configured the value is  
reset to 0.  
Figure 13-5. USB Function Address Register (FADDR)  
13-5  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
CONTROL ENDPOINT STATUS REGISTER (EP0CSR)  
EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is  
located at F1H and is read/write addressable.  
Bit7  
Bit6  
Bit5  
CLEAR_SETUP_END : MCU writes “1” to this bit to clear SETUP_END bit (bit4). This bit is  
automatically cleared after clearing SETUP_END bit by SIE. So read value will be always “0”.  
CLEAR_OUT_PKT_RDY: MCU writes “1” to this bit to clear OUT_PKT_RDY bit (bit0). This bit is  
automatically cleared after clearing OUT_PKT_RDY bit by USB block. So read value will be always “0”.  
SEND_STALL: MCU writes “1” to this bit to send STALL packet to Host, it must clear OUT_PKT_RDY  
(bit 0) at the same time. If MCU receive invalid command then should write #60h to this register. The SIE  
issues a STALL handshake to the current control transfer(Means next transaction). This bit will be  
cleared after sending STALL handshake.  
Bit4  
Bit3  
SETUP_END : SIE sets this bit, when a control transfer ends without setting DATA_END bit (bit3). MCU  
clears this bit, by writing a “1” to CLEAR_SETUP_END bit (bit7). When SIE sets this bit, an interrupt is  
generated to MCU. When such condition occurs, SIE flushes the FIFO. MCU can not access to FIFO  
until this bit cleared. This flag is a read only bit so MCU can not write to this bit directly.  
DATA_END: MCU sets this bit:  
— After loading the last packet of data into the FIFO, and at the same time IN_PKT_RDY bit should be  
set.  
— While it clears OUT_PKT_RDY bit after unloading the last packet of data.  
— For a zero length data phase, this bit should be set when it clears OUT_PKT_RDY bit.  
Bit2  
Bit1  
SENT_STALL: SIE sets this bit after send stall handshake to host. There are two cases which issue stall  
packet to host. If MCU set SEND_STALL bit, then SIE will send stall to the next transaction and set this  
bit. The other case is send stall by SIE automatically since protocol violation. An interrupt is generated  
when this bit gets set. This bit is a read/write bit so MCU should clears this bit to end the STALL  
condition.  
IN_PKT_RDY: MCU sets this bit, after loading data into Endpoint 0 FIFO. SIE clears this bit, once the  
packet has been successfully sent to the host. An interrupt is generated when SIE clears this bit so that  
MCU can load the next packet. For a zero length data phase, MCU sets IN_PKT_RDY bit without load  
data to FIFO.  
Bit0  
OUT_PKT_RDY: SIE sets this bit, if the device receive valid data from host. An interrupt is generated,  
when SIE sets this bit. MCU should download data and clears this bit by writing "1” to  
CLEAR_OUT_PKT_RDY bit at the end of execution.  
NOTES:  
1. When SETUP_END bit is set, OUT_PKT_RDY bit may also be set. This happens when the current transfer has  
terminated by new setup transaction. In such case, MCU should first clear SETUP_END bit, and then start servicing the new  
control transfer.  
13-6  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
INTRRUPT ENDPOINTS STATUS REGISTER (EP1CSR, EP2CSR)  
EP1CSR register controls Endpoint 1, and also holds status bits for Endpoint 1. EP1CSR is located at F2H and is  
read/write addressable. EP2CSR register controls Endpoint2, and the contents is perfectly same to EP1CSR.  
EP2CSR is located at F9H and is read/write addressable.  
EP1CSR and EP2CSR have two modes. These are IN and OUT mode which are decided by ENDPOINT_MODE  
register. The below is IN mode configuration.  
Bit7  
CLR_DATA_TOGGLE : MCU write "1" to this bit for initializing data toggle sequence. Data toggle  
sequence can be monitored through WRT_CNT register.  
Bit6  
Bit5  
Bit4  
Bit3  
MAXP[3].  
MAXP[2].  
MAXP[1].  
MAXP[0].  
— KS86P6604 is a low speed USB controller so the maximum packet size is 8 bytes,  
— This part is a limitation of MAXMUM packet size so the device can not send more data than this  
value.  
Bit2  
UC_FIFO_FLUSH : MCU sets this bit for initializing the FIFO. MCU can not clear IN_PKT_RDY so if  
MCU want to clear IN_PKT_RDY after set then MCU should issue UC_FIFO_FLUSH for clearing  
IN_PKT_RDY.  
Bit1  
Bit0  
FORCE_STALL : MCU sets this bit for sending stall packet. This flag will not be cleared by SIE. So  
MCU should clear this flag for stopping stall condition. Device will send stall until this flag is cleared.  
IN_PKT_RDY : MCU sets this bit after loading data to FIFO. SIE will clear this flag after sending data to  
host. An interrupt is generated when this flag is cleared. If MCU issue UC_FIFO_FLUSH during this flag  
set then this flag is cleared and generate interrupt to MCU. So MCU will get interrupt directly after setting  
UC_FIFO_FLUSH flag if this flag was set.  
13-7  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
INTRRUPT ENDPOINTS STATUS REGISTER (EP1CSR, EP2CSR)  
The below is OUT mode configuration.  
Bit7  
Bit6  
Reserved.  
CLEAR_OUT_PKT_RDY : MCU writes "1" to this bit to clear OUT_PKT_RDY bit (bit0). This bit is  
automatically cleared after clearing OUT_PKT_RDY bit by SIE. So read value will be always "0".  
Bit5  
Bit4  
Bit3  
Reserved.  
Reserved.  
SENT_STALL :. This flag is set by SIE after sending stall packet. And this flag is just for monitoring the  
action of SIE so it does not mean any other things. This flag can be cleared by MCU.  
Bit2  
UC_FIFO_FLUSH : MCU sets this bit for initializing the FIFO. MCU can not clear IN_PKT_RDY so if  
MCU want to clear IN_PKT_RDY after set then MCU should issue UC_FIFO_FLUSH for clearing  
IN_PKT_RDY.  
Bit1  
Bit0  
FORCE_STALL : MCU sets this bit for sending stall packet. This flag will not be cleared by SIE. So  
MCU should clear this flag for stopping stall condition. Device will send stall until this flag is cleared.  
OUT_PKT_RDY : SIE sets this bit, if the device receive valid data from host. An interrupt is generated,  
when SIE sets this bit. MCU should download data and clears this bit by writing "1" to  
CLEAR_OUT_PKT_RDY bit at the end of execution.  
13-8  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
ENDPOINT 0 WRITE COUNT REGISTER (EP0BCNT)  
EP0BCNT register contains data count value, some monitoring and flow control flag. EP0BCNT is located at  
F3H, Page 0 and read addressable.  
Bit7  
Bit6  
DATA_TOGGLE : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.  
TOKEN :.This flag is for monitoring. If this value is set then it means the last received token packet is  
SETUP token and if the value is “0” then the last received token packet is OUT or IN packet.  
Bit5  
Bit4  
OVER_8 :.If device receive over 8 bytes SETUP or OUT transaction then the device does not answer to  
these transaction and set this flag as a error indicator.  
ENABLE :. MCU set this bit for disabling endpoint 0. Device does not answer to any traffic if addressed  
to endpoint 0 until this bit is cleared.  
Bit3  
Bit2  
Bit1  
Bit0  
EP0WRT_CNT[3].  
EP0WRT_CNT[2].  
EP0WRT_CNT[1].  
EP0WRT_CNT[0] : SIE store data count after receive valid data from host. The maximum value is 8.  
And if MCU downloading the FIFO then this value also decreased according to remain data count.  
13-9  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
ENDPOINT 1 WRITE COUNT REGISTER (EP1BCNT)  
EP1BCNT register contains data count value, some monitoring and flow control flag. EP1BCNT is located at  
FCH, Page 0 and read/write addressable.  
Bit7  
Bit6  
Bit5  
DATA_TOGGLE : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.  
Reserved.  
OVER_8 :.If device receive over 8 bytes SETUP or OUT transaction then the device does not answer to  
these transaction and set this flag as a error indicator.  
Bit4  
ENABLE :. MCU set this bit for disabling endpoint 1. Device does not answer to any traffic if addressed  
to endpoint 1 until this bit is cleared.  
Bit3  
Bit2  
Bit1  
Bit0  
EP1WRT_CNT[3].  
EP1WRT_CNT[2].  
EP1WRT_CNT[1].  
EP1WRT_CNT[0] : SIE store data count after receive valid data from host. The maximum value is 8.  
And if MCU downloading the FIFO then this value also decreased according to remain data count.  
13-10  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
ENDPOINT 2 WRITE COUNT REGISTER (EP2BCNT)  
EP2BCNT register contains data count value, some monitoring and flow control flag. EP2BCNT is located at  
FDH, Page 0 and read/write addressable.  
Bit7  
Bit6  
Bit5  
DATA_TOGGLE : This bit is a read only flag. This flag is just for monitoring the data toggle sequence.  
Reserved.  
OVER_8 :.If device receive over 8 bytes SETUP or OUT transaction then the device does not answer to  
these transaction and set this flag as a error indicator.  
Bit4  
ENABLE :. MCU set this bit for disabling endpoint 2. Device does not answer to any traffic if addressed  
to endpoint 2 until this bit is cleared.  
Bit3  
Bit2  
Bit1  
Bit0  
EP2WRT_CNT[3].  
EP2WRT_CNT[2].  
EP2WRT_CNT[1].  
EP2WRT_CNT[0] : SIE store data count after receive valid data from host. The maximum value is 8.  
And if MCU downloading the FIFO then this value also decreased according to remain data count.  
13-11  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
ENDPOINT MODE REGISTER (EPMODE)  
EPMODE register contains the field which defines USB reset signal length and the field which defines the  
direction of endpoints. EPMODE is located at FBH, Page 0 and read/write addressable.  
Bit7  
Bit6  
RESET_LENGTH[1].  
RESET_LENGTH[0] : This field defines the length of USB reset signal. The reset value is "00". MCU  
can control USB reset length through this field. The definition is as below.  
"00" : 22.4 ms + a  
"01" : 12.0 ms + a  
"10" : 6.0 ms + a .  
"11" : 4.0 ms + a  
(a @ 0.66 ms)  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Reserved.  
Reserved.  
Reserved.  
Reserved.  
ENDPOINT_MODE[1] : MCU can defines direction of interrupt transfer. If this value is "1" then endpoint  
2 act as a OUT interrupt endpoint and if this value is "0" then endpoint 2 act as a IN interrupt endpoint.  
The reset value is “0”.  
Bit0  
ENDPOINT_MODE[0] : MCU can defines direction of interrupt transfer. If this value is "1" then endpoint  
1 act as a OUT interrupt endpoint and if this value is "0" then endpoint 1 act as a IN interrupt endpoint.  
The reset value is “0”.  
13-12  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
USB POWER MANAGEMENT REGISTER (PWRMGR)  
PWRMGR register interacts with the Host's power management system to execute system power events such as  
SUSPEND or RESUME. And this register also contains monitoring field for detail control of MCU. This register is  
located at address F8H, Page 0 and is read/write addressable.  
Bit7  
Bit6  
Bit5  
Bit4  
Reserved.  
Reserved.  
Reserved.  
VPIN : MCU can read the VPIN value through this bit. This value is the output of transceiver and the  
input of USB module. And this value is different from the port VPIN value. Port VP value is the input of  
controller, not USB module.  
Bit3  
Bit2  
Bit1  
Bit0  
VMIN : MCU can read the VMIN value through this bit. This value is the output of transceiver and the  
input of USB module. And this value is different from the port VMIN. Port VM value is the input of  
controller, not USB module.  
CLEAR_SUSP_CNT : MCU write "1" value to this bit for clearing suspend counter which count 3 ms.  
And during this value stay "1" the suspend counter does not proceed. That means the USB controller can  
not go into suspend state during this value stays "1".  
SEND_RESUME: While in SUSPEND state, if the MCU wants to initiate RESUME, it writes "1" to this  
register for 10ms (maximum of 15ms), and clears this register. In SUSPEND mode if this bit reads "1"  
then SIE generates RESUME signaling to upstream.  
SUSPEND_STATE: Suspend state is set when the MCU sets suspend interrupt. This bit is cleared  
automatically when:  
— MCU writes "0" to SEND_RESUME bit to end the RESUME signaling (after SEND_RESUME is set  
for 10ms).  
— MCU receives RESUME signaling from the Host while in SUSPEND mode.  
USB Power Mangement Register (PWRMGR)  
F8H, R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Reserved  
SUSPEND_STATE  
SEND_RESUME  
CLEAR_SUSP_CNT  
VPIN  
VMIN  
Figure 13-6. USB Power Management Register (PWRMGR)  
13-13  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
CONTROL ENDPOINT FIFO REGISTER (EP0FIFO)  
This register is bi-directional, 8 byte depth FIFO used to transfer Control Endpoint data. EP0FIFO is located at  
address F4H and is read/write addressable.  
Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control  
transfer, that is, after MCU unload the setup token bytes, and clears OUT_PKT_RDY, the direction of FIFO is  
changed automatically from MCU to the Host.  
INTERRUPT ENDPOINT 1 FIFO REGISTER (EP1FIFO)  
EP1FIFO is an bi-direction 8-byte depth FIFO used to transfer data from the MCU to the Host or from the Host to  
the MCU. MCU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB recieves  
valid data through this register , it sets OUT_PKT_RDY , after MCU unload Data bytes, and clears  
OUT_PKT_RDY , This register is located at address F5H.  
INTERRUPT ENDPOINT 2 FIFO REGISTER (EP2FIFO)  
EP2FIFO is an bi-direction 8-byte depth FIFO used to transfer data from the MCU to the Host or from the Host to  
the MCU. MCU writes data to this register, and when finished set IN_PKT_RDY. Meanwhile, when USB recieves  
valid data through this register , it sets OUT_PKT_RDY , after MCU unload Data bytes, and clears  
OUT_PKT_RDY , This register is located at address FAH.  
USB INTERRUPT PENDING REGISTER (USBPND)  
USBPND register has the interrupt bits for endpoints and power management. This register is cleared once read  
by MCU. While any one of the bits is set, an interrupt is generated. USBPND is located at address F6H.  
Bit7–6 Not used  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
USB_RST_PND: This bit is set, when USB reset signal is received.  
ENDPT2_PND: This bit is set, when Endpoint 2 needs to be received.  
RESUME_PND: While in suspend mode, if resume signaling is received this bit gets set.  
SUSPEND_PND: This bit is set, when suspend signaling is received.  
ENDPT1_PND: This bit is set, when Endpoint 1 needs to be serviced.  
ENDPT0_PND: This bit is set, when Endpoint 0 needs to be serviced. It is set under any one of the  
following conditions:  
— OUT_PKT_RDY is set.  
— IN_PKT_RDY gets cleared.  
— SENT_STALL gets set.  
— DATA_END gets cleared.  
— SETUP_END gets set.  
13-14  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
USB Interrupt Pending Register (USBPND)  
F6H, R/W, Page 0  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used  
ENDPT0_PND  
USB_RST_PND  
ENDTT2_PND  
RESUME_PND  
SUSPEND_PND  
ENDPT1_PND  
Figure 13-7. USB Interrupt Pending Register (USBPND)  
13-15  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
USB INTERRUPT ENABLE REGISTER (USBINT)  
USBINT is located at address F7H, Page 0 and is read/write addressable. This register serves as an interrupt  
mask register. If the corresponding bit = 1 then the respective interrupt is enabled.  
By default, all interrupts except suspend interrupt is enabled. Interrupt enables bits for suspend and resume is  
combined into a single bit (bit 2).  
Bit7–5 Not used  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
ENABLE_USB_RST_INT:  
1 Enable USB RESET INTERRUPT (default)  
0 Disable USB RESET INTERRUPT  
ENABLE_ENDPT2_INT:  
1 Enable ENDPOINT 2 INTERRUPT (default)  
0 Disable ENDPOINT 2 INTERRUPT  
ENABLE_SUSPEND_RESUME_INT:  
1 Enable SUSPEND and RESUME INTERRUPT  
0 Disable SUSPEND and RESUME INTERRUPT (default)  
ENABLE_ENDPT1_INT:  
1 Enable ENDPOINT 1 INTERRUPT (default)  
0 Disable ENDPOINT 1 INTERRUPT  
ENABLE_ENDPT0_INT:  
1 Enable ENDPOINT 0 INTERRUPT (default)  
0 Disable ENDPOINT 0 INTERRUPT  
USB Interrupt Enable Register (USBINT)  
F7H, R/W, Page 0  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used  
ENABLE_ENDPT0_INT  
ENABLE_ENDPT1_INT  
ENABLE_SUSPEND_RESUME_INT  
ENABLE_USB_RST_INT  
ENABLE_ZNDPT2_INT  
Figure 13-8. USB Interrupt Enable Register (USBINT)  
13-16  
S3C9664/P9664 (Preliminary Spec)  
UNIVERSAL SERIAL BUS  
USB CONTROL REGISTER (USBCON)  
USBCON is for the control of USB data line and the control of reset .This register is located at address FEH,  
Page 0 and is read/write addressable.  
Bit5  
Bit4  
DP/DM Control: When this bit is set , DP/DM lines can be controlled by MCU as bellows  
DP: On the condition of bit5 set, if this bit is 1 , DP line is to be high and the other case this bit is 0  
DP line is low .  
Bit3  
Bit2  
DM: On the condition of bit5 set, if this bit is 1 , DM line is to be high and the other case this bit is 0  
DM line is low .  
USB_RESET_EN: When this bit is set , it is USB is made reset , which trigger MCU reset  
automatically  
Bit1  
Bit1  
MCU_RESET: When this bit is set , MCU makes USB reset  
USB_RSTN: USB reset status bit  
0 : USB is not reset  
1 : USB is reset  
USB Control Register (USBCON)  
FEH (Page 0), R/W  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Not used  
USB_RSTN  
MCU_RESET  
USB_RESET_EN  
DP/DM_CONTROL  
DM  
DP  
Figure 13-9. USB Control Register (USBCON)  
13-17  
UNIVERSAL SERIAL BUS  
S3C9664/P9664 (Preliminary Spec)  
XCON REGISTER (XCON)  
XCON register is an 8-bit register that is used to adjust signal quality and Port2 (D+/D-) configuration. This  
register is located at address FEH (Page1 ) and is read/write addressable.  
Bit7  
Pull-up resister at(D-) enable bit:  
0 : Pull up resister at (D-) disable  
1 : Pull up resister at (D-) enable  
Bit7  
GPIO or USB Port Select bit:  
0 : General in/out port enable  
1 : USB port enable  
DM  
DP  
1
Bit  
X
X
X
X
5
4
3
2
0
Edge Control  
Rise edge  
Bit 5, 2  
0
Bit 4, 1  
Bit 3, 0  
DLY Value  
Unit  
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DLY 0  
DLY 1  
DLY 2  
DLY 4  
DLY 0  
DLY 1  
DLY 2  
DLY 4  
About 2.5 nsec  
Fall edge  
1
NOTE: DLY means delay time of rising/fallling time.  
Result, DM  
x - point 1 x - point 2  
DP DM DP  
(VDD = 5.12 V)  
NUM  
HEX Value  
1
2
3
4
5
0x00  
0x38  
0x3C  
0x3D  
0x3E  
Default value, 0.88 V, 1.19 V  
1.58 V, 1.55 V  
1.50 V, 1.50 V  
1.65 V, 1.65 V  
Good  
1.80 V, 1.80 V  
NOTE: This value is only for OTP products.  
13-18  
S3C9664/P9664 (Preliminary Spec)  
SUB RC OSCILLATOR  
14 SUB RC OSCILLATOR  
OVERVIEW  
The S3C9664 have a programmable SUB RC oscillator. During IDLE or STOP, programmable SUB RC oscillator  
generated interrupt using SUB RC oscillator control register (SUBCON).  
SUB RC OSCILLATOR CONTROL REGISTER (SUBCON)  
SUB RC OSCILLATOR Control Register  
MSB  
.7  
.6  
.5  
.4  
.3  
.2  
.1  
.0  
LSB  
Sub RC Oscillator counter input clock  
selection bits:  
Interrupt enable bit:  
1 = Interrupt enable  
0 = Interrupt disable  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
fOSC/2048  
fOSC/3072  
fOSC/4096  
fOSC/6144  
fOSC/8192  
fOSC/12288  
fOSC/16384  
fOSC/24576  
Interrupt pending bit:  
1 = No pending  
0 = Pending  
SUB RC OSCILLATOR enable bit:  
1 = Sub oscillator enable  
0 = Sub oscillator disable  
Not used  
NOTE:  
fOSC = 130 kHz typ. When VDD = 0.5 V, TA = 25 C  
Figure 14-1. SUB RC OSCILLATOR Control Register  
14-1  
S3C9664/P9664 (Preliminary Spec)  
LVR (LOW VOLTAGE RESET)  
15 LVR (LOW VOLTAGE RESET)  
OVERVIEW  
The S3C9664 have a LVR (Low Voltage Reset) for power on reset and voltage reset.  
Reference  
Start Up  
Voltage  
Generator  
Glitch Filter  
RESET  
Comparator  
Voltage  
Divider  
Figure 15-1. LVR Architecture  
— Low Voltage Reset generated RESET signal.  
— Start Up Circuit: Start up reference voltage generator circuit when device powered.  
— Reference Voltage Generator: Supply Voltage independent reference voltage generator.  
— Voltage Divider: Divide supply voltage by “N”  
— Comparator: Compare reference voltage and divided voltage.  
— Glitch Filter: Remove glitch and noise signal.  
15-1  
LVR (LOW VOLTAGE RESET)  
S3C9664/P9664 (Preliminary Spec)  
Vc (Compare Voltage)  
Divide Voltage  
NOTES:  
1. LVD Operation Voltage Range: 2.3 V-6.0 V  
2. LVD Detection Voltage Range: 3.4 V  
3. LVD Current Consumption:  
0.4 V  
Reference Voltage  
Less then 10 uA (normally 5 uA)  
4. LVD Powered Reset Release Time:  
more then 500 usec (LVD only, typical)  
5. LVD Simulation Conditions (Hspice Simulation)  
Temp: 0 - 80 C  
Process Veriation: Worst to best conditions  
Test Voltage: 0.0 V-7.0 V  
Powered Slew Rate: 5 V/1 usec- 5 V/10 msec  
VDD (Supply Voltage)  
Normal Operation  
Reset Operation  
by LVD  
Figure 15-2. LVR Characteristics  
15-2  
S3C9664/P9664 (Preliminary Spec)  
LVR (LOW VOLTAGE RESET)  
LVR AND POWER ON RESET OPERATIONS  
T2  
Oscillation Stabilization Time  
Normal Operating mode  
VDD  
LVD  
RESET  
Release  
T1  
LVD RESET Release Time  
Internal  
RESET  
Release  
Oscillator  
(XOUT)  
T3  
Oscillator Stabilization Time  
BTCNT  
clock  
10000B  
BTCNT  
value  
00000B  
tWAIT = (4096x16)/fOSC  
Basic timer increment and  
CPU operations are IDLE mode  
NOTES:  
1. T1 = 500 usc (at normal)  
2. T2 = T1 + (4096 x 16)/fOSC  
Figure 15-3. LVR and Power On RESET Operation  
15-3  
S3C9664/P9664 (Preliminary Spec)  
ELECTRICAL DATA  
16 ELECTRICAL DATA  
OVERVIEW  
In this section, the following S3C9664 electrical characteristics are presented in tables and graphs:  
— Absolute maximum ratings  
— D.C. electrical characteristics  
— I/O capacitance  
— A.C. electrical characteristics  
— Oscillator characteristics  
— Operating voltage range  
— Oscillation stabilization time  
— Clock timing measurement points at XIN  
— Data retention supply voltage in Stop mode  
— Stop mode release timing when initiated by a RESET  
— Stop mode release timing when initiated by an external interrupt  
— Characteristic curves  
— AD Converter Electrical Characteristics  
16-1  
ELECTRICAL DATA  
S3C9664/P9664 (Preliminary Spec)  
Table 16-1. Absolute Maximum Ratings  
°
(TA = 25 C)  
Parameter  
Symbol  
Conditions  
Rating  
Unit  
VDD  
Supply voltage  
– 0.3 to + 6.5  
– 0.3 to VDD + 0.3  
V
VI  
VO  
IOH  
Input voltage  
All ports  
V
V
– 0.3 to VDD + 0.3  
– 18  
Output voltage  
Output current high  
All output ports  
One I/O pin active  
mA  
All I/O pins active  
One I/O pin active  
– 60  
+ 30  
IOL  
Output current low  
mA  
Total pin current for ports 0, 1, 2  
+ 100  
TA  
°
C
Operating  
0 to + 85  
temperature  
TSTG  
Storage  
– 60 to + 150  
temperature  
16-2  
S3C9664/P9664 (Preliminary Spec)  
ELECTRICAL DATA  
Table 16-2. D.C. Electrical Characteristics  
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.25 V)  
°
°
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
VIH1  
All input pins except VIH2, D+, D– 0.8 VDD  
VDD  
Input highvoltage  
V
VIH2  
VIL1  
VIL2  
VOH  
XIN  
VDD – 0.5  
VDD  
0.2 VDD  
0.4  
All input pins except VIL2, D+, D–  
XIN  
Input low voltage  
VDD = 4.0 V – 5.25 V  
IOH = – 200 mA  
VDD – 1.0  
Output high voltage  
All output ports except D+, D–  
VDD = 4.0 V – 5.25 V  
IOL = 2 mA  
VOL  
Output low voltage  
0.4  
3
All output ports except D+, D–  
VIN = VDD  
All inputs except ILIH2  
except D+, D–, XOUT  
VIN = VDD, XIN  
ILIH1  
Input high leakage  
current  
µA  
ILIH2  
ILIL1  
20  
VIN = 0 V  
Input low leakage  
current  
– 3  
All inputs except ILIL2  
except D+, D–, XOUT  
VIN = 0 V, XIN  
ILIL2  
ILOH  
– 20  
3
VOUT = VDD  
Output high leakage  
current  
All output pins except D+, D–  
VOUT = 0 V  
ILOL  
Output low leakage  
current  
– 3  
All output pins except D+, D–  
XOUT  
RL1  
RL2  
RL3  
IDD1  
VIN = 0 V, VDD = 5.0 V,  
Port 0, Port 1,Port2  
VIN = 0 V, VDD = 5.0 V,  
RESET only  
Pull-up resistors  
25  
100  
25  
50  
220  
50  
100  
400  
100  
15  
KW  
VIN = 0 V, VDD = 5.0 V,  
Port 0  
Pull-down resistors  
Supply current  
KW  
Normal operation mode,  
VDD = 5 V ± 10 %,  
6.5  
mA  
6 MHz, CPU clock  
IDD2  
IDLE mode  
VDD = 5 V ± 10 %,  
6 MHz, CPU clock  
4
8
IDD3  
Stop mode, oscillator stop  
150  
300  
µA  
VDD = 5 V ± 10 %,  
NOTES:  
1. Supply current does not include current drawn through internal pull-up resistors or external output current load.  
2. This parameter is guaranteed, but not tested (include D+, D–).  
3. Only in 4.0 V to 5.25 V, D+ and D– satisfy the USB spec 1.1.  
16-3  
ELECTRICAL DATA  
S3C9664/P9664 (Preliminary Spec)  
Table 16-3. Input/Output Capacitance  
°
°
(TA = 0 C to + 85 C, VDD = 0 V)  
Parameter  
Input  
capacitance  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
CIN  
f = 1 MHz; unmeasured pins  
are connected to VSS  
10  
pF  
COUT  
CIO  
Output  
capacitance  
expect XIN, XOUT  
I/o capacitance  
CXI, CXO XIN, XOUT  
XI/XO capacitance  
33  
Table 16-4. A.C. Electrical Characteristics  
°
°
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.25 V)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
tNF1H, tNF1L  
Noise filter  
P1 (RC delay)  
100  
200  
ns  
tNF1L  
tNF1H  
tNF2  
0.8 VDD  
0.2 VDD  
0.5 VDD  
Figure 16-1. Input Timing for External Interrupts  
16-4  
S3C9664/P9664 (Preliminary Spec)  
ELECTRICAL DATA  
Table 16-5. Oscillator Characteristics  
°
°
(TA = 0 C + 85 C)  
Oscillator  
Clock Circuit  
Test Condition  
Min  
Typ  
Max  
Unit  
Main crystal Main  
ceramic  
Oscillation frequency  
VDD = 4.0 V – 5.25 V  
6.0  
MHz  
X
X
IN  
(fOSC  
)
OUT  
External clock  
Oscillation frequency  
VDD = 4.0 V – 5.25 V  
6.0  
X
X
IN  
OUT  
Table 16-6. Oscillation Stabilization Time  
°
°
(TA = 0 C + 85 C, VDD = 4.0 V to 5.25 V)  
Oscillator  
Main crystal  
Test Condition  
Min  
Typ  
Max  
Unit  
VDD = 4.0 V to 5.25 V, fOSC > 6.0 MHz  
10  
ms  
(Oscillation stabilization occurs when VDD is equal to  
the minimum oscillator voltage range.)  
Main ceramic  
216/fOSC  
t
stop mode release time by a reset  
Oscillator  
stabilization wait  
time  
WAIT  
t
stop mode release time by an interrupt  
WAIT  
NOTE: The oscillator stabilization wait time, t  
, when it is released by an interrupt, is determined by the setting in the  
WAIT  
basic timer control register, BTCON.  
16-5  
ELECTRICAL DATA  
S3C9664/P9664 (Preliminary Spec)  
1/fOSC  
t
XL  
tXH  
V
DD - 0.5 V  
0.4 V  
X
IN  
Figure 16-2. Clock Timing Measurement Points at XIN  
Table 16-7. Data Retention Supply Voltage in Stop Mode  
°
°
(TA = 0 C to + 70 C)  
Parameter  
Symbol  
Conditions  
Stop mode  
Min  
Typ  
Max  
Unit  
VDDDR  
Data retention  
supply voltage  
2.0  
6
V
IDDDR  
Stop mode; VDDDR = 2.0 V  
Data retention  
supply current  
5
µA  
16-6  
S3C9664/P9664 (Preliminary Spec)  
ELECTRICAL DATA  
IDLE Mode  
(Basic Timer Active)  
Stop Mode  
Data Retention Mode  
VDDDR  
VDD  
Normal  
Operating  
Mode  
Execution Of  
Stop Instrction  
External  
Interrupt  
0.8 VDD  
0.2 VDD  
tWAIT  
Figure 16-3. Stop Mode Release Timing When Initiated by an External Interrupt  
Table 16-8. Low Speed Source Electrical Characteristics (USB)  
(TA = 0°C to + 85°C, Voltage Regulator Output V33OUT = 2.8 V to 3.5 V, typ 3,3 V)  
Parameter  
Transition Time:  
Symbol  
Conditions  
Min  
Max  
Unit  
Rise Time  
Tr  
Tf  
CL = 200 pF  
75  
ns  
CL = 650 pF  
CL = 200 pF  
CL = 650 pF  
(Tr/Tf) CL = 50 pF  
CL = 50 pF  
300  
Fall Time  
75  
300  
125  
2.0  
3.6  
Rise/Fall Time Matching  
Trfm  
Vcrs  
80  
1.3  
2.8  
%
V
Output Signal Crossover Voltage  
Output Voltage Regulator Built-in  
V33OUT VDD = 4.0–5.25 V  
V
16-7  
ELECTRICAL DATA  
S3C9664/P9664 (Preliminary Spec)  
Test  
Point  
V33OUT  
90 %  
90 %  
Measurement  
Points  
S/W  
R2  
10 %  
10 %  
D. U. T  
R1  
C2  
Tr  
Tf  
R1 = 15 K  
R2 = 1.5 K  
CL = 200 pF - 650 pF  
W
W
DM: S/W ON  
DP: S/W OFF  
Figure 16-4. USB Data Signal Rise and Fall Time  
3.3 V  
DP  
MAX: 2.0 V  
VCRS  
MIN: 1.3 V  
0 V  
DM  
Figure 16-5. USB Output Signal Crossover Point Voltage  
16-8  
S3C9664/P9664 (Preliminary Spec)  
ELECTRICAL DATA  
Table 16-9. A/D Converter Electrical Characteristics  
(T = – 40 C to + 85 C, VDD = 4.2 V to 5.25 V, VSS = 0 V) S3C9664/P9664: 10-bit ADC  
°
°
A
Parameter  
Symbol  
Test Conditions  
VDD = 5.12 V  
Min  
Typ  
Max  
Unit  
Total accuracy  
LSB  
± 3  
CPU clock = 10 MHz  
VDD = 5.12 V  
VSS = 0 V  
Integral linearity  
error  
ILE  
DLE  
EOT  
EOB  
tCON  
VIAN  
RAN  
IADIN  
I
ADC  
± 2  
± 1  
± 3  
± 2  
Differential  
linearity error  
– 1  
Offset error of  
top  
Offset error of  
bottom  
– 1  
50x4/ fOSC  
Conversion  
time(1)  
fcpu = 10 MHz  
VSS  
2
ms  
V
VDD  
Analog input  
voltage  
Analog input  
impedance  
MW  
mA  
VDD = 5 V  
Analog input  
current  
10  
V
DD
= 5 V  
VDD = 5 V  
ADC block  
current(2)  
1
3
mA  
nA  
100  
500  
Power down mode  
NOTES:  
1. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends.  
2. is operating current during A/D conversion.  
I
ADC  
16-9  
S3C9664/P9664 (Preliminary Spec)  
MECHANICAL DATA  
17 MECHANICAL DATA  
OVERVIEW  
This section contains the following information about the device package:  
— Package dimensions in millimeters  
— Pad diagram  
#20  
#11  
0-15  
20-DIP-300A  
#1  
#10  
26.80 MAX  
26.40 ± 0.20  
0.46 ± 0.10  
1.52 ± 0.10  
2.54  
(1.77)  
NOTE: Dimensions are in millimeters.  
Figure 17-1. 20-DIP-300A Package Dimensions  
17-1  
MECHANICAL DATA  
S3C9664/P9664 (Preliminary Spec)  
0-8  
#20  
#11  
20-SOP-300  
+ 0.10  
0.20 - 0.05  
#1  
#10  
14.10 MAX  
13.70 ± 0.20  
0.10 MAX  
1.27  
(1.14)  
+ 0.10  
0.40 - 0.05  
NOTE: Dimensions are in millimeters.  
Figure 17-2. 20-SOP-300 Package Dimensions  
17-2  
S3C9664/P9664 (Preliminary Spec)  
MECHANICAL DATA  
#24  
#13  
0-15  
24-SDIP-300  
#1  
#12  
23.35 MAX  
22.95 ± 0.20  
0.46 ± 0.10  
0.89 ± 0.10  
1.778  
(1.70)  
NOTE: Dimensions are in millimeters.  
Figure 17-3. 24-SDIP-300 Package Dimensions  
17-3  
MECHANICAL DATA  
S3C9664/P9664 (Preliminary Spec)  
0-8  
#24  
#13  
24-SOP-300  
+ 0.10  
0.20 - 0.05  
#1  
#12  
15.60 MAX  
15.20 ± 0.20  
0.10 MAX  
1.27  
+ 0.10  
0.45 - 0.05  
NOTE: Dimensions are in millimeters.  
Figure 17-4. 24-SOP-300 Package Dimensions  
17-4  
S3C9664/P9664 (Preliminary Spec)  
S3P9664 OTP  
18 S3P9664 OTP  
OVERVIEW  
The S3C9664 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9664  
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data  
format.  
The S3P9664 is fully compatible with the S3C9664, both in function and in pin configuration. Because of its  
simple programming requirements, the S3P9664 is ideal for use as an evaluation chip for the S3C9664.  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VSS/VSS  
XOUT  
1
2
3
4
5
6
7
8
9
10  
VDD/VDD  
D-/P2.0/INT2/SCLK  
D+/P2.1/INT2/SDAT  
P1.0/AD0/INT1  
P1.1/AD1/INT1  
P1.2/AD2/INT1  
P1.3/AD3/INT1  
P1.4/AD4/INT1  
P1.5/AD5/INT1  
P0.5/INT0  
XIN  
S3P9664  
TEST/TEST  
P0.0/INT0/T0 (CAP/PWM)  
P0.1/INT0  
(20-SOP-300)  
(20-DIP-300)  
RESET/RESET  
P0.2/INT0  
P0.3/INT0  
P0.4/INT0  
Figure 18-1. S3P9664 Pin Assignments (20-Pin Package)  
18-1  
S3P9664 OTP  
S3C9664/P9664 (Preliminary Spec)  
VDD/VDD  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VSS/VSS  
XOUT  
1
2
3
4
5
6
7
8
D-/P2.0/INT2/SCLK  
D+/P2.1/INT2/SDAT  
P1.0/AD0/INT1  
P1.1/AD1/INT1  
P1.2/AD2/INT1  
P1.3/AD3/INT1  
P1.4/AD4/INT1  
P1.5/AD5/INT1  
P0.5/INT0  
XIN  
TEST/TEST  
P0.0/INT0/T0 (CAP/PWM)  
P0.1/INT0  
S3P9664  
RESET/RESET  
P0.2/INT0  
(24-SOP-300)  
(24-SDIP-300)  
P0.3/INT0  
P0.4/INT0  
P0.6/INT0  
P0.7/INT0  
9
10  
11  
12  
P1.6/INT1  
P1.7/INT1  
Figure 18-2. S3P9664 Pin Assignments (24-Pin Package)  
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM  
During Programming  
Main Chip  
Pin Name  
Pin Name  
Pin No.  
(24 DIP)  
I/O  
Function  
P1.0  
SDAT  
23  
I/O  
Serial Data Pin (Output when reading, Input  
when writing) Input and Push-pull Output Port  
can be assigned  
P1.1  
SCLK  
22  
5
I/O  
I
Serial Clock Pin (Input Only Pin)  
VPP (TEST)  
TEST  
0V : OTP write and test mode  
5V : Operating mode  
8
I
Chip Initialization and EPROM Cell Writing  
Power Supply Pin (Indicates OTP Mode  
Entering) When writing 12.5V is applied and  
when reading.  
RESET  
RESET  
VDD/VSS  
VDD/VSS  
24/1  
I
Logic Power Supply Pin.  
Table 18-2. Comparison of S3P9664 and S3C9664 Features  
S3P9664  
Characteristic  
S3C9664  
Program Memory  
4 K byte EPROM  
4.0 V to 5.25 V  
4 K byte mask ROM  
4.0 V to 5.25 V  
Operating Voltage (VDD  
)
OTP Programming Mode  
VDD = 5 V, V (RESET) =12.5V  
PP  
Pin Configuration  
20 SOP/20 DIP/24 SOP/24 SDIP  
User Program 1 time  
20 SOP/20 DIP/24 SOP/24SDIP  
Programmed at the factory  
EPROM Programmability  
18-2  
S3C9664/P9664 (Preliminary Spec)  
DEVELOPMENT TOOLS  
19 DEVELOPMENT TOOLS  
OVERVIEW  
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development  
support system is configured with a host system, debugging tools, and support software. For the host system, any  
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool  
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for  
S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.  
Samsung also offers support software that includes debugger, assembler, and a program for setting options.  
SHINE  
Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE  
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked  
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be  
sized, moved, scrolled, highlighted, added, or removed completely.  
SAMA ASSEMBLER  
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates  
object code in standard hexadecimal format. Assembled program code includes the object code that is used for  
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and  
an auxiliary definition (DEF) file with device specific information.  
SASM86  
The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a  
source file containing assembly language statements and translates into a corresponding source code, object  
code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating  
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked  
with other object files and loaded into memory.  
HEX2ROM  
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be  
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code(.OBJ file) by  
HEX2ROM, the value 'FF' is filled into the unused ROM area up to the maximum ROM size of the target device  
automatically.  
19-1  
DEVELOPMENT TOOLS  
TARGET BOARDS  
S3C9664/P9664 (Preliminary Spec)  
Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters  
are included with the device-specific target board.  
OTPs  
One times programmable microcontrollers (OTPs) are under development for S3C9664/P9664 microcontroller.  
IBM-PC AT or Compatible  
RS-232C  
SMDS2+  
Target  
Application  
System  
PROM/OTP Writer Unit  
RAM Break/Display Unit  
Trace/Timer Unit  
Probe  
Adapter  
TB9664  
Target  
Board  
POD  
SAM8 Base Unit  
EVA  
Chip  
Power Supply Unit  
Figure 19-1. SMDS Product Configuration (SMDS2+)  
19-2  
S3C9664/P9664 (Preliminary Spec)  
TB9664 TARGET BOARD  
DEVELOPMENT TOOLS  
The TB9664 target board is used for the S3C9664/P9664 microcontrollers. It is supported by the SMDS2+  
development system.  
TB9664  
To User_VCC  
Off  
On  
RESET  
Idle  
Stop  
+
+
25  
1
J101  
144 QFP  
S3E9600X  
EVA Chip  
1
20  
1
36  
External  
Triggers  
10  
11  
SMDS2  
SMDS2+  
CH1  
CH2  
SW1  
SM1330A  
Figure 19-2. TB9664 Target Board Configuration  
19-3  
DEVELOPMENT TOOLS  
S3C9664/P9664 (Preliminary Spec)  
Table 19-1. Power Selection Settings for TB9664  
Operating Mode  
'To User_Vcc' Settings  
Comments  
SMDS2/SMDS2+ supplies  
VCC to the target board  
To User_VCC  
Target  
System  
TB9664  
Off  
On  
V
CC  
(evaluation chip) and the  
target system.  
V
SS  
V
CC  
SMDS2/SMDS2+  
SMDS2/SMDS2+ supplies  
VCC only to the target board  
To User_VCC  
External  
VCC  
TB9664  
Target  
System  
Off  
On  
(evaluation chip). The target  
system must have a power  
supply of its own.  
VSS  
VCC  
SMDS2+  
SMDS2+ Selection (SAM8)  
In order to write data into program memory available in SMDS2+, the target board should be selected for  
SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.  
Table 19-2. The SMDS2+ Tool Selection Setting  
'SW1' Setting  
Operating Mode  
R/W*  
SMDS2+  
R/W*  
Target  
Board  
SMDS2  
SMDS2+  
19-4  
S3C9664/P9664 (Preliminary Spec)  
DEVELOPMENT TOOLS  
Table 19-3. Using Single Header Pins as the Input Path for External Trigger Sources  
Target Board Part  
Comments  
Connector from  
External Trigger  
Sources of the  
Application System  
External  
Triggers  
CH1  
CH2  
You can connect an external trigger source to one of the two external  
trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace  
functions.  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDD  
VSS  
XOUT  
1
2
3
4
5
6
7
8
D-/P2.0/INT2  
D+/P2.1/INT2  
P1.0/AD0/INT1  
P1.1/AD1/INT1  
P1.2/AD2/INT1  
P1.3/AD3/INT1  
P1.4/AD4/INT1  
P1.5/AD5/INT1  
P0.5/INT0  
X
IN  
TEST  
P0.0/INT0/T0 (CAP/PWM)  
P0.1/INT0  
RESET  
P0.2/INT0  
P0.3/INT0  
9
P0.4/INT0  
10  
11  
12  
P1.6/INT1 (note)  
P1.7/INT1 (note)  
(note)P0.6/INT0  
(note)P0.7/INT0  
NOTE: 20 and 24 SOP/(S)DIP  
Figure 19-3. 24-Pin Socket for TB9664  
19-5  
DEVELOPMENT TOOLS  
S3C9664/P9664 (Preliminary Spec)  
Target Board  
J101  
Target System  
1
20  
1
20  
Part Name: AS20P  
Order Code: SM6304  
10 11  
10  
11  
Figure 19-4. TB9664 Adapter Cable for 20-SOP/DIP Package  
Target Board  
J101  
Target System  
1
24  
1
24  
Part Name: AP24SB-A  
Order Code: SM6531  
12 13  
12  
13  
Figure 19-5. TB9664 Adapter Cable for 24-SOP/SDIP Package  
19-6  

相关型号:

S3C9664XX-DK

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDIP20, 0.300 INCH, DIP-20
SAMSUNG

S3C9664XX-SK

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDSO20, 0.300 INCH, SOP-20
SAMSUNG

S3C9664XX-SM

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDSO24, 0.300 INCH, SOP-24
SAMSUNG

S3C9674XX-AQ

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDIP42, 0.600 INCH, SDIP-42
SAMSUNG

S3C9678XX-AQ

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PDIP42, 0.600 INCH, SDIP-42
SAMSUNG

S3C9678XX-QZ

Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44
SAMSUNG

S3C9688

8-bit single-chip CMOS microcontrollers
SAMSUNG

S3CB

SURFACE MOUNT GENERAL RECTIFIER
DIOTECH

S3CB018

The S3CB018/FB018 single-chip CMOS microcontroller
SAMSUNG

S3CB018XX-AV

RISC Microcontroller, 8-Bit, MROM, 20MHz, CMOS, PDIP30, 0.400 INCH, SDIP-30
SAMSUNG

S3CB018XX-SO

RISC Microcontroller, 8-Bit, MROM, 20MHz, CMOS, PDSO32, 0.450 INCH, SOP-32
SAMSUNG

S3CB205

S3CB205/FB205
SAMSUNG