S1T8527C01-Q0R0_技术文档

1 CHIP CLP SUBSYSTEM IC

INTRODUCTION

S1T8527C

48- QFP- 1010E

S1T8527C is a monolithic circuit which can be used in high

performance 60MHz MCA type CLP System. The S1T8527C is a

subsystem IC for FM / FSK receiving systems and a complete one chip

FM / FSK receiver IC for 60MHz system. It’s feature includes receiving

functions for FM / FSK systems, a compander to remove external

noise, and PLL ( Phase Lock Loop ) of channel selection which blocks

surrounding frequency interference.

The S1T8527C can be used with a wide range of FM / FSK VHF

bandwidth systems, including cordless phone, and the narrow band

voice and data sending / receiving systems.

To make applications easily and simply, peripheral parts are minimized.

FEATURES

•

Operating voltage range: 2.0V — 5.5V

Typical supply current: 13.5mA at 3.6V

Built- in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V )

Built- in speaker amplifier

Built- in splatter filter

Built- in dual conversion receiver, compander and universal PLL

FM Receiver

— Complete dual conversion circuit

— Excellent input sensitivity (0.7mVrms at 12dB SINAD)

Compader

•

— Easy gain control to use external component

— Included ALC (Automatic Level Control) circuit

— Included Mute logic

Universal PLL

— RX (TX) divided counter range: 1/16 — 1/16383

— Reference frequency divided counter range: 1/16 — 1/4095

— Lock detector signal output

— Serial interface with MCU for controlling each block

ORDERING INFORMATION

Device

Package

48- QFP- 1010E

Operating Temperature

S1T8527C01-Q0R0

- 20°C — + 70°C

1

S1T8527C

1 CHIP CLP SUBSYSTEM IC

BLOCK DIAGRAM

32

31

28

27

35

29

36

34

33

30

26

25

FSK

COMP

X-tal

OSC

Limiting

IF AMP

Regulator

(1V)

V_REF

(COMP)

24

VREF

2MI

37

23 ALC

2nd

MIX

IF AMP

(455KHz)

PRI

Meter

Driver

+

-

22

1MO

1LOI

EPI

38

39

40

RX

VCO

Quad

Detector

Rectifier

21

20

ERC

EO

Carrier

Detector

SUM

AMP

VCO

RX

41

SPK

AMP

1st

MIX

IF AMP

(10.7MHz)

Low

Battery

Detector

Gain Cell

SAI

19

18

17

16

SAO1

SAO2

42

43

44

45

46

47

48

1MI

SPK

AMP

Regulator

( 2.15 V )

VCC

(COMP)

Buffer

+

SUM

AMP

Limiter

GND

(PLL)

-

GND

(COMP)

15

Programmable Counter

( RX )

PRI

PDR

CPI+

CPI -

14

13

Gain Cell

V_REF

(PLL)

Programmable Counter

( TX )

ALC

V_CC

(PLL)

Programmable Counter

( REF )

4_25 CNT

Rectifier

TIF

Splatter

Filter

RX Phase

Detector

TX Phase

Detector

Compandor

mute

fMCU

CONTROL

1

2

3

4

5

6

7

8

9

10

11

12

2

1 CHIP CLP SUBSYSTEM IC

PIN CONFIGURATION

S1T8527C

32 31

28

27

35

29

25

36

34 33

30

26

37

24

23

V_REF(COMP)

ALC

2MI

38

1MO

39

40

41

42

43

44

22 EPI

21 ERC

20 EO

1LOI

VCO_RX

1MI

19 SAI

18 SAO1

S1T8527C

KB8527B

1MI

GND_(PLL)

PDR

SAO2

17

45

46

16

15

VCC_(COMP)

GND_(COMP)

CPI+

V_REF(PLL)

47

14

13

V_CC(PLL)

CPI -

TIF 48

4

5

6

9

2

8

10

12

1

3

7

11

3

S1T8527C

1 CHIP CLP SUBSYSTEM IC

PIN DESCRIPTION

Pin No

Symbol

Description

1

PDT3

Phase detector output terminal of the transmitter at PLL.

If f > f

or f is leading ® the output is negative pulse

TX

REF

TX

If f < f

or f is lagging ® the output is positive Pulse

TX

if f = f

and the same phase ® the output is High Impedance

TX

2

CO

Compressor output terminal of compander; connected to the splatter filter amp input

terminal.

3

4

5

SFI

Input terminal of Splatter filter amp.

Output terminal of Splatter filter amp.

SFO3

LDT/CDO LDT: Output terminal of transmitter lock detector in PLL block. The output is low if PLL

is in lock state and the output is high if PLL is in unlock state.

CDO: As an output terminal of the carrier detector buffer, connected to (RSSI )

terminal of MCU. This pin outputs the contents of Meter Driver buffer which is

turned on / off, according to the signal level detected by Meter Driver.

6

GND

Ground.

PLL

Ground of logic section at PLL.

7

8

9

CLK

DATA

EN

These pins are serial interface terminals for programming reference counter, auxiliary

reference counter, TX channel counter, RX channel counter and control block that

controls internal each block with test mode and power saving mode.

10

LBD

Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During

the normal operation, output level is low, but it is high at low battery detection. As this

pin is an open collector type, it requires a pull - up resistor.

11

AGIC

This pin bypasses AC elements at the feedback loop which come from the SUM amp

block of COMPRESSOR. A capacitor should be connected between this terminal and

GND. ( C = 2.2uF )

12

13

14

CRC

CPI -

CPI +

Converts waveform from the full wave rectifier to DC element at the rectifier block of

Compressor. ( RC = 33msec )

Pre-amp inverting input terminal of Compressor.

Adjusts the negative feedback loop gain. ( in application, gain is 5 )

Pre-amp non-inverting input terminal of Compressor.

Used as an input terminal for voice signals.

15

16

GND

Ground of Compander block.

(COMP)

Vcc

Supply voltage.

(COMP)

Power supply terminal of Compander.

17

SAO 2

Output terminal of speaker amp 2.

This signal is the same as SAO1 output, but phase difference is180° for SAO1.

DC voltage level is ( Vcc — 0.7V ) / 2.

4

1 CHIP CLP SUBSYSTEM IC

S1T8527C

PIN DESCRIPTION (Continued)

Pin No

Symbol

Description

18

SAO 1

Output terminal of Speaker amp 1.

DC voltage level is ( Vcc — 0.7V ) / 2.

19

SAI

Speaker Amp 1 input terminal.

Between this terminal and Expander output terminal, uses a AC coupled.

20

21

EO

Output terminal of Expander, from which a regenerated voice signals are emitted.

ERC

Converts waveform from the full wave rectifier to DC element at the rectifier block of

Expander. ( RC = 33 msec )

22

23

EPI -

Pre-amp inverting input terminal of Expander.

Adjusts the negative feedback loop gain. ( in application, gain is 5 ).

ALC

Reference current input terminal of Automatic Level Control ( ALC); Adjusts THD of

compressor output voltage to less than 3% or limits the frequency deviation of TX if the

input is higher than a certain level. The ALC circuit may be turned off depending on the

ALC reference current or the magnitude of output voltage may be limited if it is higher

than a certain level.

24

25

V

Reference voltage ( V

Expander of COMPANDER.

= 1V ). Supplies a regulator voltage to the Compressor and

REF

REF(COMP)

MDO

Output terminal of the Meter Driver.

Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit.

The Meter Driver circuit has perfect linear characteristic of 60dB range for input signal

level. ( 0.1mA / dB ).

26

DSCO

Output terminal of Data Slicing comparator.

Separates Frequency Shift Keying ( FSK ) serial data and executes data shaping and

limiting.

27

28

29

DSCI

RAO

QCI3

Input terminal of Data slicing comparator.

Non-inverting type with the negative input terminal biased to 1/2 Vcc.

Recovered Audio Output terminal. Voice signals detected by the Quadrature Detector

are amplified and then output through this terminal.

Quadrature coil input terminal.

The 455kHz oscillator circuit is an Lp = 680uH, Cp = 180pF valued LC tank circuit.

Voice signals are detected by mixture of 455kHz ( by phase difference ) which is

converted from mixer 2.

30

GND

Ground .

RX

Ground for Receiver.

31

32

LD

LI

Limiter input and decoupling terminal.

Removes amplitude modulation elements caused by fading or FM signal noise. Limiting

IF amplifies and limits the second intermediate frequency, 455kHz.The input

impedance of the limiting IF amplifier is set to 1.5kW. While FM waves are transmitted

with constant magnitude, their magnitudes are slightly modulated due to reflection from

obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before

entering the receiver’s antenna.The limiter makes amplitude uniform by removing these

AM wave elements.

5

S1T8527C

1 CHIP CLP SUBSYSTEM IC

PIN DESCRIPTION (Continued)

Pin No

Symbol

Description

33

V

Supply voltage.

CC(RX)

Supplies power to the Receiver.

34

2MO3

Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by

mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output.

35

36

2LOI

Input terminal of second local oscillator. Generates second local oscillator frequency to

convert output from mixer 1 ( 10.7MHz ) into second intermediate frequency. It is an

oscillator with crystal of 10.24MHz and 10.245MHz.

37

38

2MI

Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via

10.7MHz ceramic filter. Second mixer converts frequency to second intermediate

frequency ( 455kHz: AM IF ).

1MO3

Output terminal of mixer 1.

The signal from mixer 1 and the frequency of the first local oscillator are mixed to

produce the first intermediate frequency, which is the output through this terminal. The

output terminal is an emitter follower with an output impedance of 330W to match the

330W input/output impedance of the 10.7MHz ceramic filter.

39

40

1LOI

Input terminal of the first local oscillator.

The local oscillator is a voltage controlled oscillator. local oscillation frequency and

received frequency are mixed at mixer 1 and then converted to the first intermediate

frequency of 10.7MHz or 10.695MHz.

41

VCO

The terminal which variable capacitor is included in the chip. Used as an input terminal

where 1st local oscillation frequency is changed by varying the capacitor connected

between 1st local oscillator terminals.The internal variable capacitor has the value of

18.73 ~ 15.86pF depending on the applied voltage. ( 1.0 ~ 2.0 V ).

RX

42

43

1MI

Input terminal of Mixer 1. This mixer is made of double balanced multiplier.

The received signal amplified at RF AMP is input to this terminal.

44

GND

Ground.

(PLL)

Ground for analog at PLL

45

PDR

Phase detector output terminal of the receiver at PLL.

If f > f

or f is Leading ® The output is negative pulse

RX

REF

RX

If f < f

or f is Lagging ® The output is positive pulse

RX

If f = f

and the same phase ® The output is high impedance

RX

46

V

PLL voltage reference output pin.

REF(PLL)

An internal voltage regulator provides a stable power supply voltage for the RX and TX

PLLs.

47

48

V

Power supply terminal of PLL.

CC(PLL)

TIF

Input terminal of TX channel counter.

AC coupling with TX VCO.

Minimum input level is 300mVp-p ( at 60MHz ).

6

1 CHIP CLP SUBSYSTEM IC

S1T8527C

ABSOLUTE MAXIMUM RATINGS

Characteristic

Maximum Supply Voltage

Power Dissipation

Symbol

Value

5.5

Unit

V

mW

°C

CC

P

600

D

Operating Temperature

Storage Temperature

T

- 20 — + 70

- 55 — + 150

OPR

STG

°C

CURRENT CONSUMPTION AT EACH MODE ( VCC = 3.6V )

MODES

Min.

Typ.

350uA

6.6mA

13.5mA

Max.

Inactive mode

RX mode

-

600uA

-

Communication mode ( Active mode )

CURRENT CONSUMPTION IN EACH BLOCK ( VCC = 3.6V )

MODES

Min.

Typ.

Max.

Receiver part

Expander part

Speaker part

-

5.0mA

1.4mA

1.7mA

3.0mA

1.6mA

0.8mA

7.5mA

2.1mA

2.5mA

4.5mA

2.4mA

1.2mA

compressor part

PLL

RX part

TX part

7

S1T8527C

1 CHIP CLP SUBSYSTEM IC

ELECTRICAL CHARACTERISTICS

Characteristic

Operating Voltage

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Vcc

-

2.0

-

5.5

V

RECEIVER

( V = 3.6V, f = 49.7MHz, f

= ± 3kHz, f = 1kHz,Ta = 25°C, unless otherwise specified )

MOD

CC

C

DEV

Input for - 3dB Sensitivity

Input for 20dB Sensitivity

S/N Ratio

V

- 3dB Point

-

0.7

55

2.0

-

mVrms

dB

LIM

V

Modulation Input

-

I(SEN)

S/N

Modulation Input

48

No Modulation Input

Recovered Audio Output

Noise Output Level

V

RFin = 1mVrms

RFin = No Input

145

-

185

130

- 3.3

225

205

-

mVrms

dB

O(RA)

V

NO

Recovered Audio Output

Voltage Drop

V

Vcc = 5V ® 2V

RFin = 1mVrms

- 8

O(RAD)

Detect Output Voltage

V

RFin = 1mVrms

RFin = No Input

1.0

0.49

70

1.5

0.60

110

2.0

0.73

150

V

O(DET)

Carrier Detector Threshold

V

TH(DET)

Comparator Threshold

Voltage Difference

DV

V

= 150mVp-p

COMP

mV

TH

R = 180kW

L

Comparator Output Voltage 1

V

= 150mVp-p

COMP

2.7

-

3.0

0.25

18

-

V

OH

RL = 180kW

Comparator Output Voltage 2

V

= 150mVp-p

0.5

22

25

OL

COMP

R = 180kW

L

First Mixer Conversion

Voltage Gain

DG

V

R

= 1mVrms

I(43)

14

17

dB

V(1M)

V(2M)

= 330W

L(38)

Second Mixer Conversion

Voltage Gain

DG

V

R

= 1mVrms

21

I(37)

= 1.5kW

L(34)

Detector Output Distortion

Detector Output Resistance

THD

RFin = 1mVrms

-

1.5

1.2

2.5

-

%

DET

R

kW

O(DET)

Detector Output DC Voltage

Change Ratio

DV

0.15

0.23

V/kHz

O(DET)

Meter Drive Slope

MDS

70

100

690

7.2

100

10

135

-

nA/dB

W

First Mixer Input Resistance

First Mixer Input Capacitance

Limiter Input Sensitivity

R

fc = 50MHz

500

I(1M)

I(LIM)

V(2M)

C

fc = 50MHz

-

10

250

25

pF

V

S

fc = 455kHz, 20dB SINAD

fc = 10.7MHz, 20dB SINAD

mVrms

Second Mixer Input

Sensitivity

8

1 CHIP CLP SUBSYSTEM IC

S1T8527C

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

First Mixer 3rd Order

Sensitivity

3RD

-

-22

-

dBm

Low Battery Detector

LBD3

LBD0— LBD3 = 0 ( Default ) - 0.15

Only LBD2 = 0

Only LBD1 = 0

3.45

3.3

0.1

V

3.0

Only LBD3 = 0

LBD0 — LBD3 = 1

- 0.1

2.2

2.1

0.075

AM Rejection Ratio

AMRR

RFin = 1mVrms — 10mVrms

AM MOD = 30%

25

-

dB

Compressor

( Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified )

Reference Voltage

V

No Signal

0.9

1.0

1.1

V

REF

Standard Output Voltage

Vo(com)

Vinc = 13mVrms ( 0dB ),

Ralc = GND

255

300

345

mVrms

Compressor Gain Difference

DGV1

DGV2

THD

Vinc=1.3mVrms (- 20dB),

DGv1 (COM) = 20 ´ log

(Voc1/Voc) + 10K

- 1.0

- 2.0

- 0.5

- 1.0

-

dB

(COM)

Vinc = 0.13mVrms (- 40dB)

DGv2 (COM) = 20 ´ log

(Voc2/Voc) + 20K

Compressor Output Distortion

Mute Attenuation Ratio

Vinc = 0dB

-

0.5

80

1.0

-

%

dB

COM

MUTE

ATT

Vinc = 0dB

60

Compressor Limiting

Voltaget

V

Vinc = Variable

1.41

1.65

1.83

Vp-p

LIM(COM)

ALC

V

I

= 8uA ( R = 120kW )

ALC

280

255

330

300

380

345

mVrms

ALC

Splatter filter

Vo(SF)

VINC = 13mVrms = 0dB

Expander

(Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified)

Standard Output Voltage Vine=30mVrms ( 0dB )

V

104

130

156

mVrms

O(EXP)

9

S1T8527C

1 CHIP CLP SUBSYSTEM IC

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Expander Gain Difference

DG

Vine = 9.5mVrms (- 10dB)

DGv1(EXP) = 20 ´ log (Voe1/

Voe) + 20

0

0.5

1.0

dB

V1(EXP)

V2(EXP)

V3(EXP)

DG

Vine = 3mVrms (- 20dB)

DGv2 (EXP) = 20 ´ log

(Voe2/Voe) + 40T

0

1.0

1.5

2.0

3.0

dB

Vine = 0.95mVrms (- 30dB)

DGv3 (EXP) = 20 ´ log

(Voe3/Voe) + 60K

Expander Output Distortion

Mute Attenuation Ratio

THDEXP VinE = 0dB

ATTMUTE VinE = 0dB

-

0.5

80

1.0

%

dB

60

-

Expander Maximum Output

Voltage

V

VinE = Variable

500

600

mVrms

OEXP(MAX)

THD = 10%l

Speaker amp output 1

Speaker amp output 2

Vo( SA1) VINE = 30mVrms = 0 dB

104

130

156

mVrms

PLL

( Vcc = 3.6V, Ta = 25°C, unless otherwise specified )

Operating Current

Input Current

I

Vcc = 3.6V

Vin = Vcc

Vin = 0V

-

2.0

3.5

mA

V

CCPLL

I

-

- 5

-

5

IH

I

-

IL

Input Voltage

Output Current

Output Voltage

V

-

Vcc-0.3

-

IH

V

0.3

V

IL

I

Vout = Vcc

Vout = 0V

0.3

-

mA

V

OH

I

0.3

OL

V

PDT, PDR: Io = - 0.3mA

Vcc-0.4

OH1

( Sourcing )

V

PDT, PDR: Io = 0.3mA

( Sinking )

-

Vcc-0.5

-

0.4

-

V

OL1

OH2

V

LD, fMCU: Io = - 0.1mA

( Sourcing )

-

V

LD, fMCU: Io = 0.1mA

( Sinking )

0.5

2.25

OL2

PLL regulator voltage

V

1.95

2.15

PLLREG

10

1 CHIP CLP SUBSYSTEM IC

S1T8527C

PLL PROGRAM SUMMARY

MCU ( MICOM ) SERIAL INTERFACE ( MSB : 1ST INPUT )

Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program. DATA and CLK terminals are used for loading

data to internal Shift - Register. When EN terminal is ‘Low’ It is possible to program TX-Channel Counter, RX -

Channel Counter and various control functions of PLL. When EN terminal is ‘High’ Program 1st Local Oscillator

Capacitor Selection in receiver for U.S.A - 25 CH function.

— TX - Register, RX-Register, Control Register

MSB

LSB

DATA

PMC0

PMC1

14 Bit DATA

EN

CLK

— Reference - Register

MSB

LSB

DATA

PMC0

PMC1

UK_S1

UK_S0

12 Bit DATA

EN

CLK

— RECEIVER -1st local oscillator internal capacitor selection register & low battery detector voltage register

[ CLO_LBD-Register ]

MSB

LSB

DATA

PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0

<1>

EN

CLK

11

S1T8527C

1 CHIP CLP SUBSYSTEM IC

•

Programmable Counter

— RX - counter: Setting frequency for RX.VCO ( 14 Bits --> 1/16 — 1/16383 )

[ Default_CH. = USA_#21 ( REMOTE ): 36.075MHz ( Div._NO = 7215 )]c

< RX. Register (16bits) >

Bit

Bit 15

Bit 14

Bit 13

D13

0

Bit 12

D12

1

Bit 11

D11

1

Bit 10

D10

1

Bit 9

D9

0

Bit 8

D8

0

Name

PMC0

PMC1

Default

value

7215

*

Bit

Bit 7

D7

0

Bit 6

D6

0

Bit 5

D5

1

Bit 4

D4

0

Bit 3

D3

1

Bit 2

D2

1

Bit 1

D1

1

Bit 0

D0

1

Name

Default

value

7215

— TX - counter: Setting frequency for TX.VCO ( 14 Bits --> 1/16 — 1/16383 )

[ Default_CH. = USA_#21 ( REMOTE ): 49.830MHz ( Div._NO = 9966 )]'

< TX. Register (16 bits) >

Bit

Bit 15

Bit 14

Bit 13

D13

0

Bit 12

D12

1

Bit 11

D11

1

Bit 10

D10

1

Bit 9

D9

0

Bit 8

D8

0

Name

PMC0

PMC1

Default

value

9966

*

Bit

Bit 7

D7

1

Bit 6

D6

1

Bit 5

D5

1

Bit 4

D4

0

Bit 3

D3

1

Bit 2

D2

1

Bit 1

D1

1

Bit 0

D0

0

Name

Default

value

9966

* Program mode control

PMC0

PMC1

Program mode

Control Block

PMC0

PMC1

Program mode

UPLL_RX. Block

UPLL_TX. Block

0

1

0

1

UPLL_Ref. Block

12

1 CHIP CLP SUBSYSTEM IC

S1T8527C

— Ref - counter: Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 )

[ Default_Divider = 2048, X-tal_OSC = 10.240 MHz --> Fref = 5kHz ]

< Ref. Register (16bits) >

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

D11

1

Bit 10

D10

0

Bit 9

D9

0

Bit 8

D8

0

Name

PMC0

PMC1

UK_S1

UK_S0

Default

value

2048

*

Ref.freq. selection

for United KingdomD

Bit

Bit 7

D7

0

Bit 6

D6

0

Bit 5

D5

0

Bit 4

D4

0

Bit 3

D3

0

Bit 2

D2

0

Bit 1

D1

0

Bit 0

D0

0

Name

Default

value

2048

— UK_Selection

UK_S0

UK_S1

FR1

FR2

FrefTX

fREF (A)

FrefRX

0

1

0

1

0

1

fREF (A)

fREF/4 (B)

-

fREF (A)

fREF/4 (B)

fREF/25 (C)

fREF/4 (B)

fREF/25 (C)

fREF/4 (B)

fREF/25 (C)

fREF

(A)

LD

FR1

FR2

fREF ¸ 4

12 Bits Reference

program divider.

¸ 4

PD_TX

(B)

fREF ¸ 25

¸ 25

PDT

PDR

(C)

PD_RX

Figure 1. < Reference frequency selection >

13

S1T8527C

1 CHIP CLP SUBSYSTEM IC

•

Control program

— Control register (16 Bits)

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Name

PMC0

-

PLL -BS

CO_M

CO_BS

EX_BS

TX

Description Program

Mode

Program

Mode

Don’t

Care

PLL_Tx

Battery

Save

Compress Compress Expander Expander

or Mute

or Battery

Save

Mute

Battery

Save

Control_0 Control_1

Selection

Function

*

Don’t

0:Normal

1:Mute

0: CO-On

1: Normal

( CO-part

Power-Off )

0:Normal

1:Mute

0: EX-On

1: Normal

( EX-part

Power-Off )

Program Latch Assign Care

(PLL_TX-On)

1:PLL_TX

Power-Off

Bit

Bit 7

LDT_

Bit 6

Bit 5

Rx-Bs

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

LBD-BS

TEST2

TEST1

-

CDO

Description LDT or

Low

RX Battery

Save

Don’t

care

Don’t

care

Don’t

care

TEST

Mode 2

TEST

Mode 1

CDO

Select

Battery

Detector

Battery

Save

Function

LDT or

CDO

0:Normal

(LBD-ON)

0:Normal

(RX-ON)

* * *

Function Test On

-

Select

1:LBD-Part 1:RX-Part

Power-Off Power-Offf

each block of UPLL

*** TEST Mode & LDT-CDO Mode

LDT/CDO

TEST1

TEST2

LDT / CDO

Remark

0

1

0

1

0

1

0

1

0

1

0

1

Rx block CDO

4_25cnt block FR2

PLL block LDT

Test PLL_TX

Default

1

14

1 CHIP CLP SUBSYSTEM IC

S1T8527C

•

Operating internal circuit blocks in each mode

Mode ( state )

Operating circuit blocks

Active state

( Communication mode )

PLL regulator/MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver /

1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery

detector / TX PLL / Expander & speaker amp / Compressor / Splatter filter

amp

Receiving mode

Inactive state

PLL regulator / MICOM I/F ( Data, CLK, EN )/ 2nd local oscillator / Receiver /

1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery

detector.

PLL regulator / MICOM I/F( Data, CLK, EN )

•

CLO_LBD - Register Program

[ Rx - 1’st local oscillation internal cap. for U.S.A - 25CH & Alarm sensor detect voltage ]

— CLO register ( 6 bits ) : Receiver 1’st local oscillator internal capacitor selection

Bit

Bit10 (MSB)

Bit 5

CLO5

0

Bit 4

CLO4

0

Bit 3

CLO3

0

Bit 2

CLO2

0

Bit 1

CLO1

0

Bit 0

CLO0

0

Name

PMC

Default

Value 0

1

* * * * *

Function

-

0:Normal

1:Internal

Cap. for

USA 25

0:Normal

1:Internal

Cap. for

USA 25

0:Normal

1:Internal

Cap. for

USA 25

0:Normal

1:Internal

Cap. for

USA 25

0:Normal

1:Internal

Cap. for

USA 25

0:Normal

1:Internal

Cap. for

USA 25

Channel = Channel = Channel = Channel = Channel = Channel =

4.4pF

1.0pF

3.6pF

2.4pF

1.2pF

0.6pF

*****PMC ( Program Mode Control )

PMC = ‘HIGH’ & EN = ‘HIGH’ ---> CLO_LBD Register Program Modeap

— Rx - Low Battery Detect Voltage

Bit

Bit 10(MSB)

PMC

Bit 9

LBD3

0

Bit 8

LBD2

0

Bit 7

LBD1

0

Bit 6

LBD0

0

Low Battery

Detector Voltagef

Remark

Name

Default

Value

1* * * * *

-

Default

Function

1

0

1

0

1

0

1

0

1

0

1

0

1

3.45V

3.3V

3.0V

2.2V

2.1V

-

15

S1T8527C

1 CHIP CLP SUBSYSTEM IC

***** PMC ( Program Mode Control )

PMC = ‘HIGH’ & EN = ‘HIGH’ ---> CLO - LBD Register Program Mode

·

Example 1 >

Low battery detector voltage : 2.1V

U.S.A_CH-#1(REMOTE)--->1st local osc. varicap value =15.86pF, Internal cap=7.0pF

( Ext_L = 0.45uH, EXT_C = 30pF )

— 12 bit data format

MSB

PMC

LSB

Dummy

bit

LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0

1

1( 0 )

1

0

1

0

DATA

EN

CLK

In case the 12 bits programming, insert 1 don’t care bit ( Dummy bit ) between PMC and LBD3.

— In case of setting 16 bit data format

MSB

PMC

LSB

LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0

Dummy

bit

1

0

1

0

DATA

1( 0 ) 1( 0 ) 1( 0 ) 1( 0 ) 1( 0 )

EN

CLK

In case of 16 bits programming, insert 5 don’t care bits between the PMC and LBD3

16

1 CHIP CLP SUBSYSTEM IC

S1T8527C

EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION

1’st Local Osc. Internal Capacitor Select

Base

Hand

Varicap

Value

External External

Internal

C

Channels Channels

C

L

1.0V— 2.0V

TYP 1.5Vo

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

1 —

25CH.

1 —

25CH.

27pF

( 30pF )

0.45uH

pF

(CLO5) (CLO4 (CLO3) (CLO2) (CLO1) (CLO0)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

16 —

25CH.

18.73

— 15.86pF

18.73

27pF

30pF

27pF

30pF

0.45uH

-

16 —

25CH.

0.6

1.6

1.2

0.6

7.0

5.8

—

15.86pF

18.73

01 —

04CH.

— 15.86pF

18.73

05 —

10CH.

—

15.86pF

18.73

15.86pF

11 —

15CH

18.73

15.86pF

01 —

06CH.

18.73

15.86pF

07 —

15CH.

•

Phase detector / Lock Detector Output Waveforms

fREF

LD

FR1

(A)

fREF ¸ 4

12 Bits Reference

program divider.

REF.Freq

¸ 4

FR2

PD_TX

(B)

2LOI

TIF ¸ N

fREF ¸ 25

¸ 25

(C)

PDT

14 Bits TX.

program divider.

TIF

17

S1T8527C

1 CHIP CLP SUBSYSTEM IC

REF.Freq.

TIF ¸ N

PDT

LD

Figure 2. ( Phase Detector / Lock Detector Output Waveform )

18

1 CHIP CLP SUBSYSTEM IC

S1T8527C

APPLICATION CIRCUIT (BASE SET)

C D O

D S C O

C R C

A G I C

L B D

D S C I

R A O

E N

Q C I

D A T A

C L K

( R X ) G N D

1 0 N

C 4 3

( P L L )

L D

L I

G N D

C D O / L D T

S F O

S F I

( R X )

V C C

2 M O

2 L O I

2 L D I

C O

P D T

19

S1T8527C

1 CHIP CLP SUBSYSTEM IC

APPLICATION CIRCUIT (HAND SET)

C D O

D S C O

C R C

A G I C

D S C I

R A O

L B D

E N

Q C I

D A T A

C L K

( R X ) G N D

1 0 N

C 4 3

L D

L I

( P L L ) G N D

C D O / L D T

( R X ) V C C

2 M O

S F O

S F I

2 L O I

C O

2 L D I

P D T

20


型号：	S1T8527C01-Q0R0
厂家：	SAMSUNG
描述：	1 CHIP CLP SUBSYSTEM IC 1芯片CLP子系统IC
文件：	总20页 (文件大小：188K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

S1T8527C01-Q0R0 [SAMSUNG]

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