S1T8531 [SAMSUNG]
WIDEBAND FM/FSK IF RECEIVER; WIDEBAND FM / FSK接收器IF
| 型号： | S1T8531 |
| 厂家： | 
SAMSUNG |
| 描述： | WIDEBAND FM/FSK IF RECEIVER |
| 文件： | 总10页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WIDEBAND FM/FSK IF RECEIVER
INTRODUCTION
S1T8531
16-SOP-225
The S1T8531 is a wideband FM / FSK receiver designed for
wideband FSK data and analog FM applications.
It is fabricated using Samsung’s ASP5HB 0.5um advanced BiCMOS
process. The S1T8531 contains high gain IF amplifier with received
signal strength indicator (RSSI), a wideband FM quadrature
demodulator, a baseband filter amplifier and a high speed data slicer
with sample & hold function.
The IF amplifier has 100dB small signal gain and 2MHz through
40MHz bandwidth. The wideband FM quadrature demodulator has
demodulation bandwidth greater than 1MHz.
The baseband filter amplifier is a wideband buffer and it can be
configured as a second-order sallen-key low pass filter. The data slicer is a comparator that is designed to square
up the data signal with data rates up to 2Mbps.
FEATURES
•
•
•
•
•
•
•
Operating voltage range
Typical supply current
: 2.2 to 5.5V
: 5.5mA at 3.6V
Operating frequency range : 2MHz to 40MHz
High Gain (100dB) and Wideband (2MHz to 40MHz) IF Amplifier
Quadrature Demodulator with Greater than 1MHz Bandwidth
High Speed Data Slicer Operating Upto 2Mbps with Sample & Hold
RSSI Dynmic range : Typ : 60dB
APPLICATION
•
Wideband FM / FSK Wireless Communication Systems
ORDERING INFORMATION
Device
Package
16-SOP-225
Operating Temperature
+S1T8531X01-S0B0
- 10°C to + 70°C
+ : New Product
1
S1T8531
WIDEBAND FM/FSK IF RECEIVER
BLOCK DIAGRAM
IFIN
16
IFIP GND2 SHEN RSSI
DSO SHO
DSIN
9
15
14
13
12
11
10
Sample
Hold
A
RSSI
5pF
1
1
6
2
3
4
5
7
8
GND1 VCC1 QIN
VCC2 QOUT BIN
BOUT DSIP
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
VCC1
QIN
IFIN
IFIP
GND2
SHEN
RSSI
DSO
SHO
DSIN
VCC2
QOUT
BIN
S1T8531
BOUT
DSIP
2
WIDEBAND FM/FSK IF RECEIVER
PIN DESCRIPTION
S1T8531
Pin
1
Name
GND1
VCC1
QIN
Schematic
Description
Ground. (Pin1 and Pin14 are connected internally)
Supply. (Pin2 and Pin4 are connected internally)
Quadrature demodulator tank input.
2
3
VCC
3
4
5
VCC2
QOUT
Supply. (Pin2 and Pin4 are connected internally)
Quadrature demodulator output.
VCC
5
6
7
BIN
Baseband filter buffer amplifier input.
Baseband filter buffer amplifier output.
BOUT
VCC
6
7
8
9
DSIP
DSIN
Data slicer positive input.
Data slicer negative input.
VCC
8
9
3
S1T8531
WIDEBAND FM/FSK IF RECEIVER
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
Sample and hold output.
10
SHO
7
11
12
DSO
RSSI
Data slicer output.
VCC
11
RSSI output.
VCC
12
13
SHEN
Sample and hold enable input.
High signal input enable sample and hold function
and low signal input disable sample and hold
function .
VCC
13
14
GND2
Ground. (Pin1 and Pin14 are connected internally)
15
16
IFIP
IFIN
IF amplifier differential inputs.
DC blocking is required.
VCC
15
16
4
WIDEBAND FM/FSK IF RECEIVER
ABSOLUTE MAXIMUM RATINGS
S1T8531
Characteristic
Maximum Supply Voltage
Operating temperature
Storage Temperature
Symbol
VCC
Value
6
Unit
V
Ta
-10 to + 70
-55 to + 150
°C
°C
TSTG
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Voltage applied to any pin
Symbol
Value
Unit
V
VCC
VIN
2.2 to 5.5
- 0.3 to Vcc + 5.5
V
5
S1T8531
WIDEBAND FM/FSK IF RECEIVER
ELECTRICAL CHARACTERISTICS
( Vcc = 3.6V, IF = 10.7MHz, fdev = ± 75kHz, fmod = 10kHz,Ta = 25°C, IFin = -47dBm unless otherwise noted. )
Characteristic
Current consumption
Symbol
Icc
Test Condition
Min
-
Typ
5.5
10.7
-95
-
Max
7.0
40
-81
40
-
Unit
mA
-
-
-
-
-
-
-
-
-
-
IF Input Frequency
IFfreq
2
MHz
dBm
MHz
dB
20dB SINAD Sensitivity (Note 2)
IF Amplifire Bandwidth (Note 1)
VSEN
-
BWIF
2
IF Amplifier Voltage Gain (Note 1)
IF Amplifier Input Impedance (Note 1)
Quadrature Demodulator Output Voltage
Demodulator Bandwidth (Notes 1 and 2)
Baseband Filter Buffer Amplifier Bandwidth
∆G IF
95
-
101
1.5
150
1
RIIIF
-
kΩ
Vo(DEM)
BWDEM
BWAMP
DG AMP
100
0.6
1
200
-
mVrms
MHz
MHz
dB
2
-
Baseband Filter Buffer Amplifier Voltage
Gain
-3
0
+3
Data Slicer Maximum Operating Frequency
(Notes 1 and 2)
BWDS
-
1
2
-
Mbps
RSSI Dynamic Range
RSSI Output Level
RSSI
-
-
50
60
-
-
dB
V
Vo(RSSI)
0.5
2.0
NOTES:
1. Not 100% AC tested but guaranteed by design and characterization.
2. Measured result on evaluation board with proper impedance matching.
6
WIDEBAND FM/FSK IF RECEIVER
S1T8531
FUNCTIONAL DESCRIPTION
General
The S1T8531 is a wideband FM / FSK receiver designed for use in analog FM and digital FSK systems such as
900MHz / 2.4GHz ISM band analog / digital cordless phones and wideband data links with data rates up to 2Mbps.
It contains IF amplifier, quadrature detector, baseband filter amplifier and data slicer with sample and hold function.
IF Amplifier
The IF amplifier section is composed of seven differential stage with total gain of 100dB at 10.7MHz. The input
impedance at 10.7MHz is 1.5kΩ. For 10.7MHz ceramic filter applications, an external 430Ω resistor must be placed
between IFP(Pin15) and IFN(pin16) to provide the equivalent load impedance of 330Ω that is required by the filter.
Quadrature Demodulator
The quadrature demodulator requires tank circuit with loaded Q depending on detection bandwidth. Following
figure shows external components required for 10.7MHz operation.
QUAD IN QUAD OUT
3
5
47pF 4.255uH
Rdamp
VCC
Baseband Filter Buffer Amplifier3
Baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter.
Following figure shows the external components required.
Cutoff frequency = 1 / [2π*SQRT(R1R2C1C2)]
Quality factor = SQRT(R1R2C1C2) / (R1C2 + R2C2)
The component value of R1 should contain the quadrature detector output resistance.
C1
Vout
C2
R1
R2
Vin
6
7
BUF OUT
BUF IN
7
S1T8531
WIDEBAND FM/FSK IF RECEIVER
Data Slicer with Sample and Hold
The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the
baseband filter output can be DC coupled to the data slicer DS-INP(Pin 9). The S1T8531’s data slicer incorporates
an sample and hold used to derive the data slicer reference voltage by means of an external integration circuit. The
sample and hold is “ON“ during reception of the preamble data pattern, and is otherwise “OFF“ in TDD (Time
Division Duplex) system. The external integration circuit is formed by an RC low pass circuit placed between SHO
(Pin 10) and ground.
The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer
shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a
change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift
close to the threshold voltage, the time constant is longer.
‘The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the
settling time. When the sample and hold is “OFF“ the output (SHO) is in high impedance state with extremely low
leakage current.
‘Following figure shows the internal block diagram.
8
9
DS INP
DS INN
11
DS OUT
10
13
+1
SHO
SHEN
The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommeded that an
external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of
ground and supply currents in the S1T8531 which might desensitize the chip.
The data slicer can be used as a carrier detector also. Following figure shows application example. In this case,
sample and hold should be off.
8
9
11
12
RSSI
Carrier
Detect
Reference
Voltage
8
WIDEBAND FM/FSK IF RECEIVER
TEST CIRCUIT
S1T8531
Data
Output
VCC
RSSI
IF Input
1u
50
Ω
100n 100n
1n
1.8k
Ω
10n
10n
16
15
14
13
12
11
10
9
GND SHEN RSSI DSO SHO DSIN
IFP
IFN
S1T8531
VCC QIN VCC QOUT BIN BOUT DSIP
GND
1
2
3
4
5
6
7
8
68p
1n
39k
15k
Ω
Ω
100p
100n
20k
20k
Ω
Ω
VCC
Audio
Output
9
S1T8531
WIDEBAND FM/FSK IF RECEIVER
APPLICATION CIRCOUT
IF2
BNC
VCC
R14
0
Sample &hold diable
Sample &hold enable
R13
VCC2
0
C18
100n
C19
56p
R15
330
TP5
RSSI
1
T2
10.7MHz
R12
56K
C13
100n
TP4
DSOUT
VCC2
1
R11 10K
R10 1.8K
C17
10nF
C16
120p
R16
10K
C15
C14
10nF 10nF
1
C10 C11 C12
1u 3.3n 56p
C20
10n
16
15
14
13
12
11
10
9
GND2 SHEN RSSI DSO SHO DSIN
IFIP
IFN
S1T8531
DSIP
8
VCC1 QIN VCC2 QOUT BIN BOUT
GND1
1
2
3
4
5
6
7
GND
1
R8
51
TP2
BUFOUT
1
VCC1
POWER
R9
5.6K
*C7
68p
*C8
100p
C1
3.3n
C2
56p
AUDIOOUT
TP3
R7
39K
1
1
R1
51
VCC2
*C9
4.7n
L1
CX1 CX1 R2
R6
15K
Quad.
coil
TP1
QUADOUT
C3
3.3nF
C4
56p
C5
100n
C6
56p 51
R3
R5
20K
R4
20K
VCC
VCC1
1
POWER
VCC2
VCC
* Changable value for each application
* Quadrature Coil
C7
C8
C9
L1
360u 120p
2.7u 56p
CX1
CV1
R2
Analog
68p
100p
4.7n
Quad. coil
Ext. coil
N/A
7.5K
2.4K
Digital 100p 220p 820p
1-3p
10
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