S1T8825B [SAMSUNG]
1.3GHZ DUAL PLL; 1.3GHz的双PLL
| 型号： | S1T8825B |
| 厂家： | 
SAMSUNG |
| 描述： | 1.3GHZ DUAL PLL |
| 文件： | 总16页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.3GHZ DUAL PLL
INTRODUCTION
S1T8825B
16−TSSOP−0044
The S1T8825B is a high performance dual frequency synthesizer with
two integrated high frequency pre-scalers for RF operation up to 1.3
GHz.
The S1T8825B is composed of modulus pre-scalers providing 64 and
66, no dead-zone PFD, selectable charge pump current, selectable
power down mode circuits, lock detector output, and loop filter’s time
constant switch.
It is fabricated using the ASP5HB Bi-CMOS process and is available
16-TSSOP with surface mount plastic packaging. Serial data is trans-
ferred into the S1T8825B via three-wire interface (CK, DATA, EN).
FEATURES
•
•
•
Two systems for receiver and transmitter
Very low operating current consumption: Icc = Typ. 7.0mA @ 3.0V
Low operating power supply voltage : 2.2 to 5.5V ( 200MHz to 550MHz Operating )
2.7 to 3.6V ( 550MHz to 1.3GHz Operating )
•
•
•
•
•
•
Modulus pre-scaler: 64 / 66
No dead-zone PFD
Colpitts type local oscillation
Selectable charge pump current
Selectable power down mode
TSSOP 16-pin package (0.65 mm pitch)
ORDERING INFORMATION
Device
Package
Operating Temperature
+S1T8825B01-R0B0
16−TSSOP−0044
−30 °C to + 85 °C
+: New Product
APPLICATIONS
•
•
•
•
Cordless telephone systems
Portable wireless communications (PCS)
Wireless Local Area Networks (WLANs)
Other wireless communication systems
1
S1T8825B
1.3GHZ DUAL PLL
BLOCK DIAGRAM
Prescaler
1
32, 33
Prescaler
1
32, 33
Fin1
1
2
3
Pre_Amp 1/2
1/2 Pre_Amp 16 Fin2
15 VCC
Buffer
Buffer
VCC
2
2
Charge
Pump
Charge
Pump
CP1
14
CP2
Channel 1
Program-
able
Channel 2
Program-
able
Phase
Detector
Phase
Detector
GND 4
13 GND
12 SW
Divider
Divider
Lock
Detector
6
LD
CK
5
6
Switch
Local
OSC
11 OSCI
10 OSCO
Control
Circuit
Reference
Divider
DATA 7
1/2
Buffer
17
12
EN
8
9
BO
PIN CONFIGURATION
Fin1
1
2
3
4
16
15
14
13
12
11
10
9
Fin2
VCC
CP1
GND
LD
VCC
CP2
GND
SW
5
6
7
8
S1T8825B
OSCI
OSCO
BO
CK
DATA
EN
16TSSOP
2
1.3GHZ DUAL PLL
S1T8825B
PIN DESCRIPTION
Pin No. Symbol I/O
Description
Input terminal of channel 1 RF signal.
Power supply voltage input. PIN2 and PIN15 are connected together.
1
Fin1
Vcc
I
2, 15
3
−
CP1
O
Output terminal of channel 1 charge pump. Charge pump is constant current output
circuit, and output current is selected by input serial data.
4, 13
GND
LD
−
O
I
Terminal of GND. PIN4 and PIN13 are connected together.
Output terminal of lock detection. It is the open drain output.
Input terminal of clock.
5
6
7
8
9
CK
DATA
EN
I
Input terminal of data.
I
Input terminal of enable signal.
BO
O
Output terminal of buffer amplifier. The signal of local oscillation is output through the
buffer amplifier.
10
11
OSCO
OSCI
O
I
Output terminal of local oscillation signal.
Input terminal of local oscillation signal.
In case of external input, connecting it to this terminal.
12
SW
O
Switch-over terminal for the time constant of loop filter. It is an open drain output.
If you don’t switch the time constant of loop filter, general output is available.
14
16
CP2
Fin2
O
I
Output terminal of channel 2 charge pump. Charge pump is a constant current output
circuit, and the output current is selected by input serial data.
Input terminal of channel 2 RF signal.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Power Supply Voltage
Power Dissipation
Symbol
Vcc
Value
6
Unit
V
PD
600
mW
°C
Operating temperature
Storage temperature
TOPR
TSTG
−30 to + 85
−55 to +150
°C
Take care ! ESD sensitive device
3
S1T8825B
1.3GHZ DUAL PLL
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3V, unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min.
2.2
Typ.
3.0
Max.
5.5
Unit
V
Operating power supply
voltage
Fin1=Fin2= 200MHz — 550MHz
Fin1=Fin2= 550MHz — 1.3GHz
VCC
2.7
3.0
3.6
V
Operating current
consumption
ICC
Fin1=Fin2=1.3GHz/ -5dBm input
5.5
7.0
9.5
mA
Standby current
ISB
Fin
Standby mode
Fin1 = Fin2 = − 5dBm
Vcc=2.2V
Fin1 = Fin2
Vcc=3.0V
= 200MHz
−
0
−
−
−
−
−
−
−
−
−
−
-
10
1300
0
µA
Fin operating frequency
200
− 15
− 15
− 10
−15
−15
− 10
− 10
− 10
− 10
5
MHz
0
Vcc=5.5V
0
Vcc=2.2V
Fin1 = Fin2
Vcc=3.0V
= 550MHz
0
Fin input sensitivity
Fin
dBm
0
Vcc=5.5V
0
Vcc=2.7V
Fin1 = Fin2
Vcc=3.0V
= 1.3GHz
0
0
Vcc=3.6V
0
OSCI operating frequency
OSCI input voltage
Fosc
VFin = 0dBm, sinewave
25
5
MHz
dBm
Vcc = 2.2V
− 10
− 10
- 5
0
0
0
0
0
0
fosc = 10MHz
fosc = 20MHz
Vcc = 3.0V
Vcc = 5.5V
Vcc = 2.2V
Vcc = 3.0V
Vcc = 5.5V
5
5
Vosc
− 10
− 10
− 5
5
5
5
Serial data input high
voltage (CK, DATA, EN)
VCC
0.4
−
VIH
VIL
VCC = 2.2 to 5.5V
VCC = 2.2 to 5.5V
−
−
-
V
V
Serial data input low voltage
(CK, DATA, EN)
−
0.4
Charge pump output
current
ICP1
ICP2
ICP3
ICP4
ICPL
CP1 = 0, CP2 = 0 VCP = 1.5 V
CP1 = 1, CP2 = 0 VCP = 1.5V
CP1 = 0, CP2 = 1 VCP = 1.5V
CP1 = 1, CP2 = 1 VCP = 1.5V
Standby mode, Vcp = 1.5V
–
–
± 1.6
± 0.2
± 0.4
± 0.8
−
−
−
mA
mA
mA
mA
µA
−
−
−
−
Charge pump leakage
−1
+1
4
1.3GHZ DUAL PLL
S1T8825B
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT AND TIMING
CK (Pin6), DATA (Pin7), EN (Pin8) terminals in S1T8825B are used for MCU serial data interface (LSB: 1st input
data; MSB: Last input data). Serial data controls the programmable reference divider, programmable divider (CH1),
programmable divider (CH2), and control latch separately by means of group code. Binary serial data is entered via
the DATA pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When EN pin is high, stored
data is latched. The three terminals, CK, DATA, and EN, contain Schmitt trigger circuits to keep the data from errors
caused by noise, etc.
< Notice >
1. When power supply of S1T8825B is disconnected, CLK, DATA, EN port from MCU should be pulled low.
2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data.
3. When power goes up first, control data should be entered earlier than N1 and N2 counter data.
≥
≥
1us
0.2us
≥
0.2us
CK
DATA
≥
0.2us
LSB
MSB
L B
LSB
N1 (R1)
N2 (R2)
N3 (R3)
0.1us
N16 (R11) N17 (R12)
GC2
GC1
≥
≥
≥
0.1us
0.2us
≥
EN
0.2us
Figure 1.
NOTE: Start data input with LSB first
SERIAL DATA GROUP AND GROUP CODE
The S1T8825B can be controlled through 4 kinds of group selection. Each group is identified by selective a 2-bit
group code given below.
Serial Bits
Group Location
GC1 (MSB)
GC2 (MSB-1)
0
0
1
1
0
1
0
1
Control Latch
Ch 1 N Latch
Ch 2 N Latch
OSC R Latch
5
S1T8825B
1.3GHZ DUAL PLL
CONTROL LATCH
The control register executes the following functions:
•
•
•
•
•
Mode selection (H: test mode, L: normal mode)
Charge pump’s polarity and output current selection for each channel.
Output state selection for Lock Detector.
Standby control of each channel and reference divider.
ON / OFF control in filter switch.
LSB
CH1
CH2
MSB
GC2
"0"
GC1
"0"
T
CP
CP1
CP2
SB1
CP1
CP2
SB2
SBR
LD1
LD2
SW
Group Code
Figure 2.
Bit
Name
Description test mode
Bit 1
Bit 2
Bit 3
CP1
Bit 4
CP2
Bit 5
Bit 6
CP1
Bit 7
CP2
T
CP
SB1
charge
pump
channel 1
charge
pump
output
current
channel 1
charge
pump
output
current
channel 1
standby
channel 2
charge
pump
output
current
channel 2
charge
pump
output
current
output
polarity
Bit
Name
Bit 8
SB2
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
SBR
LD1
LD2
SW
GC2
GC1
Description channel 2
standby
reference
divider
standby
lock
detector
control 1
lock
detector
control 2
filter switch group code group code
“0” “0”
6
1.3GHZ DUAL PLL
S1T8825B
CHARGE PUMP OUTPUT POLARITY (CP)
VCO Characteristics
(1)
(2)
In normal operation, the CP should be “0”.
In reverse operation, the CP should be “1”.
Depending upon VCO characteristics, CP should be set accordingly;
When VCO characteristics are like (1), CP should be set to low
When VCO characteristics are like (2), CP should be set to high.
VCO
Output
Frequency
VCO Input Voltage
CHARGE PUMP OUTPUT CURRENT (CP1, CP2)
The S1T8825B includes a constant current output type charge pump circuit.
Output current is varied according to control bit “CP1” and “CP2”.
In order to get high speed lock-up, select the best charge pump output current.
Control Bit
Charge Pump
Output Current
CP1
CP2
0
0
1
1
0
1
0
1
± 1600 µA
± 200 µA
± 400 µA
± 800 µA
7
S1T8825B
1.3GHZ DUAL PLL
TEST MODE AND LOCK DETECTOR OUTPUT (T, LD1, LD2)
When T is normal “0”, LD (Pin5) state is varied by controlling “SB1”, “SB2”, “LD1” and “LD2”.
When T is high “1”, LD (Pin5) state is changed to be useful for test
T
SB1
SB2
LD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
×
×
LD2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
×
LD Output State
low
channel2
0
channel1
channel1. AND. channel2
0
low
high
1
0
1
0
1
channel1
channel1
low
0
channel2
high
channel2
low
1
high
high
high
low
pres2
fpll2
1
0
fref
div4
1
pres1
fpll1
fosc/2
low
1
0
1
0
low
8
1.3GHZ DUAL PLL
S1T8825B
LOCK DETECTOR OUTPUT
When the phase comparator detects a phase difference, LD (Pin5) outputs “L”.
When the phase comparator locks, LD outputs “H”. On standby, it outputs “H”.
When T is less than 2/fosc (T<2 /fosc ) for more than three cycles of reference divider output as in the figure below,
the lock detector outputs “H”.
A
B
Reference
Divider output
Channel
Divider output
T
Charge pump
output
T<2/fosc
Lock detector
output
Figure 3. Lock Detector Output
fosc: OSCI operating frequency (LOCAL OSC).
T: time difference of the pulse between reference divider output and channel divider output.
Number of divisions by reference divider
(s)
A =
B =
fosc
2
fosc
(s)
PROGRAMMABLE STANDBY MODE (SB1, SB2, SBR)
Standby mode can be controlled by 3-control bits such as SB1, SB2 and SBR. SB1 and SB2 can control the
standby mode of channel 1 and channel2. The “SBR” bit can do ON / OFF control of reference divider.
Control Bit
Standby Mode State
SB1
SB2
SBR
CH1
ON
CH2
ON
REF
ON
Mode Status
0
0
1
1
1
0
1
0
1
1
×
×
×
0
1
Inter locking Mode
CH1 Locking Mode
CH2 Locking Mode
REF On Mode
ON
OFF
ON
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
Standby Mode
9
S1T8825B
1.3GHZ DUAL PLL
FILTER SWITCH CONTROL (SW)
The operation mode of the SW terminal is set by bit “SW”.
SW control is useful for switching the time constant of the loop filter.
Output type of this terminal is an open drain output. High lock mode or normal lock mode can be used, taking
advantage of filter switch control (SW) with the charge pump output current.
When fast lock function can’t be used, normal lock mode is available.
Control Bits
Operation Mode
(SW and LPF example) The third order LPF
SW
0
CP1
0
CP2
0
0
0
1
Normal Lock Mode
0
1
0
CP1
R
0
1
1
R
1
0
0
SW
R
1
0
1
High Lock Mode
1
1
0
GND
1
1
1
CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO)
External capacitors C1, C2, C3, and C4 are required to set the proper crystal’s load capacitance and oscillation
frequency as shown in figure 4. The value of the capacitors is dependent on the crystal chosen.
The BO (Pin9) outputs local oscillation signal with buffer amplifier.
This terminal (Pin9) can be applied to the 2nd mixer input
C4
1000pF
OSCI
OSCO
BO
Reference Oscillator
OSCI
OSCO
BO
C3
C2
C1
1000pF
1000pF
2'nd MIX
or OPEN
2'nd MIX
or OPEN
Figure 4.
10
1.3GHZ DUAL PLL
S1T8825B
PROGRAMMABLE REFERENCE COUNTER
This block generates the reference frequency for the PLL.
The reference divider is composed of 12-bit reference divider and a half fixed divider
Sending certain data to the reference divider allows the setting of any of 6 to 8190 divisions (multiple of two)
.
LSB
MSB
GC2 GC1
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12
"1"
"1"
Division Ratio of the R counter, R
Group Code
R = R1 × 20 + R2 × 21 + … + R12 × 211
Division ratio: 2 × R = 2 × (3 to 4095) = 6 to 8190
Data is shifted in LSB first.
Division
Ratio
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
3
4
•
0
0
0
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
0
•
0
•
0
•
4095
1
1
1
1
1
1
1
1
1
1
1
1
Example) A 21.25MHz X-tal oscillator is connected, and divided into 25kHz steps.
(Reference frequency is 12.5kHz)
21.25 MHz ÷ 12.5 kHz = 1700
1700 = 2 × R
R = (850)10 = (1101010010)2
LSB
MSB
0
1
0
0
1
0
1
0
1
1
0
0
1
1
11
S1T8825B
1.3GHZ DUAL PLL
CHANNEL 1, CHANNEL 2 PROGRAMMABLE N COUNTER
These programmable dividers are composed of a 5-bit swallow counter (5-bit programmable divider),
12-bit programmable main counter, and two-modulus prescalers providing 64 and 66 divisions.
Sending certain data to the swallow counter and the 12-bit programmable main counter allows the setting of any of
2048 to 262142 divisions (multiple of two).
The 12-bit programmable divider and swallow counter are set by each channel;
each channel is identified by a group code.
LSB
MSB
Swallow counter
N2 N3 N4
main counter
N1
N5
N6
N7
N8
N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19
Division Ratio of the N Counter, N
Group Code
CH1 = "10"
CH2 = "01"
Figure 5.
5-BIT SWALLOW COUNTER DIVISION RATIO (A COUNTER)
A = N1 × 20 + N2 × 21 … N5 × 24
Division ratio: 0 to 31, B ≥ A
Division Ratio
N5
N4
N3
N2
N1
(A)
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
•
31
1
1
1
1
1
12-BIT MAIN COUNTER DIVISION RATIO (B COUNTER)
B = N6 × 20 + N7 × 21 + N7 × 22 … N17× 211
Division ratio: 3 to 4095
Data is shifted in LSB first
Division
N17 N16 N15 N14 N13 N12 N11 N10
N9
N8
N7
N6
Ratio (B)
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
0
•
1
0
•
4
•
4095
1
1
1
1
1
1
1
1
1
1
1
1
12
1.3GHZ DUAL PLL
S1T8825B
Channel1 and 2 Programmable Counter Division Ratio, N
N = 2 × (32 × B + A), B ≥ A
Division ratio: 192 to 262142
Example) A Signal of 453 MHz is entered into Fin1, and divided into 25 kHz steps.
(Reference frequency is 12.5 kHz)
453 MHz ÷ 12.5 kHz = 36240, N = 2 × (32 × B + A) = 36240 , 32 × B + A =18120
N = 18120 ÷ 32 = 566.25, A = 0.25*32 = 8
B = (566)10 = (1000110110)2, A = (8)10 = (01000)2
LSB
MSB
0
0
0
1
0
0
1
1
0
1
1
0
0
0
1
0
0
1
0
Example) A Signal of 462.9 MHz is entered into Fin2, and divided into 25 kHz step.
(Reference frequency is 12.5 kHz)
462.9 MHz ÷ 12.5 kHz = 37032, N = 2 × (32 × B + A) = 37032, 32 × B + A =18516
N = 18516 ÷ 32 = 578.625, A = 0.625*32 = 20
B = (578)10 = (1001000010)2, A = (20)10 = (10100)2
LSB
MSB
0
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
PHASE DETECTOR AND CHARGE PUMP CHARACTERISTICS
Phase difference detection Range: -2 π to +2 π
When SW = Low
fr
fp
LD
CPO
fr > fp
fr = fp
fr < fp
fr < fp
fr < fp
Figure 6.
13
S1T8825B
1.3GHZ DUAL PLL
SENSITIVITY TEST CIRCUIT
2.2 V to 5.5 V
51 ohm
50 ohm
Microstrip
1000pF
RF
1
2.15
VCC
Signal Generator
Fin1
LD
VCC
10 nF
+
5
10 uF
5 kohm
20.945 MHz
11
Oscilloscope
6
OSCI
CK
7
8
100p
68p
DATA
10
EN
OSCO
47p
50p
SERIAL
DATA
UNIT
14
1.3GHZ DUAL PLL
S1T8825B
TYPICAL APPLICATION CIRCUIT
10nF
VCO
2.2k
50pF
47pF
0.1µF
51k
68p
10nF
2n'd MIX
1nF
1nF
8.2k
20.945
MHz
VCC
10nF
100p
16
Fin2
15
VCC
14
CP2
13
GND
12
SW
11
OSCI
10
OSCO
9
BO
S1T8825B
Fin1
1
VCC
2
CP1
3
GND
4
LD
5
CLK
6
DATA
7
EN
8
10nF
From
Controller
5k
10uF
+
0.1µF
30k
1nF
10nF
VCC
7.5k
VCO
10nF
MOD
15
S1T8825B
1.3GHZ DUAL PLL
NOTES
16
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