S1T8536 [SAMSUNG]
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER; 2.4GHZ ， 2.5GHZ单芯片射频收发器
| 型号： | S1T8536 |
| 厂家： | 
SAMSUNG |
| 描述： | 2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER |
| 文件： | 总24页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
INTRODUCTION
S1T8536
48−LQFP−0707
The S1T8536 is a single chip RF transceiver optimized for use in ISM
2.45GHz wireless systems. It is fabricated using Samsung’s ASP5HB
0.5um advanced BiCMOS process.
The S1T8536 contains receiver, transmitter, frequency doubler,
voltage controlled oscillator (VCO), phase locked loop(PLL) and
crystal oscillator.
The receiver consists of a 2.4 - 2.5GHz high frequency mixer, an
intermediate frequency (IF) amplifier, a FM quadrature demodulator, a
received signal strength indicator (RSSI), a baseband filter buffer
amplifier and a high speed data slicer with sample & hold function.
The transmitter consists of 2.4 - 2.5GHz high frequency buffer
amplifier.
The PLL operates upto 1.3GHz with 32/33 prescaler and selectable charge pump current. S1T8536 contains on-
chip PLL regulator to minimize switching noise.
The VCO operates 1.15 - 1.3GHz and requires only external tank circuit and loop filter.
S1T8536 contains on-chip VCO regulator to minimize VCO frequency variation due to supply pushing.
The frequency doubler receives 1.15 - 1.3GHz signal from VCO and outputs 2.3 - 2.6GHz signal to receiver and
transmitter.
The crystal oscillator operates 5 - 40MHz and can accept external clock signal.
Two additional voltage regulators provide a stable supply source to external discrete stages in the Rx and Tx
chains.
FEATURES
•
•
•
•
•
•
•
•
•
2.4GHz - 2.5GHz Single-Chip RF Transceiver
Samsung ASP5HB 0.5um Advanced BiCMOS Process
3.0V to 5.5V Operation (RX / TX mode supply current of 75mA / 50mA)
Single Conversion Receiver with 110MHz IF Frequency
Quadrature Demodulator with Greater than 1MHz Bandwidth
Wideband Buffer Amplifier for Baseband Filtering
High Speed Data Slicer Operating Upto 2Mbps with Sample & Hold
1.3GHz PLL with VCO and Frequency Doubler
PLL, VCO, RX and TX Voltage Regulator Included (2.85V)
APPLICATION
•
2.45GHz ISM Band Wireless Communication Systems
ORDERING INFORMATION
Device
Package
Operating Temperature
S1T8536X01-T0R0
48-LQFP-0707
- 10 to + 70°C
1
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
BLOCK DIAGRAM
VCC
MIX
VCC
IF
GND
IF
GND
IF
GND VCC QUAD
QUAD QUAD IN
VCC
MIX
MOP MON
IFP
31
IFN
30
36
35
34
33
32
29
28
27
26
25
VREG
RX
Regulator
(2.85V)
GND
BB
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
GND
MIX
QUAD
OUT
A
GND
MIX
BUF
IN
RSSI
1
BUF
OUT
MIP
MIN
DS
INP
Frequency
Doubler
GND
FD
DS
INN
VREG
TX
Sample
Hold
SHO
GND
FD
DS OUT
SHEN
RSSI
CE
Regulator
(2.85V)
RF Counter
PFD
VCC
FD
REF Counter
CONTROL
TX
OUT
GND
VCO
VCC
VCO
Regulator
(2.85V)
Charge
Pump
Lock
Detector
OSCI
Regulator
(2.85V)
1
2
3
4
5
6
7
8
9
10
11
12
VREG
VCO
VCC VREG
PLL PLL
GND
PLL
VCOP VCON
CP
LD
CLK DATA LE
OSCO
2
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN CONFIGURATION
S1T8536
VCC VCC VCC
GND GND GND VCC QUAD
MOP MON
IFP
31
IFN
30
MIX MIX
IF
IF
IF QUAD QUAD IN
36
35
34
33
32
29
28
27
26
25
VREG
RX
GND
BB
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
GND
MIX
QUAD
OUT
GND
MIX
BUF
IN
BUF
OUT
MIP
MIN
DS
INP
GND
FD
DS
INN
S1T8536
VREG
TX
SHO
GND
FD
DS OUT
SHEN
RSSI
CE
VCC
FD
TX
OUT
GND
VCO
VCC
VCO
OSCI
1
2
3
4
5
6
7
8
9
10
11
12
VREG
VCO
GND VCC VREG
PLL PLL PLL
VCOP VCON
CP
LD
CLK DATA LE OSCO
3
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION
Pin
Name
Schematic
Description
1
VREGVCO
VCO regulator output (2.85V). Requires external
bypass capacitor.
VCCVCO
1
2
3
VCOP
VCON
These differential ports are used to supply DC
voltage to the VCO as well as tune the center
frequency of the VCO.
2
3
4
5
6
GNDPLL
VCCPLL
VREGPLL
Ground of PLL section (Note 1).
Supply of PLL section.
PLL regulator output (2.85V).
Requires external bypass capacitor.
VCCPLL
6
4
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
S1T8536
Pin
Name
Schematic
Description
Charge pump output.
7
CP
VCCPLL
7
8
LD
Lock detector open drain output.
8
9
CLK
DATA
LE
Programming clock input.
Programming data input.
10
11
VCCPLL
Programming load enable input.
9, 10, 11
12
13
OSCO
OSCI
Crystal oscillator input.
Crystal oscillator output.
VREGPLL(2.85V)
13
12
14
CE
Chip enable input. Logic high input enables the chip
and logic low input disables the chip.
VCCPLL
14
5
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
15
RSSI
Received signal strength indicator output.
VCCIF
15
16
17
SHEN
Sample and hold enable input.
High signal input enable sample and hold function
and low signal input disable sample and hold
function .
VCCIF
16
DSOUT
Data slicer output.
VCCIF
17
18
SHO
Sample and hold output.
18
19
20
DSINN
DSINP
Data slicer negative input.
Data slicer positive input.
VCCIF
19
20
21
22
BUFOUT
BUFIN
Baseband filter buffer amplifier output.
Baseband filter buffer amplifier input.
VCCIF
22
21
6
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
S1T8536
Pin
Name
Schematic
Description
23
QUADOUT
Quadrature demodulator output.
VCCQUAD
23
24
25
GNDBB
QUADIN
Ground of baseband section (Note 1).
Quadrature demodulator tank input.
VCCQUAD
25
26
27
VCCQUAD
GNDQUAD
Supply of quadrature detector section.
Ground of quadrature detector section (Note 1).
28
29
GNDIF
GNDIF
Ground of IF amplifier section (Note 1).
Pin28 and Pin29 are connected internally.
30
31
IFN
IFP
IF amplifier differential inputs.
DC blocking is required.
VCCIF
30
31
32
VCCIF
Supply of IF amplifier section.
33
34
VCCMIX
VCCMIX
Supply of mixer section.
Pin33 and Pin34 are connected internally.
7
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
35
36
MON
MOP
RF mixer differential IF outputs.
VCCMIX
35
36
37
VREGRX
RX regulator output (2.85V).
Requires external bypass capacitor.
VCCMIX
37
38
39
GNDMIX
GNDMIX
Ground of mixer section (Note 1).
Pin38 and Pin39 are connected internally.
40
41
MIP
MIN
RF mixer differential inputs.
DC blocking is required.
VCCMIX
40
41
42
GNDFD
Ground of frequency doubler section (Note 1).
8
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PIN DESCRIPTION (Continued)
S1T8536
Pin
Name
Schematic
Description
TX regulator output (2.85V).
Requires external bypass capacitor.
43
VREGTX
VCCFD
43
44
45
46
GNDFD
VCCFD
TXOUT
Ground of frequency doubler section (Note 1).
Supply of frequency doubler section.
TX buffer amplifier output.
VCCFD
46
47
48
GNDVCO
VCCVCO
Ground of VCO section (Note 1).
Supply of VCO section.
NOTE: All ground pads of the chip are down bonded to package ground paddle and each ground pin of the IC is connected to
that package ground paddle.
So all the ground pins are connected together through the exposed ground paddle of the IC package. Proper
connection of package ground to board ground is essential and highly required.
9
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
ABSOLUTE MAXIMUM RATINGS
Characteristics
Power Supply Voltage
Symbol
VCC
Value
6.0
Unit
V
Voltage applied to any pin
Storage Temperature Range
VIN
VCC + 0.3
-65 to +150
V
TSTG
°C
RECOMMENDED OPERATING CONDITIONS
Characteristics
Power Supply Voltage
Operating Temperature
Symbol
Value
3.6
Unit
V
VCC
Ta
-10 to +70
°C
Caution : S1T8536 is a high performance RF integrated circuit and is ESD sensitive.
Handling and assembly of this device should be done at ESD work stations.
10
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
DC ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3.6V, unless otherwise noted.)
Characteristics
RX Mode Supply Current
Symbol
Test condition
Min
Typ
Max
Unit
ICC-RX
-
-
75
100
mA
(Receiver + Frequency Doubler + PLL + VCO)
TX Mode Supply Current
ICC-TX
-
-
50
70
mA
(Transmitter+Frequency Doubler+PLL+VCO)
Locking Mode Supply Current (PLL + VCO)
ICC-
LOCK
-
-
-
20
10
30
mA
uA
Power Down Mode Supply Current (All Off)
ICC-PD
CE(PIN14)=LOW
100
RECEIVER / TRANSMITTER ELECTRICAL CHARACTERISTICS
(Ta=25°C, VCC=3.6V, unless otherwise noted. RF=2.45GHz/-47dBm, LO=1.17GHz/-15dBm, IF=110.592MHz
Data = 1Mbps pseudo random sequence with BTb = 0.5 GFSK modulation. Modulation index = 0.5)
Characteristics
Mixer Input RF Frequency
Symbol
Test condition
Min
Typ
Max
Unit
RF In Freq.
50ohm
2.4
-
2.5
GHz
matching
110.6
-82
-
Mixer Output IF Frequency
IF Out Freq SAW matching
50
-
200
-76
200
-
MHz
dBm
MHz
dB
1E-3 BER Sensitivity (Notes 1 and 2)
IF Amplifier Bandwidth
SENS
data out
IFAmp BW
IFAmp Gain
DET Out
-
-
50
70
100
IF Amplifier Voltage Gain
75
Quadrature Demodulator Output Voltage
External load
variable
150
200
mVrms
Quadrature Demodulator Bandwidth
DET BW
-
0.6
1
1
2
-
-
MHz
MHz
Baseband Filter Buffer Amplifier Bandwidth
BB Amp BW
External load
variable
Baseband Filter Buffer Amplifier Voltage Gain
BB Amp
Gain
-
-3
0
+3
dB
Data Slicer Maximum Operating Frequency
RSSI Dynamic Range (110MHz IF Amp Input)
RSSI Output Level (110MHz IF Amp Input)
DS BW
RSSI DR
RSSI Out
-
-
1
2
60
-
-
-
Mbps
dB
50
0.5
IF
2.0
V
input(110MHz)
TX Output Power (Notes 1 and 2)
TX Out
50ohm
-
-15
-
dBm
matching
NOTES:
1. Not 100% AC tested but guaranteed by design and characterization.
2. Measured result on evaluation board with proper impedance matching.
11
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
VCO / PLL ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3.6V, unless otherwise noted)
Characteristics
Symbol
Test condition
Min
1150
1150
-15
Typ
Max
1300
1300
5
Unit
MHz
MHz
dBm
MHz
mVpp
mA
VCO Operating Frequency (Note 1)
PLL Operating Frequency
VCO Freq.
RF In Freq
-
-
-
-
-
-
-
-
-
-
PLL Input Sensitivity (external VCO Input) RF In Power
OSC Operating Frequency
OSC Input Sensitivity
OSC In Freq.
OSC In Power
CPI = Low
5
-
40
100
± 1.1
± 2.1
500
± 1.5
± 3.0
2000
± 2.0
± 4.0
Charge Pump Output Current
CPI = High
mA
NOTE: Not 100% AC tested but guaranteed by design and characterization.
REGULATOR ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3.6V, unless otherwise noted.)
Characteristics
Symbol
VREG-PLL
VREG-VCO
VREG-RX
VREG-TX
Test condition
load regulated
load regulated
load regulated
load regulated
Min
2.7
2.7
2.7
2.7
Typ
2.85
2.85
2.85
2.85
Max
3.0
3.0
3.0
3.0
Unit
V
PLL Regulator Voltage (Note 1)
VCO Regulator Voltage (Note 1)
RX Regulator Voltage (Notes 1 and 2)
TX Regulator Voltage (Notes 1 and 2)
V
V
V
NOTES:
1. Voltage regulation operates under the condition of supply voltage greater than 3.3V.
2. RX and TX regulator are tested with load current of 10mA.
DIGITAL I / O ELECTRICAL CHARACTERISTICS
(Ta = 25°C, VCC = 3.6V, unless otherwise noted)
Characteristics
High Level Input Voltage
Symbol
VIH
Test condition
Min
Typ
Max
Unit
V
-
-
-
-
VCC-0.4
-
-
-
-
VCC
0.4
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
VIL
0
VCC-0.4
0
V
VOH
VOL
VCC
0.4
V
V
12
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
RECEIVER FUNCTIONAL DESCRIPTION
General
The S1T8536’s receiver is a single conversion wideband FM / FSK receiver. This device is designed for use as the
receiver in analog and digital FM systems such as 2.4GHz ISM band cordless phones and wideband data links with
data rates up to 2Mbps. It contains high frequency mixer, IF amplifier, quadrature detector, baseband filter amplifier
and data slicer with sample and hold function.
Mixer
The mixer is a double-balanced with fully differential RF inputs and fully differential IF outputs. Following figure
shows the external components required for wideband 110.592MHz IF operation.
MOP MON
IFP IFN
36
36
31
30
110.592MHz
SAW
VCC
Quadrature Demodulator
The quadrature demodulator requires tank circuit with loaded Q depending on detection bandwidth. Following
figure shows external components required for 110.592 MHz IF operation.
QUAD IN
25
QUAD OUT
23
56nH
10pF
22pF
VCC
Baseband Filter Buffer Amplifier
Baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter.
Following figure shows the external components required.
Cutoff frequency = 1 / [2π*SQRT(R1R2C1C2)]
Quality factor = SQRT(R1R2C1C2) / (R1C2 + R2C2)
The component value of R1 should contain the quadrature detector output resistance.
13
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
RECEIVER FUNCTIONAL DESCRIPTION
C1
Vout
C2
R2
R1
Vin
21
22
BUF OUT
BUF IN
Data Slicer with Sample and Hold
The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the
baseband filter output can be DC coupled to the data slicer DS-INP(Pin 20). The S1T8536’s data slicer
incorporates an sample and hold used to derive the data slicer reference voltage by means of an external
integration circuit. The sample and hold is ’ON’ during reception of the preamble data pattern, and is otherwise
‘OFF’ in TDD (Time Division Duplex) system. The external integration circuit is formed by an RC low pass circuit
placed between SHO (Pin 18) and ground.
The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer
shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a
change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift
close to the threshold voltage, the time constant is longer.
The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the
settling time. When the sample and hold is ‘OFF’ the output (SHO) is in high impedance state with extremely low
leakage current.
Following figure shows the internal block diagram.
DS INP
20
17
DS OUT
19
18
DS INN
SHO
+1
SHEN
16
The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommended that an
external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of
ground and supply currents in the S1T8536 which might desensitize the chip.
14
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PLL / VCO FUNCTIONAL DESCRIPTION
GENERAL
The S1T8536’s PLL / VCO is a high performance frequency synthesizer with high frequency voltage controlled
oscillator and integrated high frequency prescalers for RF operation upto 1.3GHz. It contains two voltage regulator
of VCO and PLL, dual modulus prescalers providing 32/33 division, no dead-zone PFD, selectable charge pump
current, lock detector output and crystal oscillator.
VCO / PLL VOLTAGE REGULATOR
The S1T8536’s PLL / VCO incorporates one on-chip 2.85V voltage regulators for stable VCO operation and
another on-chip 2.85V voltage regulators for minimizing ECL and CMOS switching noise eliminating the need for
an external regulator. They insures stable high frequency operation at 3.0V through 5.5V supply voltage .
VCO regulated voltage is used only for VCO. PLL regulated voltage is used for ECL-prescaler, CMOS-counter,
internal logic circuits and crystal oscillator. All digital input / output pins are referenced to supply voltage rather than
regulated voltage.
CRYSTAL OSCILLATOR
S1T8536 has a oscillator circuit composed of CMOS inverter amplifier. In case of inputting the external reference
frequency directly, use OSCI terminal (Pin 13).
.
OSCI
13
OSCO
12
OSCI
13
OSCO
12
external
LOOP FILTER
Following figure shows third order passive loop filter
CP
7
VCO tuning
15
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
LOCK DETECTOR OPERATION
1/(OSC / R)
1/OSC
fREF
fPLL
CP
LD
E
High
When the situation that E(error) is less than one period of reference frequency, 1/OSC, continues more than three
cycles of reference counter output, 1/(OSC/R), lock detector outputs ‘High’.
16
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PLL / VCO FUNCTIONAL DESCRIPTION
VOLTAGE CONTROLLED OSCILLATOR
S1T8536’s voltage controlled oscillator (VCO) uses a fully differential topology, with L-C resonant tank circuit off-
chip.
Following figure shows external components for VCO operation.
charge
pump
LOOP
FILTER
1
2
3
REGULATOR
Following figure shows external components in case of using external VCO.
VCO
1
2
3
REGULATOR
17
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PROGRAMMING DESCRIPTION
SERIAL DATA PROGRAMMING TIMING
Every bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable (LE)
pin goes to high, stored data is latched according to the group code. The three terminals, CLK, DATA and LE,
contain schmitt trigger circuits to keep the programming from errors caused by noise and etc.
>100 ns
CLK
DATA
LSB
LSB+1
LSB+2
>50 ns
MSB-2
MSB-1
MSB
LSB
>50 ns
>100 ns
>50 ns
LE
>50 ns
SERIAL DATA PROGRAMMING GROUP
S1T8536 can be controlled through 3 kinds of program group. Each group is identified by selective 2 bits group
codes given below.
MSB-1
MSB
Group Selection
GC1
GC0
0
0
1
1
0
1
0
1
Control Latch
N-Counter Latch
R-Counter Latch
Not Allowed
18
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PROGRAMMING DESCRIPTION
CONTROL DATA PROGRAMMING (Data should be shifted in LSB first)
LSB
MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
G1
G0
control data
group-code
0 0
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Name
Description
Phase detector polarity select.
Setting to ‘0’
Negative VCO
+ 1.5mA
Setting to ‘1’
PDP
CPI
Positive VCO
+ 4.5mA
Charge pump output current select.
Charge pump output state select.
Receiver power down control.
Transmitter power down control.
VCO power down control.
CPZ
Normal operation
Receiver ‘ON’
Transmitter ’ON’
VCO ‘ON’
High Impedance
Receiver ‘OFF’
Transmitter ‘OFF’
VCO ‘OFF’
RXPD
TXPD
VCOPD
PLLPD
OSCPD
TEST0
TEST1
PLL power down control.
PLL ‘ON’
PLL ‘OFF’
Crystal oscillator power down control
Test mode control.
Oscillator ‘ON’
See below.
Oscillator ‘OFF’
Test mode control.
Charge Pump Polarity
Depending upon VCO characteristics, phase detector polarity should be set accordingly.
When VCO characteristics are like (1), phase detector polarity bit (PDP) should be set low (‘0’).
When VCO characteristics are like (2), phase detector polarity bit (PDP) should be set high (‘1’).
VCO
Frequency
(2)
positive
(1)
negative
VCO
Tuning
Voltage
19
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PROGRAMMING DESCRIPTION
Charge Pump Output State Control
CPZ bit is provided for open loop modulation during TX time slot in TDD (Time Division Duplex) system.
D2
CPZ
Charge pump output state
Normal
VCO operation
Closed loop
Open Loop
0
1
High impedance
Power Mode Control
D3
D4
D5
D6
D7
Power down state
RX
PD
TX
PD
VCO
PD
PLL
PD
OSC
PD
Frequency
Doubler
VCO
PLL
RX
TX
Regulator
Regulator
Regulator
Regulator
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
OFF
Test Mode Control
D9
D8
LD Output
TEST1
TEST0
0
0
1
1
0
1
0
1
Lock Detect
fPLL (VCO / N)
fREF (OSC / R)
High
20
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
PROGRAMMING DESCRIPTION
N-COUNTER DIVISION RATIO DATA PROGRAMMING (Data should be shifted in LSB first)
The N-counter consists of the 5-bit swallow counter (A-counter), 8-bit programmable main counter (B-counter) and
dual-modulus prescaler providing 32 / 33 division.
LSB
A0
MSB
G0
A1
A2
A3
A4
B0
B1
B2
B3
B4
B5
B6
B7
G1
Swallow-counter
(A-counter)
Main-counter
(B-counter)
group-code
1 0
5-Bit Swallow Counter (A-Counter) Division Ratio
A = A4*2^4 + A3*2^3 + A2*2^2 + A1*2^1 + A0*2^0
Division ratio : 0 to 31, A < B
Division Ratio (A-Counter)
A4
0
A3
0
A2
0
A1
A0
0
0
1
0
0
•
1
0
0
0
•
•
•
•
•
31
1
1
1
1
1
8-Bit Main Counter (B-Counter) Division Ratio
B = B7*2^7 + B6*2^6 + B5*2^5 + B4*2^4 + B3*2^3 + B2*2^2 + B1*2^1 + B0*2^0
Division ratio : 3 to 255, B > A
Division Ratio (B-Counter)
B7
1
B6
1
B5
0
B4
0
B3
B2
0
B1
0
B0
0
3
4
0
0
•
0
0
1
0
0
0
0
•
•
•
•
•
•
•
•
255
1
1
1
1
1
1
1
1
N-Counter Division Ratio
N = (PXB) + A
P : Modulus of dual modulus prescaler which is 32
B : Division ratio of 8-bit main counter
A : Division ratio of 5-bit swallow counter
21
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
PROGRAMMING DESCRIPTION
REFERENCE-COUNTER DIVISION RATIO DATA PROGRAMMING (Data should be shifted in LSB first)
The R-counter consists of the 6-bit reference counter.
LSB
R0
MSB
G0
R1
R2
R3
R4
R5
G1
R-counter
group-code
0 1
6-Bit Reference Counter Division Ratio
R = R5*2^5 + R4*2^4 + R3*2^3 + R2*2^2 + R1*2^1 + R0*2^0
Division ratio : 3 to 63
Division Ratio
R5
1
R4
1
R3
R2
0
R1
0
R0
0
3
4
0
1
•
0
0
0
0
0
•
•
•
•
•
•
63
1
1
1
1
1
1
Example) If a 19.2MHz oscillator is connected, the internal PLL reference frequency is 400KHz,and the VCO
frequency is 1.2GHz,then equation is as follows.
R = X-tal / Reference Frequency
R = 19.2MHz / 400KHz = 48(d) = 110000(b)
The R register setting is 00001101(b).
N = Fvco / Freference
N =1.2GHz / 400KHz = 3000
N = 3000 / 32 = 93.75 , The B(main counter) is 93(d) = 1011101(b)
S = 0.75 * 32 = 24
,
The S(swallow counter) is 24(d) = 11000(b)
The N register setting is 000111011101010(b).
22
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
TEST CIRCUIT
S1T8536
SAFU110.6MSA40T
L5
VCC
R22
1
2
3
C42
47p
270nH
C43
4.7p
10
9
L6
270nH
4
5
33
C40 7p
C39
0.5p
8
7
6
C36
0.5p
C32
47p
C33
4.7p
C35
27p
C41 7p
C34
27p
VCC
C38
4.7n
C37
47p
R21
18
470nH
VCC
R23
18
L3
56n
C31
22p
VC1
10p
VCC
R25
C44
4.7p
C49
47p
22
24
37
38
39
GNDBB
QUADOUT
BUFIN
R17
33k
VREGRX
23
22
C27
47p
C28
4.7n
C47
10n
GNDMIX
C46
47p
R18
11k
R19
C25
15k
GNDMIX
MIP
C30
12p
R16
33k
8p
SMA
C48
1.5p
21
20
19
18
17
16
15
14
13
40
41
42
43
44
45
46
47
48
C49
BUFOUT
DSINP
1.2p
R15
C61
MIN
0
C51
4.7p
C50
47p
DSINN
SHO
GNDFD
C26 15n
C25
4.7n
C24
47p
S1T8536X01
R14
12k
R3
220
VREGTX
VCC
C52
47p
C53
10n
DSOUT
SHEN
R24
18
GNDFD
VCCFD
TXOUT
C55 C54
4.7p 47p
TP2
RSSI
L7
660nH
RSSI
CE
C23
10n
SMA7
VCC
C56
0.5p
GNDVCO
C57
N.C
R20
18
OSCI
C59
47p
VCCVCO
C52
4.7p
19.2MHz
C22
20pF
C21
30pF
L1
R1
330n
C1
10n
C2
47p
VCC
R12
56k
50
R3
18
C7
47p
L2
330n
50
C8
10n
C5
100p
R8 1K
R9 1K
R10 1K
R2
C16
47p
C6
10n
C18
47p
C17
47p
L2
330n
C4
1n
U2
R6
15k
JP1
VC0-1300GHz
C13
39p
C14
1
560p
1
2
3
4
5
6
7
14
13
12
11
10
9
R7
1.2k
2
R11
5k
VCC
11
10
9
8
7
1
3
GND
GND
VSW
GND
OUT
GND
VCC
GND
CONT
C60
?
C15
15n
4
2
3
4
5
SW1
5
6
SW SPDT
VCC
7
8
MOD
C19
100p
C20
10p
CNT1
R4
1k
R5
3.9k
C12
C9
47p
C10
4.7p
C11
1n
100n
23
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
APPLICATION CIRCUIT
SAFU110.6MSA40T
L5
270nH
VCC
R22
1
2
3
C42
47p
C43
4.7p
10
9
L6
270nH
4
5
C36
0.5p
33
C40 7p
C41 7p
C39
0.5p
8
7
6
C32
47p
C33
4.7n
C35
27p
C34
27p
VCC
C38
4.7n
C37
47p
R21
18
470nH
VCC
L3
56n
C31
22p
R23
18
VC1
10p
VCC
R25
C44
4.7p
C49
47p
18
24
37
GNDBB
QUADOUT
BUFIN
R17
33k
VREGRX
23
22
C27
47p
C28
4.7n
38
39
40
41
42
43
44
45
46
47
48
C47
10n
GNDMIX
C46
47p
VCC
R18
11k
R19
C3
10p
R34
100
C29
15k
GNDMIX
MIP
C30
12p
R16
33k
8p
SMA
C48
2.7p
21
20
19
18
17
16
15
14
13
C49
BUFOUT
DSINP
L14
1.2nH
1p
R35
18k
R15
C61
MIN
0
C50
47p
L13 1.2nH
Q2
C51
4.7p
DSINN
SHO
L12
N.C
GNDFD
C26 15n
C25
4.7n
C24
47p
S1T8536X01
R14
12k
R3
220
C68
100p
VREGTX
RFIN
RFIN
VCC
C52
47p
C53
10n
HPFB0420
DSOUT
SHEN
R24
18
GNDFD
VCCFD
TXOUT
GNDVCO
L15
N.C
TP4
RxDATA
C55 C54
4.7p 47p
TxVcc
L7
660nH
TP2
RSSI
RSSI
CE
C57
10p
C23
10n
R31
100
R32
18k
SMA
VCC
R20
18
C59
47p
C56
5p
L10
3.9nH
TxOUT C62 L11
C63
C11
OSCI
VCCVCO
1.8p
C52
4.7p
200p
VC2
10p
19.2MHz
L8
N.C
L9
N.C
2.2nH
TxOUT
33p
C21
30pF
C22
10pF
R4
10
Q1
HPFB0420
R1
10
VCC
R3
R12
56k
R8 1K
R9 1K
R10 1K
HVC355B
C7
VC
1 - 3p
18
47p
D1
C8
C4
10n
C12
100p
C5
L2
1nH
D2
DIODE
C26
2.2p
C16
47p
100p
C6
10n
2.2p
C18
47p
R31
VCO
R2
2k
L1
1nH
C17
47p
TP3
CP
0
R6
5.6k
JP1
LE
AFO
1
2
3
4
5
6
7
14
13
12
11
10
9
VREGRX
R28
R7
4.7k
C1
103
C14
680p
C2
47p
C13
N.C
DATA
CLK
LD
SHEN
CE
R11
5k
C67
150p
4.7K
RXD
GND
RSSI
RxVcc
C15
4.7n
C60
?
GND
MOD
TxVcc
TP1
R2
R5
VCC
TxVcc
8
MOD
3.9k
10k
R27
68
C19
100p
C20
10n
C9
C10
4.7p
CNT1
47p
24
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