BU2381FV [ROHM]
Multimedia ICs Clock generator for digital still camera; 多媒体IC时钟发生器，用于数字静态照相机
| 型号： | BU2381FV |
| 厂家： | 
ROHM |
| 描述： | Multimedia ICs Clock generator for digital still camera |
| 文件： | 总5页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BU2381FV
Multimedia ICs
Clock generator for digital still camera
BU2381FV
BU2381FV is a high-performance 3-channel PLL IC. PLL circuit generates necessary clocks by inputting standard clocks
of crystal oscillator from outside. Changing a connection of wire can generate any clocks required for any applications of
users. Jitter and S/N characteristic has achieved almost the same high-quality sound and vision as oscillating module
because of optimization of PLL. Frequency can be changed by the internal dividing control.
zApplications
zExternal dimensions (Unit : mm)
Digital still camera
5.0±0.2
16
9
zFeatures
1) Generate clocks for video output, CDS, USB from standard
clock input
2) No external elements required for PLL
3) Standard clocks apply to two kinds of NTSC/PAL
4) Single power supply of 3.3V operating
5) SSOP-B16 small package
1
8
0.15±0.1
0.1
0.65
0.22±0.1
SSOP-B16
zAbsolute maximum ratings (Ta=25°C)
Parameter
Applied voltage
Symbol
Limits
−0.5 to +7.0
−0.5 to VDD+0.5
−30 to +125
450
Unit
V
V
DD
IN
Input voltage
V
V
Storage temperature range
Power dissipation
Tstg
Pd
°C
mW
Derating : 4.5mW/°C for operating above Ta=25°C
An operation is not guaranteed.
Radiation resistance design is not used.
Power dissipation is measured when BU2381FV is placed on the board.
zRecommended operating conditions (Ta=25°C)
Parameter
Symbol
Min.
Typ.
−
Max.
3.6
Unit
Supply voltage
V
DD
IH
IL
3.0
V
V
Input "H" voltage range
Input "L" voltage range
Operation temperature range
Output maximum load
V
0.8VDD
0
−
VDD
V
−
0.2VDD
70
V
Topr
−5
−
°C
pF
CL
−
−
15
1/5
BU2381FV
Multimedia ICs
zBlock diagram
Data1a
Data1b
Data1c
71.877274MHz or 90.314686MHz
or 114.54546MHz
PLL1 144M
180M 228M
1 / 2
CLK1
96.016044MHz
1 / 2
1 / 2
14.318182MHz
XTAL_IN
96.016044MHz
48.008022MHz
PLL2
192MHz
XTAL
OSC
CLK2
XTAL_OUT
1 / 4
CLK2ON
FS1
17.734450MHz
14.318182MHz
PLL3
177MHz
1 / 10
REF_CLK
FS2
FS3
zPin descriptions
Functions
Pin No.
Pin name
REFCLK
1
2
14.3MHz / 17.7MHz clock output
Analog VDD
VDD
3
FS3
CLK1, 2 output select with pull up
Analog GND
4
VSS
5
X
IN
Standard crystal input
6
TEST
Input for test mode (normally open)
Standard crystal output
CLK1, 2 output select with pull up
7
X
OUT
8
FS2
CLK1OUT
FS1
9
71M / 90M / 96M / 114MHz clock output
REFCLK output select with pull up
10
11
12
13
14
15
16
CLK2 output control with pull up H : enable L : disable
GND for CLK1, 2 clock output and Logic circuit
CLK2ON
V
SS
DD
CLK2OUT
V
DD for CLK1, 2 clock output and Logic circuit
V
96M / 48M clock output
VSS
GND for REFCLK clock output
V
DD
VDD for REFCLK clock output
2/5
BU2381FV
Multimedia ICs
zInput output circuits
Pin No.
Equivalent circuit
Input PIN
3, 8, 10, 11
To inside IC
with pull−up
(PIN6 : TESTpin with
pull down)
OUTPUT PIN
1, 9, 14
From inside IC
Crystal PIN
5, 7
XTALIN
XTALOUT
To inside IC
3/5
BU2381FV
Multimedia ICs
zElectrical characteristics (Unless specified otherwise Ta=25°C, VCC=3.3V)
Parameter
Power supply current
Output frequency
Symbol
Min.
−
Typ.
40
−
Max.
50
Unit
mA
−
Conditions
I
DD
No load
−
−
−
FS2 : H
FS3 : H
Fclk1-1
Fclk1-2
Fclk1-3
Fclk1-4
Fclk2-1
Fclk2-2
−
−
−
−
−
−
96.016044
71.877274
114.54546
90.314686
96.016044
48.008022
−
−
−
−
−
−
−
−
Xtal (228 / 17) / 2
Xtal (251 / 25) / 2
FS2 : H
FS3 : L
CLK1
FS2 : L
MHz Xtal (224 / 14) / 2
MHz Xtal (164 / 12) / 2
MHz Xtal (228 / 17) / 2
MHz Xtal (228 / 17) / 4
FS3 : L
FS2 : L
FS3 : H
FS2 : L
FS3 : L
CLK2
FS2, 3 :
HL / LH / HH
Fref1-1
Fref1-2
−
−
14.318182
17.73445
−
−
MHz Crystal direct output
MHz Xtal (706 / 57) / 10
FS1 : H
REFCLK
FS1 : L
Duty1 at 100MHz
Duty2 at 100MHz
Rise time
Duty1
Duty2
tr
45
−
50
50
55
−
%
%
Measured at 1/2 VDD
Measured at 1/2 VDD
−
2.5
2.5
30
−
nsec Time between 0.2 VDD and 0.8 VDD
nsec Time between 0.8 VDD and 0.2 VDD
Fall time
tf
−
−
1
2
3
Period jitter 1σ
Period jitter MIN-MAX
Output Lock time
P-J1σ
P-JMINMAX
Tlock
−
−
psec
psec
msec
−
180
−
−
−
1
Note) When input frequency is 14.318182MHz, output frequency is above rated value.
1) Period Jitter 1σ : This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling.
2) Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling.
3) Output Lock time : This value is the time until the output clock gets stable after the power supply voltage leads to 3.0V.
4/5
BU2381FV
Multimedia ICs
zApplication example
REFCLK output
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0.1µF
FS3 H or L
CLK2 output
0.1µF
0.1µF
CLK2 ON H or L
FS1 H or L
CLK1 output
FS2 H or L
Note) The BU2381FV is placed on the board normally.
A decoupling capacitor (0.1µF) needs to be placed between pin2 and pin4, pin13 and pin12, pin16 and pin15.
The decoupling capacitor is an close to the above pins as possible.
5/5
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