BR34E02FVT-3 [ROHM]
Memory for Plug & Play DDR2/DDR3 SPD Memory (for Memory Modules); 内存即插即用DDR2 / DDR3内存的SPD (存储器模块)型号: | BR34E02FVT-3 |
厂家: | ROHM |
描述: | Memory for Plug & Play DDR2/DDR3 SPD Memory (for Memory Modules) |
文件: | 总20页 (文件大小:393K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Memory for Plug & Play
DDR2/DDR3
SPD Memory (for Memory Modules)
BR34E02FVT-3,BR34E02NUX-3
No.11002EAT05
●Description
BR34E02-3 Series is 256×8 bit Electrically Erasable PROM (Based on Serial Presence Detect)
●Features
1) 256×8 bit architecture serial EEPROM
2) Wide operating voltage range: 1.7V-5.5V
3) Two-wire serial interface
4) Self-Timed Erase and Write Cycle
5) Page Write Function (16byte)
6) Write Protect Mode
Settable Reversible Write Protect Function: 00h-7Fh
Write Protect 1 (Onetime Rom)
Write Protect 2 (Hardwire WP PIN)
7) Low Power consumption
: 00h-7Fh
: 00h-FFh
Write
Read
(at 1.7V )
(at 1.7V )
:
:
:
0.4mA (typ.)
0.1mA(typ.)
0.1µA(typ.)
Standby ( at 1.7V )
8) DATA security
Write protect feature (WP pin)
Inhibit to WRITE at low VCC
9) Compact package: TSSOP-B8, VSON008X2030
10) High reliability fine pattern CMOS technology
11) Rewriting possible up to 1,000,000 times
12) Data retention: 40 years
13) Noise reduction Filtered inputs in SCL / SDA
14) Initial data FFh at all addresses
●BR34E02-3 Series
Capacity
2Kbit
Bit format
256X8
Type
Power Source Voltage
TSSOP-B8
VSON008X2030
BR34E02-3
1.7V~5.5V
●
●
●Absolute maximum ratings (Ta=25℃)
Parameter
Symbol
VCC
Ratings
Unit
Supply Voltage
-0.3~+6.5
330(BR34E02FVT-3) *1
300(BR34E02NUX-3)*2
-65~+125
V
Power Dissipation
Pd
mW
Storage Temperature
Tstg
℃
℃
V
Operating Temperature
Terminal Voltage (A0)
Terminal Voltage (etcetera)
Topr
-40~+85
-
-
-0.3~10.0
-0.3~VCC+1.0
V
* Reduce by 3.3mW(*1), 3.0 mW(*2)/C over 25C
●Recommended operating conditions
Parameter
Symbol
Ratings
Unit
Supply Voltage
Input Voltage
VCC
VIN
1.7~5.5
0~VCC
V
V
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
1/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Memory cell characteristics(Ta=25℃, VCC=1.7~5.5V)
Limits
Parameter
Unit
Min.
1,000,000
40
Typ.
-
Max.
-
Write / Erase Cycle *1
Cycles
Years
Data Retention
*1
-
-
*1:Not 100% TESTED
●Electrical characteristics - DC(Unless otherwise specified Ta=-40~+85℃, VCC=1.7~5.5V)
Limits
Parameter
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Vcc+1.0
0.3 VCC
0.4
"H" Input Voltage
VIH
VIL
0.7 VCC
-
-
-
-
-
-
-
-
V
V
"L" Input Voltage
-0.3
-
"L" Output Voltage 1
"L" Output Voltage 2
Input Leakage Current 1
Input Leakage Current 2
Input Leakage Current 3
Output Leakage Current
VOL1
VOL2
ILI1
V
IOL=2.1mA, 2.5V≦VCC≦5.5V(SDA)
IOL=0.7mA, 1.7V≦VCC<2.5V(SDA)
VIN=0V~VCC(A0,A1,A2,SCL)
VIN=0V~VCC(WP)
-
0.2
V
-1
-1
-1
-1
1
µA
µA
µA
µA
ILI2
15
ILI3
20
VIN=VHV(A0)
ILO
1
VOUT=0V~VCC
VCC=5.5V,fSCL=400kHz, tWR=5ms
Byte Write
Page Write
Write Protect
VCC =5.5V,fSCL=400kHz
Random Read
ICC1
ICC2
-
-
-
-
2.0
0.5
mA
mA
Operating Current
Current Read
Sequential Read
VCC =5.5V,SDA,SCL= VCC
A0,A1,A2=GND,WP=GND
Standby Current
A0 HV Voltage
ISB
-
-
-
2.0
10
µA
V
VHV
7
VHV-Vcc≧4.8V
○Note: This IC is not designed to be radiation-resistant.
●Electrical characteristics - AC(Unless otherwise specified Ta=-40~+85℃, VCC =1.7~5.5V
Limits
Parameter
Clock Frequency
Symbol
Unit
Min.
-
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
400
-
fSCL
tHIGH
tLOW
tR
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time *1
SDA and SCL Fall Time *1
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
0.6
1.2
-
-
0.3
0.3
-
tF
-
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
0.6
0.6
0
-
-
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
100
0.1
0.1
0.6
1.2
-
-
0.9
-
tDH
tSU:STO
tBUF
-
-
Write Cycle Time
tWR
5
Noise Spike Width
(SDA and SCL)
tI
-
-
0.1
µs
WP Hold Time
WP Setup Time
tHD:WP
tSU:WP
0
-
-
-
-
-
-
µs
µs
µs
0.1
WP High Period
tHIGH:WP 1.0
*1:Not 100% TESTED
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
2/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Synchronous Data Timing
tR
tF
tHIGH
SCL
SDA
SCL
DATA(n)
DATA(1)
D1
tHD:STA
tSU:DAT tLOW
tHD:DAT
ACK
ACK
D0
SDA
(IN)
tWR
tBUF
tPD
tDH
WP
STOP BIT
SDA
(OUT)
tHD:WP
tSU:WP
Fig.1-(a) Synchronous Data Timing
Fig.1-(d) WP Timing Of The Write Operation
○ SDA data is latched into the chip at the rising edge
○ of SCL clock.
○ Output data toggles at the falling edge of SCL clock.
SCL
SCL
SDA
DATA(1)
D1
DATA(n)
SDA
WP
tSU:STA
tHD:STA
tSU:STO
D0 ACK
ACK
tHIGH : WP
tWR
STOP BIT
START BIT
Fig.1-(b) Start/Stop Bit Timing
Fig.1-(e) WP Timing Of The Write Cancel Operation
○For WRITE operation, WP must be "Low" from the rising edge of
the clock (which takes in D0 of first byte) until the end of tWR.
(See Fig.1-(d) ) During this period, WRITE operation can be
canceled by setting WP "High".(See Fig.1-(e))
○When WP is set to "High" during tWR, WRITE operation is
immediately ceased, making the data unreliable. It must then
be re-written.
SCL
SDA
D0
ACK
tWR
WRITE DATA(n)
STOP
CONDITION
START
CONDITION
Fig.1-(c) Write Cycle Timing
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2011.11 - Rev.A
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© 2011 ROHM Co., Ltd. All rights reserved.
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Block diagram
PROTECT_MEMORY_ARRAY
2Kbit_MEMORY_ARRAY
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
8bit
8bit
ADDRESS
DECODER
SLAVE , WORD
DATA
REGISTER
8bit
ADDRESS REGISTER
START
STOP
A2
SCL
SDA
CONTOROL LOGIC
ACK
GND
HIGH VOLTAGE GEN.
VCC LEVEL DETECT
Fig.2 Block Diagram
●Pinout diagram and description
Pin Name
Input/Output
Functions
-
-
IN
IN
VCC
Power Supply
Ground 0V
A0 1
8 VCC
7 WP
6 SCL
5 SDA
GND
A0,A1,A2
SCL
A1 2
A2 3
BR34E02FVT-3
BR34E02NUX-3
Slave Address Set.
Serial Clock Input
Slave and Word Address,
*1
*2
SDA
WP
IN / OUT
IN
Serial Data Input, Serial Data Output
GND
4
Write Protect Input
Fig.3 Pin Configuration
*1 Open drain output requires a pull-up resistor.
*2 WP Pin has a Pull-Down resistor. Please leave unconnected or
connect to GND when not in use.
●Electrical characteristics curves
The following characteristic data are typ. value.
6
6
5
4
3
2
1
0
1
0.8
0.6
0.4
0.2
0
5
4
SPEC
SPEC
3
Ta=85℃
Ta=-40℃
Ta=25℃
2
Ta=85℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=25℃
1
0
SPEC
Ta=-40℃
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
34:I2C
VCC[V]
VCC[V]
IOL1[mA]
Fig.6 "L" Output Voltage VOL1-IOL1
(VCC=2.5V)
Fig.5 "L" Input Voltage VIL
Fig.4 "H" Input Voltage VIH
(A0,A1,A2,SCL,SDA,WP)
(A0,A1,A2,SCL,SDA,WP)
1
0.8
0.6
1.2
1
16
SPEC
SPEC
12
0.8
0.6
0.4
0.2
0
8
Ta=85℃
0.4
SPEC
Ta=25℃
Ta=85℃
Ta=25℃
Ta=-40℃
4
0.2
Ta=85℃
Ta=25℃
Ta=-40℃
Ta=-40℃
0
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
IOL2[mA]
VCC[V]
VCC[V]
Fig.7 "L" Output Voltage VOL2-IOL2
(VCC=1.7V)
Fig.9 Input Leakage Current ILI2
(WP)
Fig.8 Input Leakage Current ILI1
(A0,A1,A2,SCL,SDA)
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
4/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
2.5
2
0.6
0.5
0.4
0.3
0.2
0.1
0
3.5
SPEC1
SPEC
SPEC
3
2.5
fSCL=400kHz(VCC≧2.5V)
fSCL=100kHz(1.7V≦Vcc<2.5V)
fSCL=100kHz
1.5
1
DATA=AAh
2
DATA=AA
Ta=85℃
1.5
SPEC2
Ta=25℃
1
Ta=85℃
Ta=25℃
Ta=25℃
Ta=85℃
Ta=-40℃
0.5
0
0.5
Ta=-40℃
Ta=-40℃
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.11 Read Operating Current ICC3
(fSCL=400kHz)
Fig.12 Standby Current ISB
Fig.10 Write Operating Current ICC1,2
(fSCL=100kHz,400kHz)
5
10000
5
4
3
2
1
0
Ta=85℃
Ta=25℃
SPEC2
SPEC2
Ta=-40℃
4
3
1000
SPEC1
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2
100
SPEC2:STANDARD-MODE
Ta=85℃
Ta=25℃
2
SPEC1
Ta=25℃
Ta=-40℃
Ta=85℃
Ta=-40℃
10
SPEC1
1
0
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
1
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.15 Data Clock Low Period tLow
Fig.13 Clock Frequency fSCL
Fig.14 Data Clock High Period tHigh
5
5
50
SPEC2
SPEC1,2
SPEC2
4
4
0
Ta=85℃
Ta=25℃
3
3
-50
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
Ta=-40℃
2
2
-100
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1
SPEC1
1
0
1
0
-150
-200
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.16 Start Condition Hold Time
tHD:STA
Fig.
Fig.18 Data Hold Time
tHD:DAT(High)
Start Condition Setup Time
300
50
0
300
200
100
0
SPEC2
SPEC1,2
200
100
0
SPEC1
Ta=85℃
Ta=25℃
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-50
Ta=85℃
Ta=-40℃
-100
-150
-200
Ta=85℃
Ta=25℃
-100
-200
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-100
-200
Ta=25℃
Ta=-40℃
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
Ta=-40℃
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.19 Data Hold Time
tHD:DAT(LOW)
Fig.20 Input Data Setup Time
tSU:DAT(HIGH)
Fig.21 Input Data Setup Time
tSU:DAT(LOW)
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2011.11 - Rev.A
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© 2011 ROHM Co., Ltd. All rights reserved.
BR34E02FVT-3,BR34E02NUX-3
Technical Note
4
3
2
1
0
4
5
4
3
2
1
0
SPEC2
SPEC2
3
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
Ta=85℃
Ta=25℃
Ta=85℃
Ta=85℃
SPEC1
Ta=25℃
SPEC2
Ta=25℃
SPEC1
SPEC2
1
0
Ta=-40℃
Ta=-40
℃
Ta=-40℃
SPEC1
1
SPEC1
1
0
1
2
VCC[V]
3
4
0
2
3
4
0
2
3
4
VCC[V]
VCC[V]
Fig.23 Output Data Hold Time
tDH
Fig.24 Stop Condition Setup Time
tSU:STO
Fig.22 Output Data Delay Time
tPD
0.6
5
6
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC2
SPEC1,2
0.5
5
4
3
2
1
0
Ta=-40℃
Ta=25℃
0.4
0.3
0.2
0.1
0
Ta=25℃
4
3
2
1
0
Ta=-40℃
Ta=85℃
Ta=85℃
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1,2
SPEC1
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.27 Noise Spike Width
tI(SCL H)
Fig.25 Bus Free Time
tBUF
Fig.26 Write Cycle Time
tWR
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
0.5
0.4
0.3
0.2
0.1
0
Ta=-40℃
Ta=25℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=85℃
Ta=25℃
Ta=85℃
SPEC1,2
SPEC1,2
SPEC1,2
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
VCC[V]
Fig.28 Noise Spike Width
tI(SCL L)
Fig.29 Noise Spike Width
tI(SDA H)
Fig.30 Noise Spike Width
tI(SDA L)
0.2
1.2
SPEC1,2
SPEC1,2
1
0.8
0.6
0.4
0
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-0.2
Ta=25℃
Ta=85℃
-0.4
Ta=-40℃
Ta=25℃
0.2
0
Ta=85℃
Ta=-40℃
-0.6
0
1
2
3
4
0
1
2
3
4
VCC[V]
VCC[V]
Fig.32 WP High Period
tHigh:WP
Fig.31 WP Setup Time
tSU:WP
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BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Data transfer on the I2C BUS
○Data transfer on the I2C BUS
The BUS is considered to be busy after the START condition and free a certain time after the STOP condition.
Every SDA byte must be 8-bits long and requires an ACKNOWLEDGE signal after each byte. The devices have Master
and Slave configurations. The Master device initiates and ends data transfer on the BUS and generates the clock signals
in order to permit transfer.
The EEPROM in a slave configuration is controlled by a unique address. Devices transmitting data are referred to as the
Transmitter. The devices receiving the data are called Receiver.
○START Condition (Recognition of the START bit)
・All commands are proceeded by the start condition, which is a High to Low transition of SDA when SCL is High.
・The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met. (See Fig.1-(b) START/STOP Bit Timing)
○STOP Condition (Recognition of STOP bit)
・All communications must be terminated by a stop condition, which is a Low to High transition of SDA when SCL is High.
(See Fig.1-(b) START/STOP Bit Timing)
○Write Protect By Soft Ware
・Set Write Protect command and permanent set Write Protect command set data of 00h~7Fh in 256 words write
protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect
command. Cancel of write protection block which is set by permanent set Write Protect command at once is
impossibility. When these commands are carried out, WP pin must be OPEN or GND.
○Acknowledge
・Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS after
transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the µ-COM.
When outputting the data during read operation, the Transmitter is the EEPROM.
・During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been
received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When outputting
the data during read operation the receiver is the µ-COM.)
・The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).
・In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word (word
address and write data).
・In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an Acknowledge.
・If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit
the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP
condition before returning to standby mode.
○Device Addressing
・Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits
of the slave address are the “device type indentifier.” For this EEPROM it is “1010.” (For WP register access this code
is "0110".)
・The next three bits identify the specified device on the BUS (device address). The device address is defined by the state
of the A0,A1 and A2 input pins. This IC works only when the device address input from the SDA pin corresponds to the
status of the A0,A1 and A2 input pins. Using this address scheme allows up to eight devices to be connected to the
BUS.
・The last bit of the stream (R/W…READ/WRITE) determines the operation to be performed.
R/W=0 ・・・・
R/W=1 ・・・・
WRITE (including word address input of Random Read)
READ
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2011.11 - Rev.A
7/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
Slave Address Set Pin Device Type Device Address Read Write Mode
Access Area
A2
A2
A1
A1
A0
A0
1010
A2 A1 A0
A2 A1 A0
R / W
R / W
R / W
R / W
2kbit Access to Memory
Access to Permanent Set Write
Protect Memory
GND
GND
GND VHV
Vcc VHV
0110
0
0
0
1
1
1
Access to Set Write Protect Memroy
Access to Clear Write Protect Memory
○WRITE PROTECT PIN(WP)
When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level),
it is enable to write 256 words (all address).
If permanent protection is done by Write Protect command, lower half area (00~7Fh address) is inhibited writing
regardless of WP pin state.
WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use.
○Confirm Write Protect Resistor by ACK
According to state of Write Protect Resistor, ACK is as follows.
State of Write
Protect Registor Input
WP
Write
Cycle(tWR)
Input Command
ACK
Address
ACK
Data
-
ACK
PSWP,SWP,CWP
No ACK
ACK
-
No ACK
ACK
No ACK
No
No
In case,
protect by PSWP
-
Page or Byte Write
WA7~WA0
D7~D0 No ACK
(00~7Fh)
SWP
CWP
No ACK
ACK
-
-
-
No ACK
ACK
-
-
-
No ACK
ACK
No
Yes
Yes
0
PSWP
ACK
ACK
ACK
Page or Byte Write
ACK
WA7~WA0
ACK
D7~D0 No ACK
No
In case,protect by
SWP
(00~7Fh)
SWP
No ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
-
No ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
-
-
-
No ACK
No ACK
No ACK
No
No
CSP
-
1
PSWP
-
No
Page or Byte Write
PSWP, SWP, CWP
Page or Byte Write
PSWP, SWP, CWP
Page or Byte Write
WA7~WA0
D7~D0 No ACK
No
-
-
ACK
ACK
Yes
Yes
No
0
WA7~WA0
-
D7~D0
In case,
Not protect
1
-
No ACK
WA7~WA0
D7~D0 No ACK
No
Acknowledge when writing data or defining the write-protection(instructions with R/W bit=0)
- is Don’t Car
State of Write Protect Registor
In case, protect by PSWP
Command
PSWP, SWP, CWP
SWP
ACK
No ACK
No ACK
ACK
Address
ACK
Data
ACK
-
-
-
-
-
No ACK
No ACK
No ACK
No ACK
No ACK
-
-
-
-
-
NoACK
No ACK
No ACK
No ACK
No ACK
In case, protect by SWP
CWP
PSWP
ACK
Case, Not protect
PSWP, SWP, CWP
ACK
Acknowledge when reading data the write-protection(instructions with R/W bit=1)
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
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BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Command
○Write Cycle
During WRITE CYCLE operation data is written in the EEPROM. The Byte Write Cycle is used to write only one byte. In
the case of writing continuous data consisting of more than one byte, Page Write is used. The maximum bytes that can
be written at one time is 16 bytes.
S
T
A
R
T
W
R
I
T
E
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
DATA
SDA
LINE
WA
7
WA
0
1
0
1
0 A2A1A0
D7
D0
A
C
K
A
C
K
R
/
W
A
C
K
Fig.33 Byte Write Cycle Timing
S
T
A
R
T
W
R
I
T
E
S
T
O
SLAVE
ADDRESS
W ORD
ADDRESS(n)
DATA(n)
DATA(n+15)
P
SDA
LINE
W A
7
W A
0
1
0 1 0 A2A1A0
D7
D0
D0
A
C
K
R A
A
C
K
A
C
K
/
C
W K
Fig.34 Page Write Cycle Timing
・With this command the data is programmed into the indicated word address.
・When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
・Once programming is started no commands are accepted for tWR (5ms max.).
・This device is capable of 16-byte Page Write operations.
・If the Master transmits more than 16 words prior to generating the STOP condition, the address counter will “roll over”
and the previously transmitted data will be overwritten.
・When two or more byte of data are input, the four low order address bits are internally incremented by one after the
receipt of each word, while the four higher order bits of the address (WA7~WA4) remain constant.
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
9/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Command
○Read Cycle
During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle and
Current Read Cycle. The Random Read Cycle reads the data in the indicated address.
The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the
Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With the
Sequential Read Cycle it is possible to continuously read the next data.
It is necessary to input
“High” at last ACK timing.
W
R
I
T
E
S
T
A
R
T
S
T
A
R
T
R
E
A
D
S
T
O
SLAVE
ADDRESS
SLAVE
ADDRESS
W ORD
ADDRESS(n)
DATA(n)
P
SDA
LINE
W A
7
W A
0
1
0
1
0 A2A1A0
1
0 1 0 A2A1A0
D7
D0
A
C
K
R A
/ C
W K
A
C
K
R A
/
C
W K
Fig.35 Random Read Cycle Timing
S
T
A
R
T
S
T
O
R
E
A
D
SLAVE
ADDRESS
It is necessary to input
“High” at last ACK timing.
DATA
P
SDA
LINE
1
0
1
0 A2A1A0
D7
D0
A
C
K
R
/
W
A
C
K
Fig.36 Current Read Cycle Timing
・Random Read operation allows the Master to access any memory location indicated by word address.
・In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal
address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the
next word address (n+1).
・If an Acknowledge is detected and no STOP condition is generated by the Master (µ-COM), the device will continue to
transmit data. (It can transmit all data (2kbit 256word))
・If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to standby mode.
・If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read, and
the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read input
Acknowledge with "High" always, then input a STOP condition.
S
T
A
R
T
R
E
A
D
S
T
O
P
It is necessary to
input “High” at
last ACK timing.
SLAVE
ADDRESS
DATA(n)
DATA(n+x)
SDA
LINE
1
0
1
A2A1A0
D7
D0
D7
D0
0
A
C
K
R A
A
C
K
A
C
K
/
C
W K
Fig.37 Sequential Read Cycle Timing (With Current Read)
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2011.11 - Rev.A
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© 2011 ROHM Co., Ltd. All rights reserved.
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Write Protect Cycle
W
R
I
T
E
S
T
A
S
T
O
W ORD
ADDRESS
SLAVE
R
DATA
ADDRESS
T
P
SDA
LINE
0
1
1
A2A1A0
*
*
*
*
0
A
C
K
R A
A
C
K
/
C
W P
W K
*:DON’T CARE
Fig. 38 Permanent Set Write Protect Cycle
・Permanent set Write Protect command set data of 00h~7Fh in 256 words write protection block. Cancel of write
protection block which is set by permanent set Write Protect command at once is impossibility. When these commands
are carried out, WP pin must be OPEN or GND.
・Permanent Set Write Protect command needs tWR from stop condition same as Byte Write and Page Write, During tWR,
input command is canceled.
・Refer to P8 about reply of ACK in each protect state.
W
R
I
T
E
S
T
A
R
T
S
T
O
W ORD
ADDRESS
SLAVE
ADDRESS
DATA
P
SDA
LINE
0
1
1
0
0
0 1
*
*
*
*
A
C
K
R A
A
C
K
/
C
W P
W K
*:DON’T CARE
Fig. 39 Set Write Protect Cycle
・Set Write Protect command set data of 00h~7Fh in 256 words write protection block. Clear Write Protect command can
cancel write protection block which is set by set write Protect command. When these commands are carried out, WP
pin must be OPEN or GND.
・Set write Protect command needs tWR from stop condition same as Byte Write and Page Write, During tWR, input
command is canceled.
・Refer to P8 about reply of ACK in each protect state.
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11/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
W
R
I
T
E
S
T
A
S
T
O
W ORD
ADDRESS
SLAVE
R
DATA
ADDRESS
T
P
SDA
LINE
0
1
1
0
0
1 1
*
*
*
*
A
C
K
R A
A
C
K
/
C
W P
W K
*:DON’T CARE
Fig. 40 Clear Write Protect Cycle
・Clear Write Protect command can cancel write protection block which is set by set write Protect command. When these
commands are carried out, WP pin must be OPEN or GND.
・Clear Write Protect command needs tWR from stop condition same as Byte Write and Page Write, During tWR, input
command is canceled.
・Refer to P8 about reply of ACK in each protect state.
●Software Reset
Execute software reset in the event that the device is in an unexpected state after power up and/or the command input
needs to be reset. Below are three types(Fig. 41–(a), (b), (c)) of software reset:
During dummy clock, release the SDA BUS (tied to VCC by a pull-up resistor). During this time the device may pull the SDA
line Low for Acknowledge or the outputting of read data.If the Master sets the SDA line to High, it will conflict with the device
output Low, which can cause current overload and result in instantaneous power down, which may damage the device.
DUMMY CLOCK×14
13
START×2
SCL
2
14
COMMAND
COMMAND
1
SDA
Fig.41-(a) DUMMY CLOCK×14 + START+START
START
DUMMY CLOCK×9
START
SCL
2
8
9
1
COMMAND
COMMAND
SDA
Fig.41-(b) START + DUMMY CLOCK×9 + START
START×9
SCL
3
7
2
8
9
1
COMMAND
COMMAND
SDA
Fig.41-(c) START×9
* COMMAND starts with start condition.
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
12/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Acknowledge polling
Since the IC ignores all input commands during the internal write cycle, no ACK signal will be returned.
When the Master sends the next command after the Write command, if the device returns an ACK signal it means that the
program is completed. No ACK signal indicates that the device is still busy.
Using Acknowledge polling decreases the waiting time by tWR=5ms.
When operating Write or Current Read after Write, first transmit the Slave address (R/W is"High" or "Low"). After the
device returns the ACK signal continue word address input or data output.
During the internal write cycle,
no ACK will be returned.
(ACK=High)
THE FIRST WRITE COMMAND
S
S
T
A
R
T
S
T
A
R
T
S
A
C
K
H
A
T
・・・
SLAVE
SLAVE
ADDRESS
T
C
K
H
A
R
T
WRITE COMMAND
ADDRESS
O
P
tWR
THE SECOND WRITE COMMAND
S
T
A
R
T
S
T
A
R
T
・・・
A
C
K
A
A
C
K
L
A
C
K
S
T
O
SLAVE
SLAVE
WORD
C
DATA
ADDRESS
K
ADDRESS
ADDRESS
H
After the internal write cycle
tWR
is completed, ACK will be returned
(ACK=Low). Then input next
Word Address and data.
Fig.42 Successive Write Operation By Acknowledge Polling
●WP effective timing
WP is normally fixed at "H" or "L". However, in case WP needs to be controlled in order to cancel the Write command, pay
attention to “WP effective timing” as follows:
The Write command is canceled by setting WP to "H" within the WP cancellation effective period.
The period from the START condition to the rising edge of the clock (which takes in the data D0 - the first byte of the Page
Write data) is the ‘invalid cancellation period’. WP input is considered inconsequential during this period. The setup time for
the rising edge of the SCL, which takes in D0, must be more than 100ns.
The period from the rising edge of SCL (which takes in the data D0) to the end of internal write cycle (tWR) is the ‘effective
cancellation period’. When WP is set to "H" during tWR, Write operation is stopped, making it necessary to rewrite t
he data.
It is not necessary to wait for tWR (5ms max.) after stopping the Write command by WP because the device is in standby
mode.
・The rising edge of the clock
which take in D0
SCL
SDA
・The rising edge
・of SDA
SCL
SDA
ACK
D0
D1
D0
ACK
AN ENLARGEMENT
AN ENLARGEMENT
S
T
A
R
T
A
C
K
L
A
C
K
L
tWR
A
C
K
L
S
T
O
P
A
C
K
L
SLAVE
ADDRESS
WORD
SDA
WP
DATA
D7 D6 D5
D2 D1 D0
D4 D3
ADDRESS
WP cancellation
invalid period
WP cancellation
effective period
Stop of the write
operation
No data will be written
Data is not
guaranteed
Fig.43 WP effective timing
13/19
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Command cancellation from the START and STOP conditions
Command input is canceled by successive inputs of START and STOP conditions. (Refer to Fig.42)
However, during ACK or data output, the device may set the SDA line to Low, making operation of the START and STOP
conditions impossible, and thus preventing reset. In this case execute reset by software. (Refer to Fig.39)
The internal address counter will not be determined when operating the Cancel command by the START and STOP
conditions during Random, Sequential or Current Read. Operate a Random Read in this case.
SCL
SDA
1
0
1
0
STOP
START
CONDITION
CONDITION
Fig.44 Command cancellation by the START and STOP conditions during input of the Slave Address
●I/O Circuit
○SDA Pin Pull-up Resistor
A pull-up resistor is required because SDA is an NMOS open drain. Determine the resistor value of (RPU) by considering
the VIL and IL, and VOL-IOL characteristics. If a large RPU is chosen, the clock frequency needs to be slow. A smaller
RPU will result in a larger operating current.
○Maximum RPU
The maximum of RPU can be determined by the following factors.
①The SDA rise time determined by RPU and the capacitance of the BUS line(CBUS) must be less than tR.
In addition, all other timings must be kept within the AC specifications.
②When the SDA BUS is High, the voltage Ⓐ at the SDA BUS is determined from the total input leakage(IL) of all
devices connected to the BUS. RPU must be higher than the input High level of the microcontroller and the device,
including a noise margin 0.2VCC.
BR34E02
VCC-ILRPU-0.2 VCC ≧ VIH
0.8VCC-V
Microcontroller
IH
RPU
RPU
∴
≦
IL
SDA PIN
A
Examples: When VCC =3V, IL=10µA, VIH=0.7 VCC
According to ②
IL
IL
0.8×3-0.7×3
10×10-6
RPU
≦
≦
THE CAPACITANCE
OF BUS LINE (CBUS)
300
k
[ Ω]
Fig.45 I/O Circuit
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
14/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
○Minimum RPU
The minimum value of RPU is determined by following factors.
②ꢀ
Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.
VCC-VOL
IOL
≦
RPU
RPU
VCC-VOL
IOL
∴
≧
②VOLMAX=0.4V must be lower than the input Low level of the micro controller and the EEPROM
including the recommended noise margin of 0.1VCC.
VOLMAX ≦ VIL-0.1 VCC
Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the micro controller and the EEPROM is VIL=0.3VCC,
3-0.4
3×10 -3
According to ①
RPU
≧
≧
867
[Ω]
and
And
VOL=0.4[V]
VIL=0.3×3
=0.9[V]
so that condition ② is met
○SCL Pin Pull-up Resistor
When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required.
However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended.
Several kΩ are recommended for the pull-up resistor in order to drive the output port of the microcontroller.
●A0, A1, A2, WP Pin connections
○ Device Address Pin (A0, A1, A2) connections
The status of the device address pins is compared with the device address sent by the Master. One of the devices that is
connected to the identical BUS is selected. Pull up or down these pins or connect them to VCC or GND. Pins that are not
used as device address (N.C.Pins) may be High, Low, or Hi-Z.
○ WP Pin connection
The WP input allows or prohibits write operations. When WP is High, only Read is available and Write to all address is
prohibited. Both Read and Write are available when WP is Low.
In the event that the device is used as a ROM, it is recommended that the WP input be pulled up or connected to VCC.
When both READ and WRITE are operated, the WP input must be pulled down or connected to GND or controlled.
●Microcontroller connection
○Concerning Rs
The open drain interface is recommended for the SDA port in the I2C BUS. However, if the Tri-state CMOS interface is
applied to SDA, insert a series resistor (Rs) between the SDA pin of the device and the pull up resistor RPU is
recommended, since it will serve to limit the current between the PMOS of the microcontroller, and the NMOS of the
EEPROM. Rs also protects the SDA pin from surges. Therefore, Rs is able to be used though open drain inout of the
SDA port.
ACK
SCL
RPU
RS
SDA
'H'OUTPUT OF
MICRO
“L” OUTPUT OF EEPROM
MICRO CONTROLLER
Fig.46 I/O Circuit
EEPROM
The “H” output of micro controller and the “L” output of
EEPROM may cause current overload to SDA line.
Fig.47 Input/Output Collision Timing
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2011.11 - Rev.A
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BR34E02FVT-3,BR34E02NUX-3
Technical Note
○Rs Maximum
The maximum value of Rs is determined by following factors.
①SDA rise time determined by RPU and the capacitance value of the BUS line (CBUS) of SDA must be less than tR. In
addition, the other timings must be within the timing conditions of the AC.
②When the output from SDA is Low, the voltage of the BUS at
A is determined by RPU, and Rs must be lower than
the input Low level of the microcontroller, including recommended noise margin (0.1VCC).
VCC
IL OL
CC
V -V -0.1V
S
R
PU
R
∴
≦
×
A
CC IL
1.1V -V
RPU
RS
VOL
CC
IL
CC
OL
=0.4V
PU
R =20k
ꢀ
Examples : When V =3V V =0.3V
ꢀ
V
ꢀ
Ω
IOL
0.3×3-0.4-0.1×3
1.1×3-0.3×3
20×103
S
R
According to
≦
≦
×
BUS
CAPACITANCE
②
1.67
k
[ Ω]
VIL
EEPROM
MICRO CONTROLLER
Fig.48 I/O Circuit
○Rs Minimum
The minimum value of Rs is determined by the current overload during BUS conflict.
Current overload may cause noises in the power line and instantaneous power down.
The following conditions must be met, where “I” is the maximum permissible current, which depends on the Vcc line
impedance as well as other factors. “I” current must be less than 10mA for EEPROM.
Vcc
S
R
≦
≧
I
Vcc
I
S
∴ R
RPU
CC
Examples: When V =3V, I=10mA
"L" OUTPUT
RS
3
S
R
≧
≧
10×10-3
MAXIMUM
CURRENT
"H" OUTPUT
300
[Ω]
MICRO CONTROLLER
Fig.49 I/O Circuit
EEPROM
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
16/19
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●I2C BUS Input / Output equivalent circuits
○Input (A0,A2,SCL)
Fig.50 Input Pin Circuit
○Input / Output (SDA)
Fig.51 Input / Output Pin Circuit
○Input (A1)
Fig.52 Input Pin Circuit
○Input (WP)
Fig.53 Input Pin Circuit
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BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Power Supply Notes
VCC increases through the low voltage region where the internal circuit of IC and the microcontroller are unstable. In order
to prevent malfunction, the IC has P.O.R and LVCC functionality. During power up, ensure that the following conditions are
met to guaranty P.O.R. and LVCC operability.
1. "SDA='H'" and "SCL='L' or 'H'".
2. Follow the recommended conditions of tR, tOFF, Vbot so that P.O.R. will be activated during power up.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tR
tOFF
Vbot
Below 10ms Above 10ms Below 0.3V
Below 100ms Above 10ms Below 0.2V
tOFF
Vbot
0
Fig.54 VCC rising wavefrom
3. Prevent SDA and SCL from being "Hi-Z".
In case that condition 1. and/or 2. cannot be met, take following actions.
A) If unable to keep Condition 1 (SDA is "Low" during power up)
→Make sure that SDA and SCL are "High" as in the figure below.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH tSU:DAT
tSU:DAT
Fig.55 SCL="H" and SDA="L"
Fig.56 SCL="L" and SDA="L"
B) If unable to keep Condition 2
→After the power stabilizes, execute software reset. (See page 9,10)
C) If unable to keep either Condition 1 or 2
→Follow Instruction A first, then B
●LVCC Circuit
The LVCC circuit prevents Write operation at low voltage and prevents inadvertent writing. A voltage below the LVCC voltage
(1.2V typ.) prohibits Write operation.
●VCC Noise
○Bypass Capacitor
Noise and surges on the power line may cause abnormal function. It is recommended that bypass capacitors (0.1µF) be
attached between VCC and GND externally.
●Cautions On Use
1) Descrived numeric values and data are design representative values, and the values are not guaranteed.
2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics
further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with
sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external
parts and our LSI.
3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it
that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that
of GND terminal.
5) Heat design
In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.
6) Terminal to terminal short circuit and wrong packaging
When to package LSI on to a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
7) Use in a strong electromagnetic field may cause malfunction, therfore, evaluate design sufficiently.
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2011.11 - Rev.A
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© 2011 ROHM Co., Ltd. All rights reserved.
BR34E02FVT-3,BR34E02NUX-3
Technical Note
●Ordering part number
B R
3 4
F V T
-
3
E 2
E 0 2
Part No.
BR
Part No.
34E02
Package
FVT: TSSOP-B8
NUX: VSON008X2030
Packaging and forming specification
E2: Embossed tape and reel
TR: Embossed tape and reel
TSSOP-B8
<Tape and Reel information>
3.0± 0.1
(MAX 3.35 include BURR)
Tape
Embossed carrier tape
4 ± ±4
8
7
6
5
Quantity
3000pcs
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
2
3
4
1PIN MARK
+0.05
0.145
−0.03
0.525
S
0.08 S
+0.05
0.245
M
−0.04
0.08
Direction of feed
1pin
0.65
Reel
(Unit : mm)
Order quantity needs to be multiple of the minimum quantity.
∗
VSON008X2030
<Tape and Reel information>
2.0± 0.1
Tape
Embossed carrier tape
Quantity
4000pcs
TR
1PIN MARK
Direction
of feed
S
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
0.08
S
1.5± 0.1
0.5
C0.25
1
4
8
5
0.25
Direction of feed
1pin
+0.05
−0.04
0.25
Reel
Order quantity needs to be multiple of the minimum quantity.
∗
(Unit : mm)
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.11 - Rev.A
19/19
Notice
N o t e s
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, commu-
nication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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The Products are not designed or manufactured to be used with any equipment, device or
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© 2011 ROHM Co., Ltd. All rights reserved.
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A
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