BR34E02FVT-W_09_技术文档

Memory for Plug & Play

DDR/DDR2

(For memory module) SPD Memory

BR34E02FVT-W, BR34E02NUX-W

No.09002EAT03

●Description

BR34E02FVT-W is 256×8 bit Electrically Erasable PROM (Based on Serial Presence Detect)

●Features

1) 256×8 bit architecture serial EEPROM

2) Wide operating voltage range: 1.7V-3.6V

3) Two-wire serial interface

4) High reliability connection using Au pads and Au wires

5) Self-Timed Erase and Write Cycle

6) Page Write Function (16byte)

7) Write Protect Mode

Settable Reversible Write Protect Function: 00h-7Fh

Write Protect 1 (Onetime Rom)

Write Protect 2 (Hardwire WP PIN)

: 00h-7Fh

: 00h-FFh

8) Low Power consumption

Write (at 1.7V ) :

Read (at 1.7V ) :

Standby ( at 1.7V ) :

9) DATA security

0.4mA (typ.)

0.1mA(typ.)

0.1µA(typ.)

Write protect feature (WP pin)

Inhibit to WRITE at low VCC

10)Compact package: TSSOP-B8, VSON008X2030

11)High reliability fine pattern CMOS technology

12)Rewriting possible up to 1,000,000 times

13)Data retention: 40 years

14)Noise reduction Filtered inputs in SCL / SDA

15)Initial data FFh at all addresses

●BR34E02-W Series

Capacity

2Kbit

Bit format

256X8

Type

BR34E02-W

Power Source Voltage

TSSOP-B8

●

VSON008X2030

●

1.7V～3.6V

●Absolute Maximum Ratings (Ta=25℃)

Parameter

Symbol

VCC

Rating

Unit

V

Supply Voltage

-0.3～+6.5

330(BR34E02FVT-W)

300(BR34E02NUX-W)

-65～+125

*1

*2

Power Dissipation

Pd

mW

Storage Temperature

Operating Temperature

Terminal Voltage (A0)

Tstg

Topr

-

℃

V

-40～+85

-0.3～10.0

-0.3～VCC+0.3

Terminal Voltage (etcetera)

V

* Reduce by 3.3mW(*1), 3.0 mW(*2)/C over 25C

●Recommended operating conditions

Parameter

Symbol

VCC

ＶIN

Rating

1.7～3.6

0～VCC

Unit

V

Supply Voltage

Input Voltage

www.rohm.com

2009.04 - Rev.A

1/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Memory cell characteristics(Ta=25℃, VCC=1.7V～3.6V)

Specification

Parameter

Unit

Min.

1,000,000

40

Typ.

-

Max.

-

*1

Write / Erase Cycle

Data Retention

Cycles

Years

*1:Not 100% TESTED

●Electrical characteristics - DC(Unless otherwise specified Ta=-40℃～+85℃, VCC=1.7V～3.6V)

Specification

Parameter

Symbol

Unit

Test Condition

Min.

Typ.

Max.

Vcc+0.3

0.3 VCC

0.4

"H" Input Voltage

"L" Input Voltage

VIH1

VIL1

VOL1

VOL2

ILI1

ILI2

ILI3

ILO

0.7 VCC

-

V

-

-0.3

-

-1

"L" Output Voltage 1

"L" Output Voltage 2

Input Leakage Current 1

Input Leakage Current 2

Input Leakage Current 3

Output Leakage Current

IOL=2.1mA，2.5V≦VCC≦3.6V(SDA)

IOL=0.7mA，1.7V≦VCC＜2.5V(SDA)

0.2

1

15

20

µA VIN=0V～VCC(A0,A1,A2,SCL)

µA VIN=0V～VCC(WP)

µA VIN=VHV(A0)

1

µA VOUT=0V～VCC

VCC=1.7V,fSCL=100kHz，tWR=5ms

Byte Write

Page Write

Write Protect

VCC =3.6V,fSCL=100kHz, tWR=5ms

Byte Write

Page Write

Write Protect

VCC =3.6V,fSCL=100kHz

ICC1

ICC2

ICC3

-

1.0

3.0

0.5

mA

Operating Current

mA

Random Read

Current Read

mA

Sequential Read

VCC =3.6V,SDA,SCL= VCC

A0,A1,A2=GND,WP=GND

VHV-Vcc≧4.8V

Standby Current

A0 HV Voltage

ISB

-

2.0

10

µA

VHV

7

V

○Note: This IC is not designed to be radiation-resistant.

●lectrical characteristics - AC(Unless otherwise specified Ta=-40℃～+85℃, VCC =1.7V～3.6V)

FAST-MODE

2.5V≦VCC≦5.5V

STANDARD-MODE

1.7V≦VCC≦5.5V

Parameter

Symbol

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Clock Frequency

fSCL

tHIGH

tLOW

tR

-

0.6

1.2

-

400

-

0.3

-

4.0

4.7

-

100

-

1.0

0.3

-

kHz

µs

ns

µs

ms

Data Clock High Period

Data Clock Low Period

SDA and SCL Rise Time

SDA and SCL Fall Time

Start Condition Hold Time

Start Condition Setup Time

Input Data Hold Time

Input Data Setup Time

Output Data Delay Time

Output Data Hold Time

Stop Condition Setup Time

Bus Free Time

*1

tF

-

tHD:STA

tSU:STA

tHD:DAT

tSU:DAT

tPD

tDH

tSU:STO

tBUF

0.6

0

100

0.1

0.6

1.2

-

4.0

4.7

0

250

0.1

4.0

4.7

-

0.9

-

5

3.5

-

5

Write Cycle Time

tWR

Noise Spike Width (SDA

and SCL)

tI

-

0.1

-

0.1

µs

WP Hold Time

WP Setup Time

WP High Period

tHD：WP

tSU：WP

tHIGH：WP

0

0.1

1.0

-

0

0.1

1.0

-

ns

µs

*1：Not 100％ TESTED

www.rohm.com

2009.04 - Rev.A

2/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

■Fast / Standard Modes

Fast mode and Standard mode differ only in operation frequency. Operations performed at 100kHz are considered in

"Standard-mode", while those conducted at 400kHz are in "Fast-mode".

Please note that these clock frequencies are maximum values. At lower power supply voltage it is difficult to operate at high speeds.

The EEPROM can operate at 400kHz, between 2.5V and 3.6V, and at 100kHz from 1.7V-2.5V.

●Synchronous Data Timing

tR

tF

tHIGH

SCL

SDA

tSU:DAT

tLOW

tPD

tHD:STA

tBUF

tHD:DAT

tSU:STA

tHD:STA

tSU:STO

SDA

(IN)

tDH

SDA

(OUT)

START BIT

STOP BIT

Fig.1-(b) Start/Stop Bit Timing

Fig.1-(a) Synchronous Data Timing

○SDA data is latched into the chip at the rising edge ○

of SCL clock.

○Output data toggles at the falling edge of SCL clock.

SCL

SDA

DATA(1)

D1 D0 ACK

DATA(n)

ACK

SDA

WP

ｔWR

D0

ACK

Stop Condition

tWR

WRITE DATA(n)

STOP CONDITION

START CONDITION

tSU：WP

ｔHD：WP

Fig.1-(d) WP Timing Of The Write Operation

Fig.1-(c) Write Cycle Timing

SCL

SDA

WP

DATA(n)

DATA(1)

D1 D0 ACK

ACK

tHIGH:WP

tWR

Fig.1-(e) WP Timing Of The Write Cancel Operation

○For WRITE operation, WP must be "Low" from the rising edge of the

clock (which takes in D0 of first byte) until the end of tWR. (See

Fig.1-(d) ) During this period, WRITE operation can be canceled by

setting WP "High".（See Fig.1-(e)）

○When WP is set to "High" during tWR, WRITE operation is

immediately ceased, making the data unreliable. It must then be

re-written.

www.rohm.com

2009.04 - Rev.A

3/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Block diagram

PROTECT_MEMORY_ARRY

2Kbit_MEMORY_ARRY

A0 1

8 VCC

7 WP

6 SCL

5 SDA

8bit

ADDRESS

DECODER

SLAVE , WORD

DATA

REGISTE

A1 2

A2 3

8bit

ADDRESS

START

STOP

CONTOROL LOGIC

ACK

HIGH VOLTAGE

VCC LEVEL

GND 4

Fig.2 Blo

●Pinout diagram and description

Pin Name

Input/Output

Functions

VCC

GND

-

Power Supply

Ground 0V

A0 1

8 V_CC

7 WP

6 SCL

5 SDA

-

A0,A1,A2

SCL

IN

Slave Address Set.

Serial Clock Input

A1 2

BR34E02FVT-W

BR34E02NUX-W

A2 3

*1

Slave and Word Address,

SDA

IN / OUT

Serial Data Input, Serial Data Output

GND 4

*2

WP

IN

Write Protect Input

*1 Open drain output requires a pull-up resistor.

*2 WP Pin has a Pull-Down resistor. Please leave unconnected or

connect to GND when not in use.

Fig.3 Pin Configuration

●Electrical characteristics curves

The following characteristic data are typ. value.

6

5

4

3

2

1

0

1

0.8

0.6

0.4

0.2

0

SPEC

Ta=85℃

Ta=-40℃

Ta=25℃

SPEC

Ta=85℃

Ta=-40℃

Ta=25℃

SPEC

Ta=-40℃

0

1

2

3

4

0

1

2

3

4

VCC[V]

IOL1[mA]

Fig.5 "L" Input Voltage VIL

Fig.4 "H" Input Voltage VIH

(A0,A1,A2,SCL,SDA,WP)

Fig.6 "L" Output Voltage VOL1-IOL1

(VCC=2.5V)

(A0,A1,A2,SCL,SDA,WP)

1

0.8

0.6

1.2

1

16

SPEC

12

0.8

0.6

0.4

0.2

0

8

Ta=85℃

0.4

Ta=25℃

SPEC

Ta=85℃

Ta=25℃

Ta=-40℃

4

0.2

0

Ta=85℃

Ta=25℃

Ta=-40℃

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

IOL2[mA]

VCC[V]

Fig.7 "L" Output Voltage VOL2-IOL2

(VCC=1.7V)

Fig.9 Input Leakage Current ILI2

(WP)

Fig.8 Input Leakage Current ILI1

(A0,A1,A2,SCL,SDA)

www.rohm.com

2009.04 - Rev.A

4/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

0.6

0.5

0.4

0.3

0.2

0.1

0

3.5

2.5

2

SPEC1

SPEC

3

2.5

ｆSCL=400kHz(VCC≧2.5V)

fSCL=100kHz(1.7V≦Vcc＜２．５V)

fSCL=100kHz

DATA=AAh

1.5

1

2

1.5

1

DATA=AA

Ta=85℃

SPEC2

Ta=25℃

Ta=85℃

Ta=-40℃

0.5

0

Ta=85℃

Ta=25℃

Ta=-40℃

0.5

0

Ta=40℃

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

VCC[V]

Fig.11 Read Operating Current ICC3

(fSCL=400kHz)

Fig.12 Standby Current ISB

Fig.10 Write Operating Current ICC1,2

(fSCL=100kHz,400kHz)

5

10000

5

4

3

2

1

0

Ta=85℃

Ta=25℃

SPEC2

Ta=-40℃

4

1000

3

SPEC1

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

100

SPEC2

2

Ta=85℃

Ta=-40℃

Ta=25℃

Ta=-40℃

SPEC1

10

1

0

Ta=85℃

SPEC1

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

1

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

VCC[V]

Fig.15 Data Clock Low Period tLow

Fig.13 Clock Frequency fSCL

Fig.14 Data Clock High Period tHigh

5

50

5

SPEC2

SPEC1,2

SPEC2

4

0

=85℃

Ta=25℃

Ta=-40℃

3

-50

-100

-150

-200

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

2

Ta=-40℃

Ta=25℃

Ta=85℃

Ta=-40℃

Ta=25℃

Ta=85℃

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

1

0

1

SPEC1

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

VCC[V]

Fig.16 Start Condition Hold Time

tHD:STA

Fig.17 Start Condition Setup Time

tSU:STA

FiagmDag.18 ck DiTarata

HoldimtHD:DAT(High)

300

50

SPEC2

SPEC1

200

100

0

-50

SPEC1,2

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

100

Ta=85℃

SPEC1

Ta=25℃

Ta=-40℃

Ta=85℃

-100

-150

-200

0

Ta=85℃

Ta=25℃

-100

-200

Ta=-40℃

-100

-200

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

Ta=25℃

Ta=-40℃

0

1

2

3

4

0

1

2

3

4

0

1

2

3

4

VCC[V]

Fig.19 Data Hold Time

tHD:DAT(LOW)

Fig.20 Input Data Setup Time

tSU:DAT(HIGH)

Fig.21 Input Data Setup Time

tSU:DAT(LOW)

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2009.04 - Rev.A

5/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

4

3

2

1

0

4

5

4

3

2

1

0

SPEC2

3

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

2

Ta=85℃

Ta=25℃

Ta=-40℃

Ta=85℃

SPEC1

Ta=85℃

Ta=25℃

Ta=-40

℃

SPEC2

Ta=25℃

Ta=-40℃

SPEC1

2

1

0

SPEC2

SPEC1

1

SPEC1

1

0

1

3

4

0

2

3

4

0

2

3

4

VCC[V]

Fig.23 Output Data Hold Time

tDH

Fig.24 Stop Condition Setup Time

tSU:STO

Fig.22 Output Data Delay Time

tPD

0.6

5

6

SPEC1:FAST-MODE

SPEC2

SPEC2:STANDARD-MODE

SPEC1,2

0.5

5

4

Ta=-40℃

0.4

4

Ta=-40℃

Ta=25℃

3

0.3

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

3

Ta=85℃

2

0.2

2

Ta=85℃

SPEC1,2

1

0

SPEC1

2

0.1

Ta=25℃

Ta=-40℃

1

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

0

1

2

3

4

0

1

3

4

0

1

2

3

4

VCC[V]

Fig.27 Noise Spike Width

tI(SCL H)

Fig.25 Bus Free Time

tBUF

Fig.26 Write Cycle Time

tWR

0.6

0.5

0.4

0.3

0.2

0.1

0

0.6

0.5

0.4

0.3

0.2

0.1

0

0.6

0.5

0.4

0.3

0.2

0.1

0

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

Ta=-40℃

Ta=25℃

Ta=-40℃

Ta=25℃

Ta=-40℃

Ta=85℃

Ta=25℃

Ta=85℃

SPEC1,2

3

0

1

2

3

4

0

1

2

4

0

1

2

3

4

VCC[V]

Fig.28 Noise Spike Width

tI(SCL L)

Fig.29 Noise Spike Width

tI(SDA H)

Fig.30 Noise Spike Width

tI(SDA L)

1.2

1

0.2

SPEC1,2

0

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

0.8

0.6

0.4

0.2

0

SPEC1:FAST-MODE

SPEC2:STANDARD-MODE

-0.2

Ta=25℃

Ta=85℃

-0.4

Ta=-40℃

Ta=25℃

Ta=85℃

Ta=-40℃

-0.6

0

1

2

3

4

0

1

2

3

4

VCC[V]

Fig.32 WP High Period

tHigh:WP

Fig.31 WP Setup Time

tSU:WP

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2009.04 - Rev.A

6/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Data transfer on the I²C BUS

○Data transfer on the I²C BUS

The BUS is considered to be busy after the START condition and free a certain time after the STOP condition.

Every SDA byte must be 8-bits long and requires an ACKNOWLEDGE signal after each byte. The devices have Master

and Slave configurations. The Master device initiates and ends data transfer on the BUS and generates the clock signals

in order to permit transfer.

The EEPROM in a slave configuration is controlled by a unique address. Devices transmitting data are referred to as the

Transmitter. The devices receiving the data are called Receiver.

○START Condition (Recognition of the START bit)

・All commands are proceeded by the start condition, which is a High to Low transition of SDA when SCL is High.

・The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command

until this condition has been met. (See Fig.1-(b) START/STOP Bit Timing)

○STOP Condition (Recognition of STOP bit)

・All communications must be terminated by a stop condition, which is a Low to High transition of SDA when SCL is High.

(See Fig.1-(b) START/STOP Bit Timing)

○Write Protect By Soft Ware

・Set Write Protect command and permanent set Write Protect command set data of 00h～7Fh in 256 words write

protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect

command. Cancel of write protection block which is set by permanent set Write Protect command at once is

impossibility. When these commands are carried out, WP pin must be OPEN or GND.

○Acknowledge

・Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS after

transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the µ-COM.

When outputting the data during read operation, the Transmitter is the EEPROM.

・During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been

received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When outputting

the data during read operation the receiver is the µ-COM.)

・The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).

・In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word (word

address and write data).

・In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an Acknowledge.

・If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit

the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP

condition before returning to standby mode.

○Device Addressing

・Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits of the

slave address are the “device type indentifier.” For this EEPROM it is “1010.

” (For WP register access this code is "0110".)

・The next three bits identify the specified device on the BUS (device address).

The device address is defined by the state of the A0,A1 and A2 input pins. This IC works only when the device address

input from the SDA pin corresponds to the status of the A0,A1 and A2 input pins. Using this address scheme allows up

to eight devices to be connected to the BUS.

・The last bit of the stream (R/W…READ/WRITE) determines the operation to be performed.

R/W=0 ････

R/W=1 ････

WRITE (including word address input of Random Read)

READ

Read Write

Slave Address Set Pin Device Type Device Address

Access Area

2kbit Access to Memory

Mode

―

A2

A1

A0

1010

0110

A2 A1 A0

R/W

―

Access to Permanent Set Write Protect Memory

Access to Set Write Protect Memroy

R/W

―

GND

GND VHV

Vcc VHV

0

1

R/W

―

Access to Clear Write Protect MEmory

R/W

www.rohm.com

2009.04 - Rev.A

7/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

○WRITE PROTECT PIN(WP)

When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level),

it is enable to write 256 words (all address).

If permanent protection is done by Write Protect command, lower half area (00～7Fh address) is inhibited writing

regardless of WP pin state.

WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use.

○Confirm Write Protect Resistor by ACK

According to state of Write Protect Resistor, ACK is as follows.

State of Write

Protect Registor

Write

Cycle(tWR)

No

WP Input

-

Input Command

ACK

Address

-

ACK

No ACK

ACK

Data

ACK

PSWP, SWP, CWP No ACK

Page or Byte Write

No ACK

In case,

protect by PSWP

ACK

WA7～WA0

D7～D0 No ACK

No

(00～7Fh)

SWP

CWP

PSWP

No ACK

ACK

-

No ACK

ACK

-

No ACK

ACK

No

Yes

0

1

Page or Byte Write

(00～7Fh)

ACK

WA7～WA0

ACK

D7～D0 No ACK

No

In case,

protect by SWP

SWP

CSP

PSWP

No ACK

ACK

-

No ACK

ACK

-

No ACK

No

Page or Byte Write

PSWP, SWP, CWP

Page or Byte Write

PSWP, SWP, CWP

Page or Byte Write

WA7～WA0

D7～D0 No ACK

No

-

ACK

Yes

No

0

1

WA7～WA0

-

WA7～WA0

D7～D0

In case,

Not protect

-

No ACK

D7～D0 No ACK

No

*- is Don’t Care

State of Write Protect Registor

In case, protect by PSWP

Command

PSWP, SWP, CWP

SWP

CWP

PSWP

PSWP, SWP, CWP

ACK

Address

ACK

No ACK

Data

ACK

No ACK

ACK

-

No ACK

In case, protect by SWP

In case, Not protect

○Write Cycle

During WRITE CYCLE operation data is written in the EEPROM. The Byte Write Cycle is used to write only one byte. In

the case of writing continuous data consisting of more than one byte, Page Write is used. The maximum bytes that can

be written at one time is 16 bytes.

S

T

A

R

T

W

R

I

T

E

S

T

O

P

SLAVE

ADDRESS

WORD

ADDRESS

DATA

SDA

LINE

WA

7

WA

0

1

0

1

0 A2A1A0

D7

D0

A

C

K

A

C

K

R

/

W

A

C

K

Fig.33 Byte Write Cycle Timing

S

T

A

R

T

W

R

I

T

E

S

T

O

SLAVE

ADDRESS

W ORD

ADDRESS(n)

DATA(n)

DATA(n+15)

P

SDA

LINE

W A

7

W A

0

1

0 1 0 A2A1A0

D7

D0

A

C

K

R A

A

C

K

A

C

K

/

C

W K

Fig.34 Page Write Cycle Timing

www.rohm.com

2009.04 - Rev.A

8/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

・With this command the data is programmed into the indicated word address.

・When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory

array.

・Once programming is started no commands are accepted for tWR (5ms max.).

・This device is capable of sixteen-byte Page Write operations.

・If the Master transmits more than sixteen words prior to generating the STOP condition, the address counter will “roll

over” and the previously transmitted data will be overwritten.

・When two or more byte of data are input, the four low order address bits are internally incremented by one after the

receipt of each word, while the four higher order bits of the address (WA7～WA4) remain constant.

○Read Cycle

During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle and

Current Read Cycle. The Random Read Cycle reads the data in the indicated address.

The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the

Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With the

Sequential Read Cycle it is possible to continuously read the next data.

It is necessary to input

“High” at last ACK timing.

W

R

I

T

E

S

T

A

R

T

S

T

A

R

T

R

E

A

D

S

T

O

SLAVE

ADDRESS

SLAVE

ADDRESS

W ORD

ADDRESS(n)

DATA(n)

P

SDA

LINE

W A

7

W A

0

1

0

1

0 A2A1A0

1

0 1 0 A2A1A0

D7

D0

A

C

K

R A

/ C

W K

A

C

K

R A

/

C

W K

Fig.35 Random Read Cycle Timing

S

T

A

R

T

S

T

O

R

E

A

D

SLAVE

ADDRESS

It is necessary to input

“High” at last ACK timing.

DATA

P

SDA

LINE

1

0

1

0 A2A1A0

D7

D0

A

C

K

R

/

W

A

C

K

Fig.36 Current Read Cycle Timing

・ Random Read operation allows the Master to access any memory location indicated by word address.

・ In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal

address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the

next word address (n+1).

・ If an Acknowledge is detected and no STOP condition is generated by the Master (µ-COM), the device will continue to

transmit data. (It can transmit all data (2kbit 256word))

・ If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition

before returning to standby mode.

・ If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read, and

the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read input

Acknowledge with "High" always, then input a STOP condition.

S

T

A

R

T

R

E

A

D

S

T

O

P

It is necessary to

input “High” at

last ACK timing.

SLAVE

ADDRESS

DATA(n)

DATA(n+x)

SDA

LINE

1

0

1

A2A1A0

D7

D0

D7

D0

0

A

C

K

R A

A

C

K

A

C

K

/

C

W K

Fig.37 Sequential Read Cycle Timing （With Current Read）

www.rohm.com

2009.04 - Rev.A

9/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

○Write Protect Cycle

W

R

I

T

E

S

T

A

R

T

S

T

O

W ORD

ADDRESS

SLAVE

ADDRESS

DATA

P

SDA

LINE

0

1

A2A1A0

*

0

A

C

K

R A

A

C

K

/

C

W P

W K

*:DON’T CARE

Fig. 38 Permanent Write Protect Cycle

・Permanent set Write Protect command set data of 00h～7Fh in 256 words write protection block. Clear Write Protect

command can cancel write protection block which is set by set write Protect command. Cancel of write protection block

which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out,

WP pin must be OPEN or GND.

・Permanent Set Write Protect command needs tWR from stop condition same as Byete Write and Page Write, During

tWR, input command is canceled.

・Refer to P8/19 about reply of ACK in each protect state.

W

R

I

T

E

S

T

A

R

T

S

T

O

W ORD

ADDRESS

SLAVE

ADDRESS

DATA

P

SDA

LINE

0

1

0

0 1

*

A

C

K

R A

A

C

K

/

C

W P

W K

*:DON’T CARE

Fig. 39 Set Write Protect Cycle

・Permanent set Write Protect command set data of 00h～7Fh in 256 words write protection block. Clear Write Protect

command can cancel write protection block which is set by set write Protect command. Cancel of write protection block

which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out,

WP pin must be OPEN or GND.

・Permanent Set Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR,

input command is canceled.

・Refer to P8/19 about reply of ACk in each protect state.

W

R

I

T

E

S

T

A

R

T

S

T

O

W ORD

ADDRESS

SLAVE

ADDRESS

DATA

P

SDA

LINE

0

1

0

1 1

*

A

C

K

R A

A

C

K

/

C

W P

W K

*:DON’T CARE

Fig. 40 Clear Write Protect Cycle

・Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of

write protection block which is set by permanent set Write Protect command at once is impossibility. When these

commands are carried out, WP pin must be OPEN or GND.

・Permanent Clear Write Protect command needs tWR from stop condition same as Byete Write and Page Write, During

tWR, input command is canceled.

・Refer to P8/19 about reply of ACk in each protect state.

www.rohm.com

2009.04 - Rev.A

10/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Software Reset

Execute software reset in the event that the device is in an unexpected state after power up and/or the command input

needs to be reset. Below are three types(Fig.39 –(a), (b), (c)) of software reset:

During dummy clock, release the SDA BUS (tied to VCC by a pull-up resistor). During this time the device may pull the SDA

line Low for Acknowledge or the outputting of read data.If the Master sets the SDA line to High, it will conflict with the device

output Low, which can cause current overload and result in instantaneous power down, which may damage the device.

DUMMY CLOCK×14

13

START×2

COMMAND

2

14

1

SCL

SDA

Fig.39-(a) DUMMY CLOCK×14 + START+START

START

DUMMY CLOCK×9

1

COMMAND

2

8

9

SCL

SDA

Fig.39-(b) START + DUMMY CLOCK×9 + START

START×9

3

7

COMMAND

2

8

9

1

SCL

SDA

Fig.39-(c) START×9

* COMMAND starts with start condition.

●Acknowledge polling

Since the IC ignores all input commands during the internal write cycle, no ACK signal will be returned.

When the Master sends the next command after the Write command, if the device returns an ACK signal it means that the

program is completed. No ACK signal indicates that the device is still busy.

Using Acknowledge polling decreases the waiting time by tWR=5ms.

When operating Write or Current Read after Write, first transmit the Slave address (R/W is"High" or "Low"). After the device

returns the ACK signal continue word address input or data output.

During the internal write cycle,

THE FIRST WRITE COMMAND

no ACK will be returned.

(ACK=High)

S

T

A

R

T

S

T

A

R

T

S

T

A

R

T

S

T

O

P

A

C

K

H

A

C

K

H

SLAVE

ADDRESS

WRITE COMMAND

・・・

ADDRESS

tWR

THE SECOND WRITE COMMAND

S

T

A

R

T

S

T

A

R

T

A

C

K

L

A

C

K

A

C

K

L

A

C

K

L

S

T

O

P

SLAVE

WORD

DATA

ADDRESS

H

ADDRESS

・・・

tWR

After the internal write cycle

is completed, ACK will be returned

(ACK=Low). Then input next

Word Address and data.

Fig.40 Successive Write Operation By Acknowledge Polling

www.rohm.com

2009.04 - Rev.A

11/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●WP effective timing

WP is normally fixed at "H" or "L". However, in case WP needs to be controlled in order to cancel the Write command, pay

attention to “WP effective timing” as follows:

The Write command is canceled by setting WP to "H" within the WP cancellation effective period.

The period from the START condition to the rising edge of the clock (which takes in the data DO - the first byte of the Page

Write data) is the ‘invalid cancellation period’. WP input is considered inconsequential during this period. The setup time for

the rising edge of the SCL, which takes in DO, must be more than 100ns.

The period from the rising edge of SCL (which takes in the data D0) to the end of internal write cycle (tWR) is the ‘effective

cancellation period’. When WP is set to "H" during tWR, Write operation is stopped, making it necessary to rewrite the data.

It is not necessary to wait for tWR (5ms max.) after stopping the Write command by WP because the device is in standby

mode.

・The rising edge of the clock

which take in D0

・The rising edge

・of SDA

SCL

SDA

ACK

AN ENLARGEMENT

SDA D0

D1

D0

ACK

AN ENLARGEMENT

S

T

A

R

T

A

C

K

L

A

C

K

L

A

C

K

L

S

T

O

P

A

C

K

L

tWR

SLAVE

ADDRESS

WORD

SDA

WP

DATA

D7 D6 D5

D2 D1 D0

D4 D3

ADDRESS

WP cancellation

effective period

Stop of the write

operation

WP cancellation

invalid period

Data is not

guaranteed

No data will be written

Fig.41 WP effective timing

●Command cancellation from the START and STOP conditions

Command input is canceled by successive inputs of START and STOP conditions. (Refer to Fig.42)

However, during ACK or data output, the device may set the SDA line to Low, making operation of the START and STOP

conditions impossible, and thus preventing reset. In this case execute reset by software. (Refer to Fig.39)

The internal address counter will not be determined when operating the Cancel command by the START and STOP

conditions during Random, Sequential or Current Read. Operate a Random Read in this case.

SCL

SDA

1

0

STOP

START

CONDITION

Fig.42 Command cancellation by the START and STOP conditions during input of the Slave Address

www.rohm.com

2009.04 - Rev.A

12/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●I/O Circuit

○SDA Pin Pull-up Resistor

A pull-up resistor is required because SDA is an NMOS open drain. Determine the resistor value of (RPU) by considering

the VIL and IL, and VOL-IOL characteristics. If a large RPU is chosen, the clock frequency needs to be slow. A smaller

RPU will result in a larger operating current.

○Maximum RPU

The maximum of RPU can be determined by the following factors.

①The SDA rise time determined by RPU and the capacitance of the BUS line(CBUS) must be less than tR.

In addition, all other timings must be kept within the AC specifications.

A

②When the SDA BUS is High, the voltage ○ at the SDA BUS is determined from the total input leakage(IL) of all

devices connected to the BUS. RPU must be higher than the input High level of the microcontroller and the device,

including a noise margin 0.2VCC.

Microcontroller

BR34E02

VCC-ILRPU-0.2 VCC ≧ VIH

0.8V -V

CC IH

IL

RPU

R

∴

≦

PU

SDA PIN

A

Examples: When VCC =3V, IL=10µA, VIH=0.7 VCC

According to ②

IL

0.8x3-0.7x3

10x10^-6

≦

RPU

THE CAPACITANCE OF BUS

LINE (CBUS)COMPUTER

≦

300 [kΩ]

Fig.43 I/O Circuit

○Minimum RPU

The minimum value of RPU is determined by following factors.

①Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.

V_CC-V_OL

R_PU

I_OL

≦

V_CC-V_OL

I_OL

R_PU

∴

≧

②VOLMAX=0.4V must be lower than the input Low level of the microcontroller and the EEPROMincluding the

recommended noise margin of 0.1VCC.

VOLMAX ≦ VIL-0.1 VCC

Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC, According to ①

3-0.4

3×10

RPU

≧

-3

867

Ω

［］

≧

and

VOL=0.4［V］

VIL=0.3×3

=0.9［V］

o that condition ② is met

○SCL Pin Pull-up Resistor

When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required.

However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended.

Several kΩ are recommended for the pull-up resistor in order to drive the output port of the microcontroller.

●A0, A1, A2, WP Pin connections

○Device Address Pin (A0, A1, A2) connections

The status of the device address pins is compared with the device address sent by the Master. One of the devices that is

connected to the identical BUS is selected. Pull up or down these pins or connect them to VCC or GND. Pins that are not

used as device address (N.C.Pins) may be High, Low, or Hi-Z.

○WP Pin connection

The WP input allows or prohibits write operations. When WP is High, only Read is available and Write to all address is

prohibited. Both Read and Write are available when WP is Low.

In the event that the device is used as a ROM, it is recommended that the WP input be pulled up or connected to VCC.

When both READ and WRITE are operated, the WP input must be pulled down or connected to GND or controlled.

www.rohm.com

2009.04 - Rev.A

13/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Microcontroller connection

○Concerning Rs

The open drain interface is recommended for the SDA port in the I²C BUS. However, if the Tri-state CMOS interface is

applied to SDA, insert a series resistor (Rs) between the SDA pin of the device and the pull up resistor RPU is

recommended, since it will serve to limit the current between the PMOS of the microcontroller, and the NMOS of the

EEPROM. Rs also protects the SDA pin from surges. Therefore, Rs is able to be used though open drain inout of the

SDA port.

ACK

SCL

RPU

RS

'H'OUTPUT OF

SDA

CONTROLLER

“L” OUTPUT OF EEPROM

The “H” output of controller and the “L” output of

EEPROM may cause current overload to SDA line.

CONTROLLER

EEPROM

Fig.44 I/O Circuit

Fig.45 Input/Output Collision Timing

○Rs Maximum

The maximum value of Rs is determined by following factors.

①SDA rise time determined by RPU and the capacitance value of the BUS line (CBUS) of SDA must be less than tR. In

addition, the other timings must be within the timing conditions of the AC.

A

②When the output from SDA is Low, the voltage of the BUS at ○ is determined by RPU, and Rs must be lower than the

input Low level of the microcontroller, including recommended noise margin (0.1VCC).

VCC

(V_CC-V_OL)×R_S

+

V_OL+0.1V_CC

V

IL

≦

A

R

_PU+R_S

RPU

RS

VOL

V -V_OL-0.1V_CC

IL

R_S

×

R_PU

∴

≦

IOL

1.1V_CC-V

IL

BUS

CAPACITANCE

Examples : When V_CC=3V V =0.3V_CC

V_OL=0.4V R_PU=20kΩ

ꢀ ꢀ

IL

ꢀ

VIL

EEPROM

0.3×3-0.4-0.1×3

1.1×3-0.3×3

CONTROLLER

20×10³

According to

R_S

×

②

≦

Fig.46 I/O Circuit

1.67 kΩ

［

］

○Rs Minimum

The minimum value of Rs is determined by the current overload during BUS conflict.

Current overload may cause noises in the power line and instantaneous power down.

The following conditions must be met, where “I” is the maximum permissible current, which depends on the Vcc line

impedance as well as other factors. “I” current must be less than 10mA for EEPROM.

Vcc

R

S

I

≦

RPU

"L" OUTPUT

Vcc

I

∴

≧

R

S

RS

Examples: When V =3V, I=10mA

CC

MAXIMUM

CURRENT

"H" OUTPUT

3

R

S

≧

10×10^-3

CONTROLLER

EEPROM

［］

300

Ω

Fig.47 I/O Circuit

www.rohm.com

2009.04 - Rev.A

14/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●I²C BUS Input / Output equivalent circuits

○Input (A0,A2,SCL)

Fig.48 Input Pin Circuit

○Input / Output (SDA)

Fig.49 Input / Output Pin Circuit

○Input (A1)

Fig.50 Input Pin Circuit

○Input (WP)

Fig.51 Input Pin Circuit

www.rohm.com

2009.04 - Rev.A

15/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Power Supply Notes

VCC increases through the low voltage region where the internal circuit of IC and the microcontroller are unstable. In order

to prevent malfunction, the IC has P.O.R and LVCC functionality. During power up, ensure that the following conditions are

met to guaranty P.O.R. and LVCC operability.

1. "SDA='H'" and "SCL='L' or 'H'".

2. Follow the recommended conditions of tR, tOFF, Vbot so that P.O.R. will be activated during power up.

tR

VCC

Recommended conditions of tR, tOFF, Vbot

tR

tOFF

Vbot

tOFF

Below 10ms Above 10ms

Below 100ms Above 10ms

Below 0.3V

Below 0.2V

Vbot

0

Fig.52 VCC rising wavefrom

3. Prevent SDA and SCL from being "Hi-Z".

In case that condition 1. and/or 2. cannot be met, take following actions.

A) If unable to keep Condition 1 (SDA is "Low" during power up)

→Make sure that SDA and SCL are "High" as in the figure below.

VCC

tLOW

SCL

SDA

After Vcc becomes stable

tDH tSU:DAT

tSU:DAT

Fig.53 SCL="H" and SDA="L"

Fig.54 SCL="L" and SDA="L"

B) If unable to keep Condition 2

→After the power stabilizes, execute software reset. (See page 9,10)

C) If unable to keep either Condition 1 or 2

→Follow Instruction A first, then B

●LVCC Circuit

The LVCC circuit prevents Write operation at low voltage and prevents inadvertent writing. A voltage below the LVCC voltage

(1.2V typ.) prohibits Write operation.

●VCC Noise

○Bypass Capacitor

Noise and surges on the power line may cause abnormal function. It is recommended that bypass capacitors (0.1µF) be

attached between VCC and GND externally.

www.rohm.com

2009.04 - Rev.A

16/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Notes for Use

1) Descrived numeric values and data are design representative values, and the values are not guaranteed.

2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further

sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin

in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.

3) Absolute maximum ratings

If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI

may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear

exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that

conditions exceeding the absolute maximum ratings should not be impressed to LSI.

4) GND electric potential

Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of

GND terminal.

5) Heat design

In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin.

6) Terminal to terminal short circuit and wrong packaging

When to package LSI on to a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may

destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND

owing to foreign matter, LSI may be destructed.

7) Use in a strong electromagnetic field may cause malfunction, therfore, evaluate design sufficiently.

www.rohm.com

2009.04 - Rev.A

17/18

Technical Note

BR34E02FVT-W, BR34E02NUX-W

●Ordering part number

B R

3 4

E

0

2

F

V

T

-

W E 2

ROHM type

BUS type

34：I²C

Priduct type Capacity

02= 2K

Packagr

W : Double cell

Packaging and forming specification

E2: Embossed tape and reel

(TSSOP-B8)

FVT:TSSOP-B8

NUX:VSON008X2030

TR: Embossed tape and reel

(VSON008X2030)

SSOP-B8

3.0 0.2

(MAX 3.35 include BURR)

Tape

Embossed carrier tape

2500pcs

Quantity

8

7 6

5

E2

Direction

of feed

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

1

2 3

4

0.15 0.1

S

0.1

0.22

+0.06

0.04

-

M

0.08

Direction of feed

1pin

(0.52)

0.65

Reel

(Unit : mm)

Order quantity needs to be multiple of the minimum quantity.

∗

VSON008X2030

2.0 0.1

Tape

Embossed carrier tape

Quantity

4000pcs

TR

1PIN MARK

Direction

of feed

S

The direction is the 1pin of product is at the upper right when you hold

reel on the left hand and you pull out the tape on the right hand

(

)

0.08

S

1.5 0.1

0.5

C0.25

1

4

8

5

0.25

+0.05

–0.04

Direction of feed

Order quantity needs to be multiple of the minimum quantity.

1pin

0.25

Reel

(Unit : mm)

∗

www.rohm.com

2009.04 - Rev.A

18/18

Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

The content speciﬁed herein is for the purpose of introducing ROHM's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

examples of application circuits for the Products. ROHM does not grant you, explicitly or

implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the

use of such technical information.

The Products speciﬁed in this document are intended to be used with general-use electronic

equipment or devices (such as audio visual equipment, ofﬁce-automation equipment, commu-

nication devices, electronic appliances and amusement devices).

The Products speciﬁed in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard

against the possibility of physical injury, ﬁre or any other damage caused in the event of the

failure of any Product, such as derating, redundancy, ﬁre control and fail-safe designs. ROHM

shall bear no responsibility whatsoever for your use of any Product outside of the prescribed

scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or

system which requires an extremely high level of reliability the failure or malfunction of which

may result in a direct threat to human life or create a risk of human injury (such as a medical

instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,

fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of

any of the Products for the above special purposes. If a Product is intended to be used for any

such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology speciﬁed herein that may

be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to

obtain a license or permit under the Law.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

www.rohm.com

R0039

A


型号：	BR34E02FVT-W_09
厂家：	ROHM
描述：	DDR/DDR2 (For memory module) SPD Memory DDR / DDR2 （对于内存模块）内存SPD 光电二极管双倍数据速率
文件：	总19页 (文件大小：447K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BR34E02FVT-W_09 [ROHM]

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