BR34E02FVT-3E2 [ROHM]
Serial EEPROM Series Standard EEPROM Plug & Play EEPROM; 串行EEPROM系列标准EEPROM即插即用EEPROM
| 型号： | BR34E02FVT-3E2 |
| 厂家： | 
ROHM |
| 描述： | Serial EEPROM Series Standard EEPROM Plug & Play EEPROM |
| 文件： | 总33页 (文件大小：791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Serial EEPROM Series Standard EEPROM
Plug & Play EEPROM
BR34E02-3
General Description
BR34E02-3 is 256×8 bit Electrically Erasable PROM (Based on Serial Presence Detect)
Packages W(Typ) x D(Typ) x H(Max)
Features
256×8 bit Architecture Serial EEPROM
Wide Operating Voltage Range: 1.7V to 5.5V
Two-Wire Serial Interface
Self-Timed Erase and Write Cycle
Page Write Function (16byte)
Write Protect Mode
¾ Settable Reversible Write Protect Function : 00h-7Fh
¾ Write Protect 1 (Onetime Rom)
¾ Write Protect 2 (Hardwire WP PIN)
Low Power consumption
: 00h-7Fh
: 00h-FFh
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
¾ Write
¾ Read
¾ Standby
(at 1.7V)
(at 1.7V)
(at 1.7V)
:
:
:
0.4mA (typ)
0.1mA (typ)
0.1µA (typ)
Prevention of Write Mistake
¾ Write Protect Feature (WP pin)
¾ Prevention of Write Mistake at Low Voltage
High Reliability Fine Pattern CMOS Technology
More than 1 million write cycles
More than 40 years data retention
Noise Reduction Filtered Inputs in SCL / SDA
Initial delivery state FFh
VSON008X2030
2.00mm x 3.00mm x 0.60mm
Absolute Maximum Ratings (Ta=25℃)
Parameter
Supply Voltage
Symbol
Rating
-0.3 to +6.5
Unit
V
Remark
VCC
Derate by 3.3mW/°C when operating above Ta=25°C
Derate by 3.0mW/°C when operating above Ta=25°C
330 (TSSOP-B8)
300 (VSON008X2030)
-65 to +125
Power Dissipation
Pd
mW
Storage Temperature
Tstg
Topr
℃
℃
Operating Temperature
-40 to +85
Input Voltage / Output
Voltage (A0)
Input Voltage / Output
Voltage (others)
-
-
-0.3 to 10.0
V
V
-0.3 to VCC+1.0
Memory Cell Characteristics (Ta=25℃, VCC=1.7V to 5.5V)
Limit
Parameter
Unit
Min
1,000,000
40
Typ
Max
Write / Erase Cycle (1)
Data Retention(1)
-
-
-
-
Times
Years
(1) Not 100% TESTED
○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
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Recommended Operating Ratings
Parameter
Supply Voltage
Input Voltage
Symbol
Rating
1.7 to 5.5
0 to VCC
Unit
V
VCC
VIN
V
DC Characteristics (Unless otherwise specified Ta=-40℃ to +85℃, VCC =1.7V to 5.5V)
Limit
Parameter
Symbol
Unit
Test Conditions
Min
Typ
Max
Vcc+1.0
0.3 VCC
0.4
Input High Voltage
VIH
VIL
0.7 VCC
-
-
-
-
-
-
-
-
V
V
Input Low Voltage
-0.3
-
Output Low Voltage 1
Output Low Voltage 2
Input Leakage Current 1
Input Leakage Current 2
Input Leakage Current 3
Output Leakage Current
VOL1
VOL2
ILI1
V
IOL=2.1mA, 2.5V≦VCC≦5.5V(SDA)
IOL=0.7mA, 1.7V≦VCC＜2.5V(SDA)
VIN=0V to VCC (A0, A1, A2, SCL)
VIN=0V to VCC (WP)
-
0.2
V
-1
-1
-1
-1
1
µA
µA
µA
µA
ILI2
15
ILI3
20
VIN=VHV(A0)
ILO
1
VOUT=0V to VCC
VCC =5.5V, fSCL=400kHz, tWR=5ms
Byte Write
Page Write
Write Protect
VCC =5.5V, fSCL=400kHz
Random Read
Supply Current (Write)
Supply Current (Read)
ICC1
-
-
-
-
2.0
0.5
mA
mA
ICC2
Current Read
Sequential Read
VCC =5.5V, SDA, SCL= VCC
A0, A1, A2=GND, WP=GND
Standby Current
A0 HV Voltage
ISB
-
-
-
2.0
10
µA
V
VHV
7
VHV-VCC≧4.8V
AC Characteristics (Unless otherwise specified Ta=-40℃ to +85℃, VCC =1.7V to 5.5V)
Limit
Parameter
Symbol
Unit
Min
-
Typ
Max
Clock Frequency
fSCL
tHIGH
tLOW
tR
-
-
-
-
-
-
-
-
-
-
-
-
-
-
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
Data Clock High Period
Data Clock Low Period
SDA and SCL Rise Time(1)
SDA and SCL Fall Time(1)
Start Condition Hold Time
Start Condition Setup Time
Input Data Hold Time
Input Data Setup Time
Output Data Delay Time
Output Data Hold Time
Stop Condition Setup Time
Bus Free Time
0.6
1.2
-
-
-
0.3
tF
-
0.3
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
0.6
0.6
0
-
-
-
100
0.1
0.1
0.6
1.2
-
-
0.9
-
tDH
tSU:STO
tBUF
-
-
Write Cycle Time
tWR
5
Noise Spike Width
(SDA and SCL)
tI
-
-
0.1
µs
WP Hold Time
WP Setup Time
tHD:WP
tSU:WP
0
-
-
-
-
-
-
µs
µs
µs
0.1
1.0
WP High Period
tHIGH:WP
(1) Not 100% TESTED
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Serial Input / Output Timing
tR
tF
tHIGH
SCL
SDA
WP
SCL
DATA(1)
D1
DATA(n)
ACK
tHD:STA
tSU:DAT tLOW
tHD:DAT
D0 ACK
SDA
(IN)
tWR
STOP CONDITION
tHD：WP
tBUF
tPD
tDH
SDA
(OUT)
tSU：WP
Figure 1-(a). Serial Input / Output Timing
Figure 1-(d). WP Timing of the Write Operation
○SDA data is latched into the chip at the rising edge of SCL clock.
○Output data toggles at the falling edge of SCL clock.
SCL
SDA
SCL
SDA
DATA(1)
D1
DATA(n)
D0
tSU:STA
tHD:STA
tSU:STO
ACK
ACK
WP
tHIGH : WP
tWR
STOP BIT
START BIT
Figure 1-(b). Start/Stop Bit Timing
Figure 1-(e). WP Timing of the Write Cancel Operation
○For WRITE operation, WP must be "Low" from the rising edge of the
clock (which takes in D0 of first byte) until the end of tWR. (See Figure
1-(d) ) During this period, WRITE operation can be canceled by setting
WP "High".（See Figure 1-(e)）
SCL
SDA
D0
ACK
○When WP is set to "High" during tWR, WRITE operation is immediately
ceased, making the data unreliable. It must then be re-written.
tWR
WRITE DATA(n)
STOP
CONDITION
START
CONDITION
Figure 1-(c). Write Cycle Timing
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Block Diagram
PROTECT_MEMORY_ARRAY
2Kbit_MEMORY_ARRAY
VCC
A0 1
8
7 WP
6 SCL
5 SDA
8bit
8bit
ADDRESS
DECODER
SLAVE , WORD
DATA
REGISTE
A1 2
A2 3
8bit
ADDRESS
START
STOP
CONTOROL LOGIC
ACK
HIGH VOLTAGE
GND 4
VCC LEVEL DETECT
Pin Configuration
(TOP VIEW)
BR34E02-3
A0 1
8 VCC
A1 2
A2 3
7 WP
6 SCL
5 SDA
GND 4
Pin Descriptions
Pin Name
Input/Output
Descriptions
VCC
GND
-
Power supply
Ground 0V
-
A0, A1, A2
SCL
IN
IN
Slave address set.
Serial clock input
Slave and word address(1)
Serial data input, serial data output
SDA
WP
IN / OUT
IN
Write protect input(2)
(1) Open drain output requires a pull-up resistor.
(2) WP Pin has a Pull-Down resistor. Please leave unconnected or connect to GND when not in use.
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Typical Performance Curves
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 3. Input Low Voltage vs Supply Voltage
(A0, A1, A2, SCL, SDA, WP)
Figure 2. Input High Voltage vs Supply Voltage
(A0, A1, A2, SCL, SDA, WP)
Output Low Current: IOL(mA)
Output Low Current: IOL(mA)
Figure 4. Output Low Voltage1 vs Output Low Current
(Vcc=2.5V)
Figure 5. Output Low Voltage2 vs Output Low Current
(Vcc=1.7V)
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Typical Performance Curves‐Continued
Supply Voltage : V (V)
Supply Voltage : VCC(V)
CC
Figure 7. Input Leakage Current2 vs Supply Voltage
(WP)
Figure 6. Input Leakage Current1 vs Supply Voltage
(A0, A1, A2, SCL)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 9. Supply Current (WRITE) vs Supply Voltage
(fSCL=400kHz)
Figure 8. Output Leakage Current vs Supply Voltage
(SDA)
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Typical Performance Curves‐Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 11. Standby Current vs Supply Voltage
Figure 10. Supply Current (READ) vs Supply Voltage
(fSCL=400kHz)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 12. Clock Frequency vs Supply Voltage
Figure 13. Data Clock High Period vs Supply Voltage
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Typical Performance Curves‐Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 14. Data Clock Low Period vs Supply Voltage
Figure 15. Start Condition Hold Time vs Supply Voltage
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 16. Start Condition Setup Time vs Supply Voltage
Figure 17. Input Data Hold Time vs Supply Voltage
(HIGH)
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Typical Performance Curves‐Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 18. Input Data Hold Time vs Supply Voltage
(LOW)
Figure 19. Input Data Setup Time vs Supply Voltage
(HIGH)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 20. Input Data Setup Time vs Supply Voltage
(LOW)
Figure 21. Low Output Data Delay Time vs Supply Voltage
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Typical Performance Curves‐Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 22. High Output Data Delay Time vs Supply Voltage
Figure 23. Stop Condition Setup Time vs Supply Voltage
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 25. Write Cycle Time vs Supply Voltage
Figure 24. Bus Free Time vs Supply Voltage
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Typical Performance Curves‐Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 26. Noise Spike Width vs Supply Voltage
(SCL H)
Figure 27. Noise Spike Width vs Supply Voltage
(SCL L)
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 28. Noise Spike Width vs Supply Voltage
(SDA H)
Figure 29. Noise Spike Width vs Supply Voltage
(SDA L)
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Typical Performance Curves‐Continued
Supply Voltage : VCC(V)
Supply Voltage : VCC(V)
Figure 30. WP Hold Time vs Supply Voltage
Figure 31. WP Setup Time vs Supply Voltage
Supply Voltage : VCC(V)
Figure 32. WP High Period vs Supply Voltage
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Timing Chart
1. I2C BUS Data Communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte. I2C BUS data communication with several devices is possible by
connecting with 2 communication lines: serial data (SDA) and serial clock (SCL).
Among the devices, there should be a “master” that generates clock and control communication start and end. The
rest become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that
outputs data to the bus during data communication is called “transmitter”, and the device that receives data is called
“receiver”.
2. START Condition (START bit Recognition)
(1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
‘HIGH' is necessary.
(2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition
is satisfied, any command cannot be executed.
3. STOP Condition (STOP bit Recognition)
(1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is
'HIGH'. (See Figure 1-(b) START/STOP Bit Timing)
4. Write Protect By Soft Ware
(1) Set Write Protect command and permanent set Write Protect command set data of 00h to 7Fh in 256 words write
protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect
command. Cancel of write protection block which is set by permanent set Write Protect command at once is
impossibility. When these commands are carried out, WP pin must be OPEN or GND.
5. Acknowledge
(1) Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS
after transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the
µ-COM. When outputting the data during read operation, the Transmitter is the EEPROM.
(2) During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been
received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When
outputting the data during read operation the receiver is the µ-COM.)
(3) The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit).
(4) In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word
(word address and write data).
(5) In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an
Acknowledge.
(6) If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit
the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP
condition before returning to standby mode.
6. Device Addressing
Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits
of the slave address are the “device type indentifier.” For this EEPROM it is “1010.” (For WP register access this
code is "0110".) The next three bits identify the specified device on the BUS (device address). The device address is
defined by the state of the A0,A1 and A2 input pins. This IC works only when the device address input from the SDA
pin corresponds to the status of the A0,A1 and A2 input pins. Using this address scheme allows up to eight devices
to be connected to the BUS. The last bit of the stream (R/W…READ/WRITE) determines the operation to be
performed.
R/W=0 ････
R/W=1 ････
WRITE (including word address input of Random Read)
READ
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Slave Address Set Pin Device Type Device Address Read Write Mode
Access Area
A2
A2
A1
A1
A0
A0
1010
A2 A1 A0
A2 A1 A0
2kbit Access to Memory
R / W
R / W
R / W
R / W
Access to Permanent Set Write
Protect Memory
GND
GND
GND
VCC
VHV
VHV
0110
0
0
0
1
1
1
Access to Set Write Protect Memroy
Access to Clear Write Protect Memory
7. Write Protect Pin (WP)
When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level),
it is enable to write 256 words (all address).
If permanent protection is done by Write Protect command, lower half area (00 to 7Fh address) is inhibited writing
regardless of WP pin state.
WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use.
8. Confirm Write Protect Resistor by ACK
According to state of Write Protect Resistor, ACK is as follows.
State of Write
Protect Register Input
WP
Write
Cycle(tWR)
Input Command
ACK
Address
ACK
Data
-
ACK
PSWP,SWP,CWP
No ACK
ACK
-
No ACK
ACK
No ACK
No
No
In case,
protect by PSWP
-
Page or Byte Write
(00 to 7Fh)
WA7 to WA0
D7 to D0 No ACK
SWP
CWP
No ACK
ACK
-
-
-
No ACK
ACK
-
-
-
No ACK
ACK
No
Yes
Yes
0
PSWP
ACK
ACK
ACK
Page or Byte Write
(00 to 7Fh)
ACK
WA7 to WA0
ACK
D7 to D0 No ACK
No
In case,protect by
SWP
SWP
No ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
-
No ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
-
-
-
No ACK
No ACK
No ACK
No
No
CSP
-
1
PSWP
-
No
Page or Byte Write
PSWP, SWP, CWP
Page or Byte Write
PSWP, SWP, CWP
Page or Byte Write
WA7 to WA0
D7 to D0 No ACK
No
-
-
ACK
ACK
Yes
Yes
No
0
WA7 to WA0
-
D7 to D0
-
In case,
Not protect
1
No ACK
WA7 to WA0
D7 to D0 No ACK
No
Acknowledge when writing data or defining the write-protection (instructions with R/W bit=0) - is Don’t Care
State of Write Protect Register
In case, protect by PSWP
Command
PSWP, SWP, CWP
SWP
ACK
No ACK
No ACK
ACK
Address
ACK
Data
ACK
-
-
-
-
-
No ACK
No ACK
No ACK
No ACK
No ACK
-
-
-
-
-
No ACK
No ACK
No ACK
No ACK
No ACK
In case, protect by SWP
CWP
PSWP
ACK
Case, Not protect
PSWP, SWP, CWP
ACK
Acknowledge when reading data the write-protection (instructions with R/W bit=1)
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Command
1. Write Cycle
During WRITE CYCLE operation data is written in the EEPROM. The Byte Write Cycle is used to write only one byte.
In the case of writing continuous data consisting of more than one byte, Page Write is used. The maximum bytes that
can be written at one time is 16 bytes.
S
T
A
R
T
W
R
I
T
E
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
DATA
SDA
LINE
WA
7
WA
0
1
0
1
0 A2A1A0
D7
D0
A
C
K
A
C
K
R
/
W
A
C
K
Figure 33. Byte Write Cycle Timing
S
T
A
R
T
W
R
I
T
E
S
T
O
SLAVE
ADDRESS
W ORD
ADDRESS(n)
DATA(n)
DATA(n+15)
P
SDA
LINE
W A
7
W A
0
1
0 1 0 A2A1A0
D7
D0
D0
A
C
K
R A
A
C
K
A
C
K
/
C
W K
Figure 34. Page Write Cycle Timing
(1) With this command the data is programmed into the indicated word address.
(2) When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
(3) Once programming is started no commands are accepted for tWR (5ms max).
(4) This device is capable of 16-byte Page Write operations.
(5) If the Master transmits more than 16 words prior to generating the STOP condition, the address counter will “roll
over” and the previously transmitted data will be overwritten. When two or more byte of data are input, the four low
order address bits are internally incremented by one after the receipt of each word, while the four higher order bits
of the address (WA7 to WA4) remain constant.
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2. Read Cycle
During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle
and Current Read Cycle. The Random Read Cycle reads the data in the indicated address.
The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the
Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With
the Sequential Read Cycle it is possible to continuously read the next data.
It is necessary to input
“High” at last ACK timing.
W
R
I
T
E
S
T
A
R
T
S
T
A
R
T
R
E
A
D
S
T
O
SLAVE
ADDRESS
SLAVE
ADDRESS
W ORD
ADDRESS(n)
DATA(n)
P
SDA
LINE
W A
7
W A
0
1
0
1
0 A2A1A0
1
0 1 0 A2A1A0
D7
D0
A
C
K
R A
/ C
W K
A
C
K
R A
/
C
W K
Figure 35. Random Read Cycle Timing
S
T
A
R
T
S
T
O
R
E
A
D
SLAVE
ADDRESS
It is necessary to input
“High” at last ACK timing.
DATA
P
SDA
LINE
1
0
1
0 A2A1A0
D7
D0
A
C
K
R
/
W
A
C
K
Figure 36. Current Read Cycle Timing
(1) Random Read operation allows the Master to access any memory location indicated by word address.
(2) In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal
address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of
the next word address (n+1).
(3) If an Acknowledge is detected and no STOP condition is generated by the Master (µ-COM), the device will
continue to transmit data. (It can transmit all data (2kbit 256word))
(4) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to standby mode.
(5) If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read,
and the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read
input Acknowledge with "High" always, then input a STOP condition.
S
T
A
R
T
R
E
A
D
S
T
O
P
It is necessary to
input “High” at
last ACK timing.
SLAVE
ADDRESS
DATA(n)
DATA(n+x)
SDA
LINE
1
0
1
A2A1A0
D7
D0
D7
D0
0
A
C
K
R A
A
C
K
A
C
K
/
C
W K
Figure 37. Sequential Read Cycle Timing（With Current Read）
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3. Write Protect Cycle
W
R
I
T
E
S
T
A
R
T
S
T
O
W ORD
ADDRESS
SLAVE
ADDRESS
DATA
P
SDA
LINE
0
1
1
A2A1A0
*
*
*
*
0
A
C
K
R A
A
C
K
/
C
W P
W K
*:DON’T CARE
Figure 38. Permanent Set Write Protect Cycle
(1) Permanent Set Write Protect Cycle
(a) Permanent set Write Protect command set data of 00h to 7Fh in 256 words write protection block. Cancel of
write protection block which is set by permanent set Write Protect command at once is impossibility. When
these commands are carried out, WP pin must be OPEN or GND.
(b) Permanent Set Write Protect command needs tWR from stop condition same as Byte Write and Page Write,
during tWR, input command is canceled.
(c) Refer to Page14 about reply of ACK in each protect state.
W
R
I
T
E
S
T
A
R
T
S
T
O
W ORD
ADDRESS
SLAVE
ADDRESS
DATA
P
SDA
LINE
0
1
1
0
0
0 1
*
*
*
*
A
C
K
R A
A
C
K
/
C
W P
W K
*:DON’T CARE
Figure 39. Set Write Protect Cycle
(2) Set Write Protect Cycle
(a) Set Write Protect command set data of 00h to 7Fh in 256 words write protection block. Clear Write Protect
command can cancel write protection block which is set by set write Protect command. When these
commands are carried out, WP pin must be OPEN or GND.
(b) Set write Protect command needs tWR from stop condition same as Byte Write and Page Write, during tWR
,
input command is canceled.
(c) Refer to Page14 about reply of ACK in each protect state.
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W
R
I
T
E
S
T
A
R
T
S
T
O
W ORD
ADDRESS
SLAVE
ADDRESS
DATA
P
SDA
LINE
0
1
1
0
0
1 1
*
*
*
*
A
C
K
R A
A
C
K
/
C
W P
W K
*:DON’T CARE
Figure 40. Clear Write Protect Cycle
(3) Clear Write Protect Cycle
(a) Clear Write Protect command can cancel write protection block which is set by set write Protect command.
When these commands are carried out, WP pin must be OPEN or GND.
(b) Clear Write Protect command needs tWR from stop condition same as Byte Write and Page Write, during tWR
,
input command is canceled.
(c) Refer to Page14 about reply of ACK in each protect state.
Software Reset
Software reset is executed to avoid malfunction after power on and during command input. Software reset has several
kinds and 3 kinds of them are shown in the figure below. (Refer to Figure 41.-(a), Figure 41.-(b), and Figure 41.-(c).) Within
the dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may
be output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
DUMMY CLOCK x 14
13
START x 2
SCL
2
14
COMMAND
COMMAND
1
SDA
Figure 41-(a). DUMMY CLOCK x 14 + START + START
START
DUMMY CLOCK x 9
START
SCL
2
8
9
1
COMMAND
COMMAND
SDA
Figure 41-(b). START + DUMMY CLOCK x 9 + START
START x 9
SCL
3
7
2
8
9
1
COMMAND
COMMAND
SDA
Figure 41-(c). START x 9
* COMMAND starts with start condition.
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Acknowledge Polling
During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic
write execution after write cycle input, next command (slave address) is sent. If the first ACK signal sends back 'L', then it
means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge
polling, next command can be executed without waiting for tWR = 5ms.
To write continuously, R/ W = 0, then to carry out current read cycle after write, slave address with R/ W = 1 is sent. If
ACK signal sends back 'L', and then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is returned.
THE FIRST WRITE COMMAND
S
S
T
A
R
T
S
T
A
R
T
S
A
C
K
H
A
T
SLAVE
SLAVE
ADDRESS
Ｔ
C
K
H
A
R
T
WRITE COMMAND
ADDRESS
O
P
・・・
tWR
THE SECOND WRITE COMMAND
S
T
A
R
T
S
T
A
R
T
A
C
K
L
A
A
C
K
L
A
C
K
L
S
Ｔ
O
P
SLAVE
SLAVE
WORD
C
DATA
・・・
ADDRESS
K
ADDRESS
ADDRESS
H
tWR
After completion of internal write,
ACK=LOW is returned, so input next
word address and data in succession.
Figure 42. Case of Continuous Write by Acknowledge Polling
WP Effective Timing
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, observe the following WP valid timing.
During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write
cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of data(in
page write cycle, the first byte data) is the cancel invalid area.
WP input in this area becomes ‘Don't care’. The area from the rise of SCL to take in D0 to the stop condition input is the
cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status..
・The rising edge of the clock
SCL
SDA
which take in D0
・The rising edge
・of SDA
SCL
D0
ACK
ACK
AN ENLARGEMENT
SDA
D1
D0
AN ENLARGEMENT
S
T
A
R
T
A
C
K
L
A
C
K
L
tWR
A
C
K
L
S
T
O
P
A
C
K
L
SLAVE
ADDRESS
WORD
SDA
DATA
D7 D6 D5
D2
D1 D0
D4 D3
ADDRESS
Stop of the write
operation
WP cancellation
effective period
WP cancellation invalid period
WP
Data is not
guaranteed
No data will be written
Figure 43. WP Effective Timing
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Command Cancellation from the START and STOP Conditions
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure
44.) However, within ACK output area and during data read, SDA bus may output 'L'. In this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by
start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession,
carry out random read cycle.
SCL
SDA
1
0
1
0
STOP
START
CONDITION
CONDITION
Figure 44. Command Cancellation by the START and STOP Conditions during Input of the Slave Address
I/O Peripheral Circuit
1. Pull-Up Resistance of SDA Terminal
SDA is NMOS open drain, so it requires a pull up resistor. As for this resistance value (RPU), select an appropriate
value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is limited.
The smaller the RPU, the larger is the supply current (Read).
2. Maximum RPU
The maximum value of RPU is determined by the following factors.
(1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower.
Furthermore, AC timing should be satisfied even when SDA rise time is slow.
(2) The bus. electric potential
A to be determined by the input current leak total (IL) of device connected to bus at
○
output of 'H' to the SDA line and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and
EEPROM including recommended noise margin of 0.2Vcc.
VCC-ILRPU-0.2 VCC ≧ VIH
BR34E02
Microcontroller
CC IH
0.8V -V
PU
R
∴
≦
RPU
L
I
SDA PIN
A
Examples: When VCC =3V, IL=10µA, VIH=0.7 VCC
According to (2)
IL
IL
0.8×3-0.7×3
RPU
≦
≦
10×10-6
THE CAPACITANCE
OF BUS LINE (CBUS
[kΩ]
300
)
Figure 45. I/O Circuit
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3. Minimum RPU
The minimum value of RPU is determined by following factors.
(1) Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low.
VCC-VOL
RPU
IOL
≦
VCC-VOL
IOL
RPU
∴
≧
(2) VOLMAX=0.4V must be lower than the input Low level of the micro controller and the EEPROM including the
recommended noise margin of 0.1VCC.
VOLMAX ≦ VIL-0.1 VCC
Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the micro controller and the EEPROM is VIL=0.3VCC,
3-0.4
3×10-3
According to (1)
PU
R
≧
[ꢀ]
≧ 867
And
And
VOL=0.4 [V]
VIL=0.3×3
=0.9 [V]
so that condition (2) is met
4. Pull-up Resistance of SCL Terminal
When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time
where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several kꢀ to several ten kꢀ
is recommended in consideration of drive performance of output port of microcontroller.
A0, A1, A2, WP Pin Connections
1. Device Address Pin (A0, A1, A2) Connections
The status of the device address pins is compared with the device address sent by the Master. One of the devices that
are connected to the identical BUS is selected. Pull up or down these pins or connect them to VCC or GND. Pins that
are not used as device address (N.C.Pins) may be High, Low, or Hi-Z.
2. WP Pin Connection
The WP input allows or prohibits write operations. When WP is High, only Read is available and Write to all address is
prohibited. Both Read and Write are available when WP is Low.
In the event that the device is used as a ROM, it is recommended that the WP input be pulled up or connected to VCC.
When both READ and WRITE are operated, the WP input must be pulled down or connected to GND or controlled.
Microcontroller Connection
1. RS
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output
of tri state to SDA port, insert a series resistance RS between the pull up resistor Rpu and the SDA terminal of
EEPROM. This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM
are turned ON simultaneously. RS also plays the role of protecting the SDA terminal against surge. Therefore, even
when SDA port is open drain input/output, RS can be used.
ACK
SCL
RPU
RS
“H” OUTPUT OF
MICROCONTROLLER
“L” OUTPUT OF EEPROM
SDA
EEPROM
MICRO CONTROLLER
The “H” output of micro controller and the “L” output of
EEPROM may cause current overload to SDA line.
Figure 46. I/O Circuit
Figure 47. Input/Output Collision Timing
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2. Maximum Value of RS
The maximum value of RS is determined by the following relations.
(1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower.
Furthermore, AC timing should be satisfied even when SDA rise time is slow.
(2) The bus’ electric potential
A to be determined by RPU and RS the moment when EEPROM outputs 'L' to SDA bus
○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin of 0.1Vcc.
VCC
CC OL
(V -V )×R
S
+
VOL+0.1VCC≦VIL
RPU+RS
A
RPU
RS
VOL
IL OL
V -V -0.1V
CC
S
PU
R
∴
R
≦
×
1.1VCC-VIL
IOL
BUS
CAPACITANCE
CC
IL
CC, OL
PU
Examples: When V =3V, V =0.3V
V
=0.4V, R =20k
0.3×3-0.4-0.1×3
1.1×3-0.3×3
20×103
×
VIL
S
According R
≦
≦
EEPROM
MICRO CONTROLLER
Figure 48. I/O Circuit
1.67[kꢀ]
3. Minimum Value of RS
The minimum value of RS is determined by over current at bus collision. When over current flows, noises in power source
line and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of the impedance of power source
line in set and so forth. Set the over current to EEPROM at 10mA or lower.
Vcc
RS
I
≦
Vcc
RS
∴
≧
I
PU
R
"L" OUTPUT
Examples: When V =3V, I=10mA
CC
S
R
3
RS
≧
10×10-3
MAXIMUM
CURRENT
"H" OUTPUT
300 [ꢀ]
≧
MICRO CONTROLLER
EEPROM
Figure 49. I/O Circuit
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I/O Equivalence Circuit
1. Input (A0,A1,A2,SCL)
Figure 50. Input Pin Circuit Diagram
2. Input (SDA)
Figure 51. Input Pin Circuit Diagram
3. Input (WP)
Figure 52. Input Pin Circuit Diagram
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Power-Up/Down Conditions
At power ON, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal
logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and
LVCC circuit. To assure the operation, observe the following conditions at power ON.
1. "SDA='H'" and "SCL='L' or 'H'".
2. Follow the recommended conditions of tR, tOFF, Vbot so that P.O.R. will be activated during power up.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
R
OFF
bot
V
t
t
Below 10ms Above 10ms Below 0.3V
Below 100ms Above 10ms Below 0.2V
tOFF
Vbot
0
Figure 53. Vcc Rising Waveform
3. Set SDA and SCL so as not to become "Hi-Z".
When the above conditions 1 and 2 cannot be observed, take following countermeasures.
(1) In the case when the above condition 1 cannot be observed such that SDA becomes ‘L’ at power ON.
→Control SCL and SDA as shown below, to make SCL and SDA, ‘H’ and ‘H’.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Figure 54. SCL="H" and SDA="L"
Figure 55. SCL="L" and SDA="L"
(2) In the case when the above condition 2 cannot be observed.
→After the power source become stable, execute software reset.(Figure 41)
(3) In the case when the above condition 1 and 2 cannot be observed.
→Carry out (1), and then carry out (2).
Low Voltage Malfunction Prevention Function
LVCC circuit prevents data rewrite operation at low power, and prevents write error. At LVCC voltage (Typ =1.2V) or below,
data rewrite is prevented.
Noise Countermeasures
1. Bypass Capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a
bypass capacitor (0.1µF) between IC Vcc and GND pins. Connect the capacitor as close to IC as possible. In addition, it
is also recommended to connect a bypass capacitor between board’s Vcc and GND.
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Operational Notes
1. Described numeric values and data are design representative values only, and the values are not guaranteed.
2. We believe that the application circuit examples in this document are recommendable. However, in actual use, confirm
characteristics further sufficiently. If changing the fixed number of external parts is desired, make your decision with
sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of external parts
and our LSI.
3. Absolute maximum ratings
If the absolute maximum ratings such as supply voltage, operating temperature range, and so on are exceeded, LSI
may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings.
In the case of fear of exceeding the absolute maximum ratings, take physical safety countermeasures such as adding
fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplied to the LSI.
4. GND electric potential
Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower
than that of GND terminal.
5. Thermal design
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions.
6. Short between Pins and Mounting Errors
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong
orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
7. Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design
sufficiently.
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BR34E02-3
Part Numbering
B
R
3 4
E
0
2
x x x -
3
x x
BUS Type
34 : I2C
Operating Temperature
-40℃ to+85℃
Capacity
02=2K
Package
FVT
:TSSOP-B8
NUX
:VSON008X2030
Process
Packaging and Forming Specification
E2
: Embossed tape and reel
(TSSOP-B8)
TR
: Embossed tape and reel
(VSON008X2030)
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Physical Dimension Tape and Reel Information
TSSOP-B8
3.0± 0.1
(MAX 3.35 include BURR)
4 ± ±4
8
7
6
5
1
2
3
4
1PIN MARK
+0.05
0.145
−0.03
0.525
S
0.08 S
+0.05
0.245
M
−0.04
0.08
0.65
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
Quantity
3000pcs
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
Direction of feed
1pin
Reel
Order quantity needs to be multiple of the minimum quantity.
∗
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Physical Dimension Tape and Reel Information‐Continued
VSON008X2030
2.0± 0.1
1PIN MARK
S
0.08 S
1.5± 0.1
0.5
C0.25
1
8
4
5
0.25
+0.05
−0.04
0.25
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape
4000pcs
Quantity
TR
Direction
of feed
The direction is the 1pin of product is at the upper right when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
Direction of feed
1pin
Reel
Order quantity needs to be multiple of the minimum quantity.
∗
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BR34E02-3
Marking Diagrams
TSSOP-B8 (TOP VIEW)
VSON008X2030 (TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
3 E 0
2
3
LOT Number
1PIN MARK
1PIN MARK
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Revision History
Date
Revision
001
Changes
07.Sep.2012
25.Feb.2013
New Release
Update some English words, sentences’ descriptions, grammar and
formatting.
002
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Notice
●General Precaution
1) Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2) All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
●Precaution on using ROHM Products
1) Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment, transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
2) ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3) Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4) The Products are not subject to radiation-proof design.
5) Please verify and confirm characteristics of the final or mounted products in using the Products.
6) In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8) Confirm that operation temperature is within the specified range described in the product specification.
9) ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
●Precaution for Mounting / Circuit board design
1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
●Precautions Regarding Application Examples and External Circuits
1) If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2) You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
●Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
●Precaution for Storage / Transportation
1) Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2) Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3) Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4) Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
●Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
●Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
●Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
●Precaution Regarding Intellectual Property Rights
1) All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
●Other Precaution
1) The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
2) This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
3) The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
4) In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
5) The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - Rev.004
© 2013 ROHM Co., Ltd. All rights reserved.
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