CY62148VLL-70BAI [ROCHESTER]
512KX8 STANDARD SRAM, 70ns, PBGA36, 7 X 8.50 X 1.50 MM, FINE PITCH, TBGA-36;
| 型号： | CY62148VLL-70BAI |
| 厂家： | 
Rochester Electronics |
| 描述： | 512KX8 STANDARD SRAM, 70ns, PBGA36, 7 X 8.50 X 1.50 MM, FINE PITCH, TBGA-36 输入元件 静态存储器 输出元件 内存集成电路 |
| 文件： | 总13页 (文件大小：896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
48V
MoBL
CY62148V MoBL™
512K x 8 MoBL Static RAM
The device can be put into standby mode when deselected
(CE HIGH).
Features
• Low voltage range:
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A18).
— 2.7V–3.6V
• Ultra low active power
• Low standby power
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
The CY62148V is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII,
and a 32-pin SOIC package.
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
Data in Drivers
A
0
A
1
A
2
A
3
A
4
A
512K x 8
ARRAY
5
A
6
A
A
A
7
8
9
6
7
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
62148V-1
OE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05070 Rev. **
Revised September 4, 2001
CY62148V MoBL™
Pin
Configurations
FBGA
Top View
TSOPII/SOIC
Top View
1
2
4
3
5
6
A
A
V
A
A
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
32
31
30
29
1
17
16
CC
2
3
4
5
6
15
A
A
6
A
A
NC
A
3
8
A
B
C
1
0
A
14
18
A
12
A
I/O
WE
4
A
I/O
0
A
A
A
A
A
A
A
A
A
28
27
26
25
4
7
7
6
5
2
13
8
7
9
11
NC
A
5
I/O
I/O
1
5
4
3
8
24
23
9
V
V
SS
CC
D
E
F
2
10
11
12
13
10
22
21
20
19
18
17
1
0
0
7
V
CC
V
SS
I/O
6
5
I/O
I/O
V
1
2
14
15
A
A
17
I/O
I/O
2
4
18
6
SS 16
3
CE
A
G
H
I/O
OE
A
A
I/O
3
16
7
15
A
A
A
13
A
A
14
12
11
10
9
62148V–2
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied...............................................55°C to +125°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +4.6V
Range
Industrial
Ambient Temperature
VCC
DC Voltage Applied to Outputs
–40°C to +85°C
2.7V to 3.6V
in High Z State[1]....................................–0.5V to VCC + 0.5V
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC Standby (ISB2)
Product
VCC Range
Typ.[2]
)
Min.
Max.
Speed
Typ.[2]
Maximum
Ty.p[2]
Maximum
CY62148V
2.7V
3.0V
3.6V
70 ns
7
15 mA
2 µA
20 µA
Notes:
1. VIL(min.) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05070 Rev. **
Page 2 of 12
CY62148V MoBL™
Electrical Characteristics Over the Operating Range
CY62148V
Typ.[2]
Parameter
Description
Test Conditions
IOH = –1.0 mA
Min.
Max.
Unit
VOH
Output HIGH Voltage
2.4
V
VCC = 2.7V
VCC = 2.7V
VCC = 3.6V
VCC = 2.7V
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 2.1 mA
0.4
VCC + 0.5V
0.8
V
V
V
2.2
–0.5
IIX
Input Load Current
GND < VI < VCC
–1
–1
+1
+1
+1
+1
µA
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output
Disabled
ICC
VCC Operating Supply
Current
IOUT = 0 mA, (f =
fMAX = 1/tRC) CMOS
Levels
VCC = 3.6V
7
15
mA
IOUT = 0 mA, f = 1 MHz CMOS Levels
1
2
mA
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC − 0.3V,
VIN > VCC − 0.3V or
VIN < 0.3V, f = fMAX
100
µA
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC − 0.3V
VIN > VCC − 0.3V
or VIN < 0.3V, f = 0
L
1
2
50
20
µA
µA
VCC
3.6V
=
LL
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Max.
Unit
CIN
Input Capacitance
Output Capacitance
6
8
pF
pF
COUT
Thermal Resistance
Description
Test Conditions
Symbol
Others
BGA
Units
Thermal Resistance[3]
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch, 4-lay-
er printed circuit board
ΘJA
TBD
TBD
°C/W
Thermal Resistance[3]
(Junction to Case)
ΘJC
TBD
TBD
°C/W
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05070 Rev. **
Page 3 of 12
CY62148V MoBL™
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
OUTPUT
V
Typ
CC
90%
10%
10%
R2
30 pF
GND
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
62148V–4
62148V–3
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
3.0V
Unit
R1
R2
1105
1550
645
Ohms
Ohms
Ohms
Volts
RTH
VTH
1.75V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
Min.
Typ.[2]
Max.
3.6
Unit
V
VCC for Data Retention
Data Retention Current
1.0
VCC = 1.0V
L/ LL
0.2
5.5
µA
µA
CE > VCC − 0.3V,
VIN > VCC − 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
[3]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[4]
tR
Operation Recovery
Time
tRC
Note:
4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) > 10 µs.
Data Retention Waveform
DATA RETENTION MODE
1.0V
1.0V
V
DR
> 1.0 V
V
CC
t
t
R
CDR
CE
62148V–5
Document #: 38-05070 Rev. **
Page 4 of 12
CY62148V MoBL™
Switching Characteristics Over the Operating Range[5]
(2.7V–3.6V
Operation)
Parameter
READ CYCLE
Description
Min.
Max.
Unit
tRC
Read Cycle Time
70
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[7 ]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
70
tOHA
tACE
70
35
tDOE
tLZOE
5
10
0
tHZOE
25
25
70
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
tPWE
tSD
50
30
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[6, 7]
WE HIGH to Low Z[6]
tHD
tHZWE
25
tLZWE
10
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7.
tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05070 Rev. **
Page 5 of 12
CY62148V MoBL™
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62148V–6
Read Cycle No. 2 [11, 12]
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
I
CC
50%
50%
I
SB
62148V–7
Write Cycle No. 1 (WE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA I/O
DATA VALID
IN
NOTE15
t
HZOE
62148V–8
Notes:
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = VIH
.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05070 Rev. **
Page 6 of 12
CY62148V MoBL™
Switching Waveforms (continued)
[8, 13, 14]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
62148V–9
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 15
IN
t
t
LZWE
HZWE
62148–10
Document #: 38-05070 Rev. **
Page 7 of 12
CY62148V MoBL™
Typical DC and AC Characteristics
Standby Current vs. Supply Voltage
45
Normalized Operating Current
vs. Supply Voltage
1.4
40
35
30
25
1.2
1.0
0.8
0.6
20
0.4
15
10
0.2
0.0
1.0
3.7
2.8
1.9
SUPPLY VOLTAGE (V)
1.7
2.2
2.7
3.2
3.7
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
70
60
50
40
30
20
10
1.0
3.7
2.8
SUPPLY VOLTAGE (V)
1.9
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power-Down
Read
Standby (ISB
)
H
L
Data Out
Data In
High Z
Active (ICC
Active (ICC
Active (ICC)
)
L
L
X
Write
)
L
H
H
Output Disabled
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY62148VLL-70BAI
Package Type
70
BA37
ZS32
S34
36-Ball Fine Pitch BGA
32-Lead TSOPII
Industrial
CY62148VLL-70ZI
CY62148VLL-70SI
32-Lead 450 mil. molded SOIC
Document #: 38-05070 Rev. **
Page 8 of 12
CY62148V MoBL™
Package Diagrams
36-Ball (7.00 mm x 8.5 mm x 1.5 mm) Thin BGA BA37
51-85105-A
Document #: 38-05070 Rev. **
Page 9 of 12
CY62148V MoBL™
Package Diagrams (continued)
32-Lead (450 MIL) Molded SOIC S34
Document #: 38-05070 Rev. **
Page 10 of 12
CY62148V MoBL™
Package Diagrams (continued)
32-Lead
TSOP II ZS32
51-85095
Document #: 38-05070 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148V MoBL™
Document Title: CY62148V MoBL™ 512K x 8 MoBL Static RAM
Document Number: 38-05070
Issue
Orig. of
Change
REV.
ECN NO. Date
Description of Change
Change from Spec number: 38-00646 to 38-05070
**
107263
09/15/01
SZV
Document #: 38-05070 Rev. **
Page 12 of 12
相关型号：
CY62148VLL-70BAIT
512KX8 STANDARD SRAM, 70ns, PBGA36, 7 X 8.50 X 1.50 MM, FINE PITCH, TBGA-36
ROCHESTER
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