CY62148VLL-70SI [CYPRESS]
512K x 8 MoBL Static RAM; 512K ×8的MoBL静态RAM
| 型号： | CY62148VLL-70SI |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 8 MoBL Static RAM |
| 文件： | 总11页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MoBL
CY62148V MoBL™
512K x 8 MoBL Static RAM
The device can be put into standby mode when deselected
(CE HIGH).
Features
• Low voltage range:
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O through I/O ) is then written into the location speci-
— 2.7V–3.6V
• Ultra low active power
• Low standby power
0
7
fied on the address pins (A through A ).
0
18
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The eight input/output pins (I/O through I/O ) are placed in a
0
7
The CY62148V is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII,
and a 32-pin SOIC package.
Logic Block Diagram
I/O
0
1
2
Data in Drivers
I/O
I/O
A
A
0
6
1
A
2
A
3
A
4
I/O
I/O
I/O
3
4
5
6
512K x 8
ARRAY
A
5
A
A
A
A
7
8
9
I/O
I/O
POWER
DOWN
COLUMN
DECODER
CE
WE
7
62148V-1
OE
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Cypress Semiconductor Corporation
March 23, 2000
CY62148V MoBL™
Pin
Configurations
FBGA
Top View
TSOPII/SOIC
Top View
4
3
1
2
A1
A2
5
6
A8
I/O
A
V
A
A
1
32
31
30
29
17
16
CC
A
A
A
2
3
4
15
A
NC
A0
6
A
B
C
3
14
18
A
12
WE
A
I/O
WE
4
A7
A
0
28
27
26
25
A
4
7
5
6
13
A
A
8
6
A
5
A
9
A
7
NC
A
I/O
I/O
1
5
5
A
4
8
11
A
24
23
3
OE
9
V
A
V
SS
CC
D
E
F
2
A
10
10
11
12
13
A
22
21
20
19
18
17
1
0
CE
A
I/O
7
V
CC
V
SS
I/O
I/O
0
6
I/O
I/O
I/O
V
1
2
5
14
15
I/O
A18
CE
A
17
I/O
I/O
2
4
6
I/O
SS 16
3
A
G
H
I/O
OE
A15 I/O
3
16
7
A
A
A
13
A
A9
A14
12
11
10
62148V–2
[1]
DC Input Voltage ................................ –0.5V to V + 0.5V
Maximum Ratings
CC
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Industrial
Ambient Temperature
V
CC
DC Voltage Applied to Outputs
[1]
–40°C to +85°C
2.7V to 3.6V
in High Z State ....................................–0.5V to V + 0.5V
CC
Product Portfolio
Power Dissipation (Industrial)
Product
V
Range
Operating (I
)
Standby (I
)
SB2
CC
CC
[2]
[2]
[2]
Min.
Typ.
Max.
Speed
Typ.
Maximum
Ty.p
2 µA
Maximum
CY62148V
2.7V
3.0V
3.6V
70 ns
7
15 mA
20 µA
Notes:
1. IL(min.) = –2.0V for pulse durations less than 20 ns.
V
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
2
CY62148V MoBL™
Electrical Characteristics
Over the Operating Range
CY62148V
[2]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
I
I
= –1.0 mA
V
V
V
V
= 2.7V
= 2.7V
= 3.6V
= 2.7V
2.4
OH
OH
CC
CC
CC
CC
V
= 2.1 mA
0.4
V
OL
OL
V
V
2.2
–0.5
–1
V
+ 0.5V
CC
V
IH
IL
0.8
+1
+1
V
I
I
GND < V < V
CC
+1
+1
µA
µA
IX
I
GND < V < V , Output
–1
OZ
O
CC
Disabled
I
V
Operating Supply
I
f
= 0 mA, (f =
V
= 3.6V
7
15
mA
CC
CC
OUT
MAX
CC
Current
= 1/t ) CMOS
RC
Levels
I
= 0 mA, f = 1 MHz CMOS Levels
1
2
mA
OUT
I
I
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V − 0.3V,
100
µA
SB1
CC
V
V
> V − 0.3V or
IN
IN
CC
< 0.3V, f = f
MAX
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V − 0.3V
L
1
2
50
20
µA
µA
SB2
CC
V > V − 0.3V
IN CC
V
3.6V
=
LL
CC
or V < 0.3V, f = 0
IN
Capacitance[3]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
6
8
pF
pF
IN
A
V
= 3.0V
CC
OUT
Thermal Resistance
Description
Test Conditions
Symbol
Others
BGA
Units
[3]
Thermal Resistance
Still Air, soldered on a 4.25 x 1.125inch, 4-layer
printed circuit board
Θ
TBD
TBD
°C/W
JA
(Junction to Ambient)
[3]
Thermal Resistance
Θ
TBD
TBD
°C/W
JC
(Junction to Case)
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62148V MoBL™
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
90%
OUTPUT
VCC Typ
GND
90%
10%
10%
R2
30 pF
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
62148V–4
62148V–3
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
3.0V
1105
1550
645
Unit
R1
R2
Ohms
Ohms
Ohms
Volts
R
V
TH
TH
1.75V
Data Retention Characteristics
(Over the Operating Range)
[2]
Parameter
Description
Conditions
Min.
1.0
Typ.
Max.
3.6
Unit
V
V
V
for Data Retention
CC
DR
I
Data Retention Current
V
= 1.0V
CC
L/ LL
0.2
5.5
µA
µA
CCDR
CE > V − 0.3V,
CC
V
> V − 0.3V or
IN
CC
V
< 0.3V
IN
No input may exceed
+0.3V
V
CC
[3]
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
CDR
[4]
R
Operation Recovery
Time
t
RC
Note:
4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) > 10 µs.
Data Retention Waveform
DATA RETENTION MODE
1.0V
1.0V
V
DR
> 1.0 V
V
CC
t
t
R
CDR
CE
62148V–5
4
CY62148V MoBL™
[5]
Switching Characteristics
Over the Operating Range
(2.7V–3.6V
Operation)
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
70
AA
Data Hold from Address Change
CE LOW to Data Valid
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
70
35
OE LOW to Data Valid
[6]
OE LOW to Low Z
5
10
0
[7 ]
OE HIGH to High Z
25
25
70
[6]
CE LOW to Low Z
[6, 7]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
PD
[8, 9]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
SA
50
30
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[6, 7]
WE LOW to High Z
25
HZWE
LZWE
[6]
WE HIGH to Low Z
10
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
5
CY62148V MoBL™
Switching Waveforms
[10, 11]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62148V–6
[11, 12]
Read Cycle No. 2
t
RC
CE
t
ACE
OE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
ICC
50%
50%
ISB
62148V–7
[8, 13, 14]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
DATA I/O
NOTE
15
IN
t
HZOE
62148V–8
Notes:
10. Device is continuously selected. OE, CE = VIL
11. WE is HIGH for read cycle.
.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = VIH
.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in output state and input signals should not be applied.
6
CY62148V MoBL™
Switching Waveforms
(continued)
[8, 13, 14]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
62148V–9
[9, 14]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 15
IN
t
t
LZWE
HZWE
62148–10
7
CY62148V MoBL™
Typical DC and AC Characteristics
Standby Current vs. Supply Voltage
45
Normalized Operating Current
vs. Supply Voltage
1.4
40
35
30
25
1.2
1.0
0.8
0.6
20
0.4
15
10
0.2
0.0
1.0
3.7
2.8
1.9
SUPPLY VOLTAGE (V)
1.7
2.2
2.7
3.2
3.7
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
70
60
50
40
30
20
10
1.0
3.7
2.8
SUPPLY VOLTAGE (V)
1.9
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Power
Standby (I
Deselect/Power-Down
Read
)
SB
H
L
Data Out
Data In
High Z
Active (I
Active (I
Active (I
)
CC
L
L
X
Write
)
CC
L
H
H
Output Disabled
)
CC
8
CY62148V MoBL™
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
36-Ball Fine Pitch BGA
70
CY62148VLL-70BAI
CY62148VLL-70ZI
CY62148VLL-70SI
BA37
ZS32
S34
Industrial
32-Lead TSOPII
32-Lead 450 mil. molded SOIC
Document #: 38-00646-C
Package Diagrams
36-Ball (7.00 mm x 8.5 mm x 1.5 mm) Thin BGA BA37
51-85105-A
9
CY62148V MoBL™
Package Diagrams
(continued)
32-Lead (450 MIL) Molded SOIC S34
10
CY62148V MoBL™
Package Diagrams
(continued)
32-Lead
TSOP II ZS32
51-85095
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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