UPD5753T7G-E1 [RENESAS]
SiGe/CMOS Integrated Circuit; SiGe半导体/ CMOS集成电路型号: | UPD5753T7G-E1 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | SiGe/CMOS Integrated Circuit |
文件: | 总15页 (文件大小:270K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PreliminaryData Sheet
μPD5753T7G
R09DS0014EJ0100
Rev.1.00
SiGe/CMOS Integrated Circuit
Feb 22, 2011
4 × 2 IF Switch Matrix with Tone/Voltage Controller
FEATURES
•
•
4 independent IF channels, integral switching to channel input to either channel output
4 × 2 switch matrix with integrated switch control - Tone/Voltage
- Switch’s Enable/Disable function is linked with POLA input voltage level
Switch’s Enable condition : VPOLA > 9.5 V
•
•
•
•
•
•
Frequency range
High isolation
Insertion loss
: f = 250 MHz to 2150 MHz
: ISLD/U = 33 dB TYP. @Worst mode
: LINS = 7 dB TYP. @ ZS = ZL = 50 Ω
: ΔLINS = 1.0 dB TYP.
Insertion loss flatness
20-pin 4 × 4 mm square micro lead package ( 20-pin plastic QFN (0.5 mm pitch))
APPLICATIONS
•
•
•
DBS IF switching
Multiswitch, Switch box
4 × 2 switching application for microwave signal
ORDERING INFORMATION
Part Number
Order Number
Package
Marking
Supplying Form
• Embossed tape 12 mm wide
• Pin 6 to 10 face the perforation side of the tape
• Qty 5 kpcs/reel
μPD5753T7G-E1 μPD5753T7G-E1-A 20-pin plastic QFN D5753
(0.5 mm pitch)
(Pb-Free)
• Dry packing specification (MSL 3 Equivalent)
Remark To order evaluation samples, please contact your nearby sales office.
Part number for sample order: μPD5753T7G
CAUTION
Observe precautions when handling because these devices are sensitive to electrostatic discharge.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 1 of 13
μPD5753T7G
ABSOLUTE MAXIMUM RATINGS (T = +25°C, unless otherwise specified)
A
Parameter
Supply Voltage
Symbol
VDD
Ratings
+4.0
Unit
V
Logic mode Control Voltage
(MO and M1)
VMO, VM1
+4.0
V
Power Dissipation Note
Storage Temperature
Operating Ambient Temperature
Input Power
PD
Tstg
TA
325
mW
°C
°C
dBm
V
−55 to +125
−40 to +85
+15
Pin
POLA Control Input Voltage
(POLA1 and POLA2)
VPOLA
+25
TONE Signal Input Voltage
VTONE
1
Vp-p
Note: Mounted on double-sided copper-clad 50 × 50 × 0.51 mm laminates PWB, TA = +85°C
RECOMMENDED OPERATING RANGE (T = +25°C, unless otherwise specified)
A
Parameter
Supply Voltage
Symbol
VDD
MIN.
+3.0
−40
0
TYP.
MAX.
+3.6
+85
21
Unit
V
+3.3
+25
−
Operating Ambient Temperature
POLA Control Input Voltage
TONE Signal Frequency
TA
°C
V
VPOLA
fTONE
VTONE
18
22
26
kHz
Vp-p
TONE Signal Input Voltage
0.4
0.6
0.8
ELECTRICAL CHARACTERISTICS
(TA = +25°C, VDD = +3.3 V, ZS = ZL = 50 Ω for each port, Worst mode, unless otherwise
specified)
Parameter
Supply Current
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
IDD
Non–RF,
−
1.9
3.0
mA
Non control Signal/Voltage
Pin = 0 dBm, f = 0.95 GHz
Pin = 0 dBm, f = 2.15 GHz
Pin = 0 dBm, f = 2.15 GHz
Pin = 0 dBm, f = 0.95 GHz
Pin = 0 dBm, f = 2.15 GHz
Insertion Loss 1
LINS
LINS
1
2
−
−
28
15
10
14
6.5
7.5
8.5
9.5
−
−
−
dB
dB
dB
dB
dB
V
Insertion Loss 2
Isolation D/U Ratio 2 Note
Output Return Loss 1
Output Return Loss 2
ISLD/U
2
33
RLout
RLout
1
25
2
13
POLA Control Threshold Voltage,
Channel Selection
Vth_POLA OFF to ON
14.75
15.5
TONE Signal Threshold
Voltage, Channel Selection
Vth_TONE fTONE = 22 kHz, Duty Cycle = 50%,
pulse wave, OFF to ON
0.1
0.15
0.35
Vp-p
Note: Isolation D/U (Desire/Un-desire) ratio = ⎪(Signal Leakage (off-state)) − (Insertion loss (on-state))⎪ at Worst mode
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 2 of 13
μPD5753T7G
STANDARD CHARACTERISTICS FOR REFERENCE
(TA = +25°C, VDD = +3.3 V, ZS = ZL = 50 Ω for each port, Worst mode, unless otherwise
specified)
Parameter
Insertion Loss Flatness
Isolation D/U Ratio 1 Note
Input Return Loss 1
Symbol
Test Conditions
|LINS1-LINS2|
Reference Value
Unit
dB
dB
dB
dB
μA
μs
ΔLINS
1.0
40
ISLD/U
1
Pin = 0 dBm, f = 0.95 GHz
Pin = 0 dBm, f = 0.95 GHz
Pin = 0 dBm, f = 2.15 GHz
VPOLA = 21 V
RLin1
RLin2
IPOLA
20
Input Return Loss 2
14
POLA Control Current
POLA Switching Time
TONE Switching Time
230
0.75
220
TPOLA
TTONE
VPOLA = 18 V, OFF to ON
fTONE = 22 kHz, Duty Cycle = 50%,
μs
pulse wave, VTONE = 600 mVp-p
OFF to ON
,
Note: Isolation D/U (Desire/Un-desire) ratio = ⎪(Signal Leakage (off-state)) − (Insertion loss (on-state))⎪ at Worst mode
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 3 of 13
μPD5753T7G
PIN CONNECTIONS
(Top View)
(Bottom View)
Pin 1 Identifier
5
4 3 2 1
1
2
3
4 5
6
7
20
19
20
6
7
19
18
17
16
D 5 7 5 3
8
18
8
GND
9
17
16
9
10
10
11 12 13 14 15
15 14 13 12 11
Pin No.
Pin Name
TONE1
POLA1
GND
Pin No.
Pin Name
IN-B
Pin No.
11
Pin Name
GND
Pin No.
16
Pin Name
OUT2
M1
1
2
3
4
5
6
7
GND
12
IN-C
17
8
GND
13
GND
18
VDD
IN-A
9
GND
14
POLA2
TONE2
19
M0
GND
10
IN-D
15
20
OUT1
Remark Heat Sink (Bottom side) : GND
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 4 of 13
μPD5753T7G
TRUTH TABLE
SWITCHING CONTROL OF OUT1 SIGNAL PATH
SWITCHING CONTROL OF OUT2 SIGNAL PATH
Logic Pattern
Select
CONTROL PINS
for OUT1
OUT1
Logic Pattern
Select
CONTROL PINS
for OUT2
OUT2
M0
M1
POLA1
No Voltage
No Voltage
Low
TONE1
Output Signal
None
None
IN-C
M0
M1
POLA2
No Voltage
No Voltage
Low
TONE2
Output Signal
None
None
IN-C
22 kHz
22 kHz
0
0
22 kHz
22 kHz
0
0
0
0
Low
0
IN-D
Low
0
IN-D
High
0
IN-B
High
0
IN-B
High
22 kHz
IN-A
High
22 kHz
IN-A
No Voltage
No Voltage
Low
22 kHz
None
None
IN-A
No Voltage
No Voltage
Low
22 kHz
None
None
IN-A
0
0
22 kHz
22 kHz
1
0
1
1
1
0
1
0
1
1
1
0
Low
0
IN-B
Low
0
IN-B
High
0
22 kHz
22 kHz
0
IN-D
High
0
22 kHz
22 kHz
0
IN-D
High
IN-C
High
IN-C
No Voltage
No Voltage
Low
None
None
IN-D
No Voltage
No Voltage
Low
None
None
IN-D
22 kHz
0
22 kHz
0
Low
IN-C
Low
IN-C
High
0
IN-B
High
0
IN-B
High
22 kHz
22 kHz
0
IN-A
High
22 kHz
22 kHz
0
IN-A
No Voltage
No Voltage
Low
None
None
IN-B
No Voltage
No Voltage
Low
None
None
IN-B
22 kHz
0
22 kHz
0
Low
IN-A
Low
IN-A
High
0
IN-D
High
0
IN-D
High
22 kHz
IN-C
High
22 kHz
IN-C
Remarks M0, M1 : “0“ : 0 V dc (Connected to GND line)
“1“ : VDD dc (Connected to VDD line)
VDD = + 3.3 V dc
POLA1, 2 : “Low”
“High”
: 9.5 V to 14 V dc
: 15.5 V to 19 V dc
“No Voltage” : 0 V dc (< 5 V dc) or Open
Switch’s Enable/Disable function is linked with POLA input voltage level
Switch’s Enable condition : VPOLA > 9.5 V
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 5 of 13
μPD5753T7G
FUNCTIONAL DIAGRAM
(Top View)
5
1
20
6
IN-B
OUT1
M0
Enable1
GND
GND
GND
IN-D
Switch
Controller
VDD
M1
Enable2
OUT2
16
10
11
15
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 6 of 13
μPD5753T7G
EVALUATION CIRCUIT
330 pF
R = 0 kΩNote
POLA1
POLA control = 13 V/18 V
TONE1
TONE control = 0/22 kHz,
0.6 Vp-p, pluse
10 000 pF (10 nF)
100 pF
RF input A
IN-A
100 pF
OUT1
Output 1
5
1
20
6
100 pF
RF input B
IN-B
Logic mode control
= 0/1 (0 V dc / VDD dc)
Enable1
= Connected to GND line/VDD Line
M0
GND
V
DD
Switch
Controller
GND
GND
VDD = +3.3 V
1 000 pF
M1
100 pF
RF input D
IN-D
Logic mode control
= 0/1 (0 V dc/VDD dc)
= Connected to GND line/VDD Line
Enable2
16
10
11
15
RF input C
IN-C
OUT2
Output 2
100 pF
100 pF
10 000 pF (10 nF)
TONE2
TONE control = 0/22 kHz,
0.6 Vp-p, pluse
POLA2
POLA control = 13 V/18 V
R = 0 kΩNote
330 pF
Note: R = 0 kΩ (at POLA control = 13 V/18 V)
= 5.6 kΩ (at POLA control = 14 V/18 V)
Remarks Heat Sink (Bottom Side): GND
ZS = ZL = 50 Ω
Switch’s Enable/Disable function is linked with POLA input voltage level
Switch’s Enable condition : VPOLA > 9.5 V
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 7 of 13
μPD5753T7G
TYPICAL CHARACTERISTICS
(TA = +25°C, VDD = +3.3 V, Pin = 0 dBm, ZS = ZL = 50 Ω for each port, unless otherwise
specified)
INSERTION LOSS vs. FREQUENCY
(IN x - OUT1)
INSERTION LOSS vs. FREQUENCY
(IN x - OUT2)
-
-
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
ISOLATION D/U RATIO vs. FREQUENCY
(IN A - OUT1)
ISOLATION D/U RATIO vs. FREQUENCY
(IN B - OUT1)
-
-
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
ISOLATION D/U RATIO vs. FREQUENCY
(IN C - OUT1)
ISOLATION D/U RATIO vs. FREQUENCY
(IN D - OUT1)
-
-
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
Remark The graphs indicate nominal characteristics.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 8 of 13
μPD5753T7G
ISOLATION D/U RATIO vs. FREQUENCY
(IN A - OUT2)
ISOLATION D/U RATIO vs. FREQUENCY
(IN B - OUT2)
-
-
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.00.0
0.5
1.0
1.5
2.0
2.5
–90.00.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
ISOLATION D/U RATIO vs. FREQUENCY
(IN C - OUT2)
ISOLATION D/U RATIO vs. FREQUENCY
(IN D - OUT2)
-
-
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.00.0
0.5
1.0
1.5
2.0
2.5
–90.00.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
OUTPUT RETURN LOSS vs. FREQUENCY
(IN x - OUT1)
OUTPUT RETURN LOSS vs. FREQUENCY
(IN x - OUT2)
-
-
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.00.0
0.5
1.0
1.5
2.0
2.5
–60.00.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
Remark The graphs indicate nominal characteristics.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 9 of 13
μPD5753T7G
INPUT RETURN LOSS vs. FREQUENCY
(IN A - OUTx)
INPUT RETURN LOSS vs. FREQUENCY
(IN B - OUTx)
-
-
0.0
0.0
–5.0
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–50.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
INPUT RETURN LOSS vs. FREQUENCY
(IN C - OUTx)
INPUT RETURN LOSS vs. FREQUENCY
(IN D - OUTx)
-
-
0.0
0.0
–5.0
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
Frequency f (GHz)
Frequency f (GHz)
Remark The graphs indicate nominal characteristics.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 10 of 13
μPD5753T7G
MOUNTING PAD LAYOUT DIMENSIONS
20-PIN 4 × 4 mm SQUARE MICRO LEAD PACKAGE (20-PIN PLASTIC QFN (0.5 mm pitch)) (UNIT:
mm)
2.15
1.65
1.35
2.15
1.65
1.35
20-0.2
Remark The mounting pad layout in this document is for reference only.
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 11 of 13
μPD5753T7G
PACKAGE DIMENSIONS
20-PIN 4 × 4 mm SQUARE MICRO LEAD PACKAGE (20-PIN PLASTIC QFN (0.5 mm pitch)) (UNIT:
mm)
(Top View)
(Side View)
0.57
+0.03
–0.05
4 0.1
(Bottom View)
0.15
1.72
Pin 1
0.35 0.075
0.5 0.1
2.7 0.1
Remark A>0
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 12 of 13
μPD5753T7G
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For soldering methods and
conditions other than those recommended below, contact your nearby sales office.
Soldering Method
Soldering Conditions
Condition Symbol
Infrared Reflow
Peak temperature (package surface temperature) : 260°C or below
IR260
Time at peak temperature
: 10 seconds or less
: 60 seconds or less
: 120 30 seconds
: 3 times
Time at temperature of 220°C or higher
Preheating time at 120 to 180°C
Maximum number of reflow processes
Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below
Partial Heating
Peak temperature (package surface temperature) : 350°C or below
HS350
Soldering time (per side of device)
: 3 seconds or less
Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below
CAUTION
Do not use different soldering methods together (except for partial heating).
R09DS0014EJ0100 Rev.1.00
Feb 22, 2011
Page 13 of 13
Revision History
μPD5753T7G Data Sheet
Description
Summary
Rev.
1.00
Date
Page
Feb 22, 2011
−
First edition issued
All trademarks and registered trademarks are the property of their respective owners.
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(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2011 Renesas Electronics Corporation. All rights reserved.
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