ISL97677IRZ-T [RENESAS]
SMBus/I2C 8-Channel LED Driver; QFN32; Temp Range: -40° to 85°C;
| 型号： | ISL97677IRZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SMBus/I2C 8-Channel LED Driver; QFN32; Temp Range: -40° to 85°C 驱动 接口集成电路 |
| 文件： | 总24页 (文件大小：1601K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOL
ETE PROD
UCT
DATASHEET
NO RECO
MMENDE
our Techn
D REPLA
CEMENT
ort Center
contact
ical Supp
RSIL or w
at
il.com/tsc
1-888-INTE
ww.inters
ISL97677
SMBus/I2C 8-Channel LED Driver
FN6996
Rev.2.00
Sep 13, 2017
2
The ISL97677 is an SMBus/I C controlled multi-
channel LED driver for notebook and monitor LCD
backlight applications with PWM dimming and fault
Features
• 8 channels
reporting functions. The ISL97677 is capable of driving
typically 96 pieces of 3.4V/50mA LEDs. The ISL97677
has multiple channels of voltage controlled current
sources with typical currents matching to ±0.7%,
which compensate for the non-uniformity effect of
forward voltages variance in the LED strings. To
minimize the voltage headroom and power loss in the
typical multi-string operation, the ISL97677 features
dynamic headroom control that monitors the highest
LED forward voltage string and uses its feedback signal
for output regulation.
• 4.75V ~ 26V input
• 45V maximum output
• Drive typically 96 LEDs (3.4V/50mA each)
• Dimming controls
2
- SMBus/I C 8-bit PWM dimming
- SMBus and external PWM DPST dimming control
- External PWM dimming with or without
2
SMBus/I C
- PWM dimming range from 0.4% to 100%
• Current matching ±0.7%
• Protections
- String open circuit and short circuit detections,
OVP, and OTP
• Adjustable dimming frequency
• Adjustable switching frequency
• 32 Ld (5mmx5mm) QFN package
The ISL97677 can operate in multiple modes of
2
operations. It can be controlled by SMBus/I C
communications and an external PWM dimming
signal with currents matching of ±1% across all
ranges.
The ISL97677 features extensive protection functions
that include string open and short circuit detections,
OVP, and OTP. The fault conditions will be recorded in
the Fault/Status register. There are selectable short-
circuit thresholds and the switching frequency can be
programmed between 500kHz and 1.5MHz.
Applications
• Notebook displays WLED or RGB LED backlighting
• LCD monitor LED backlighting
The ISL97677 is available in the 32 Leads QFN
5mmx5mm and operate from -40°C to +85°C with
input voltage ranges from 4.75V to 26V.
Related Literature
• For a full list of related documents, visit our
website
- ISL97677 product page
FN6996 Rev.2.00
Sep 13, 2017
Page 1 of 24
ISL97677
Typical Application Circuit
8x12 = 96 LEDs
VIN* = 4.75V~26V
Output 45V*, 50mA per string max
L1
D1
10uH/3A
Co
3x4.7uF
Ci
ISL97677
10uF
1uF
LX1 20
16 VIN
LX2 21
806k
VDC
100pF
3.3nF
18
10
OVP 23
VLOGIC
22k
1uF
SMBCLK/SCL
2
CH1
3 SMBDAT/SDA
25
CH2
26
PWM
EN
4
CH3
CH4
CH5
CH6
CH7
CH8
27
28
17
14
COMP
RSET
FSW
3.3nF
15k
29
30
31
13
11
12
14.2k
50k
FPWM
333k
32
6
AGND
PGND
PGND
1
* Vin > = 12V for 45V/50mA
Applications
7
8
AGND
AGND
19
PGND 22
9
5
AGND
AGND
15 AGND
FIGURE 1. ISL97677 TYPICAL APPLICATION DIAGRAM
FN6996 Rev.2.00
Sep 13, 2017
Page 2 of 24
ISL97677
Block Diagram
45V*, 50mA per string
96 (8x12) LEDs
VIN* = 4.75V~26V
10uH/3A
/EN
2x4.7uF/50V
VIN
LX
VDC
Analog Bias
Logic Bias
REG1
O/P Short
VLOGIC
OVP
REG2
OVP
Fault/Status
Register
Boost SW
fsw
OSC &
RAMP
fSW
Comp
FET
Drivers
Logic
Imax
ILIMIT
PGND
pe
Open Ckt, Short Ckt
Detects
Fault/Status Control
COMP
GM
AMP
CH1
CH2
Highest VF
String Detect
CH8
Temp
1
VSET
+
-
Sensor
+
-
REF
GEN
RSET
Fault/Status
Register
REF_OVP
REF_VSC
2
+
-
AGND
SMBCLK/SCL
SMBus
SMBDAT/SDA
Interface
* Vin >=12V for 45V/50mA apps
PWMI
Mode
Select &
Dimming
Controller
fPWM
PWM
Controller
+
-
8
ISL97677
FIGURE 2. ISL97677 BLOCK DIAGRAM
Ordering Information
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
PART NUMBER
PART MARKING
ISL9767 7IRZ
ISL97677IRZ (Notes 1, 2)
NOTES:
32 Ld 5x5 QFN
L32.5x5B
1. Add “-T” suffix for 6k unit or “-TK” for 1k unit tape and reel options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the product information page for ISL97677. For more information on MSL, see TB363.
FN6996 Rev.2.00
Sep 13, 2017
Page 3 of 24
ISL97677
Pin Configuration
ISL97677
(32 LD 5X5 QFN)
TOP VIEW
32 31 30 29 28 27 26 25
PGND
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SMBCLK/SCL
SMBDAT/SDA
PWM
OVP
PGND
LX
EXPOSED THERMAL PAD
AGND
LX
AGND
PGND
VDC
EN
AGND
AGND
9
10 11 12 13 14 15 16
Pin Descriptions
(I = Input, O = Output, S = Supply)
PIN
NAME
PGND
TYPE
DESCRIPTION
1, 19, 22
S
I
Power Ground
2
2
3
4
SMBCLK/SCL
SMBDAT/SDA
PWM
SMBus/I C Serial Clock Input
2
I/O
I
SMBus/I C Serial Data Input and Output
PWM Brightness Control
Analog Ground
5, 6, 7, 8, 9,
15
AGND
S
10
11
VLOGIC
FSW
O
I
Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation
When R
When R
is 100k, f
is 33k, f
SW
is 500kHz.
is 1.5MHz
fSW
fSW
SW
12
FPWM
I
When R
When R
is 333k, F
is 3.3k, F
is 200Hz.
is 20kHz.
FPWM
FPWM
PWM
PWM
13
14
RSET
COMP
VIN
I
O
S
I
Resistor Connection for Setting LED Current
Boost compensation
16
Main Power
17
EN
Enable
18
VDC
S
O
I
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation
Boost MOSFET Drain Terminal Switching Node
Overvoltage Protection Input as well as Output Voltage FB Monitoring
No Connect
20, 21
23
LX
OVP
24
NC
I/O
I
25 ~ 32
CH1 ~ CH8
LED Driver PWM Dimming Monitoring
FN6996 Rev.2.00
Sep 13, 2017
Page 4 of 24
ISL97677
Absolute Maximum Ratings
Thermal Information
voltage ratings are all with respect to AGND pin
Thermal Resistance (Typical)
(°C/W)
(°C/W)
3
JA
JC
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
VLOGIC. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
VDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . -0.3V to min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (VDC + 0.3V, 5.75V)
SMBCLK, SMBDAT, PWM . . . . . . . . . . . . . . . -0.3V to 5.75V
CH1 - CH8, LX, OVP . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
32 Ld QFN (Notes 4, 5) . . . . . . . . .31
Thermal Characterization (Typical, Note 6)
PSI (°C/W)
JT
32 Ld QFN. . . . . . . . . . . . . . . . . . . . . . . . .
0.2
Maximum Continuous Junction Temperature . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Power Dissipation
T < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W
A
T < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W
A
T < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
A
T < +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
A
Recommended Operating Conditions
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . see TB493
Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for
details.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. PSI is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this
JT
rating then the die junction temperature can be estimated more accurately than the and thermal resistance ratings.
JC JC
5.
Electrical Specifications
All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V, I = 36kΩ, unless
A
IN
SET
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 7)
MAX
(Note 7) UNIT
PARAMETER
GENERAL
DESCRIPTION
CONDITION
TYP
V
Backlight Supply Voltage
4.75
26
(Note 8)
V
IN
I
VIN Shutdown Current
/SHUT = 0
5
µA
V
VIN_SHDN
V
V
V
Output Voltage
45
3.3
OUT
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
2.9
4.8
2.3
V
UVLO
300
mV
UVLO_HYS
LINEAR REGULATOR
V
V
5V Analog Bias Regulator
VDC LDO Dropout Voltage
Active Current
V
> 6V
5
5.1
V
DC
IN
I
= 30mA
71
10
2.4
31
100
mV
mA
V
DC_DROP
VDC
VDC
/SHUT = 5V, R = 33k
> 6V
I
V
V
2.5V Logic Bias Regulator
V
2.5
LOGIC
IN
V
LDO Dropout Voltage
I = 30mA
VLOGIC
100
mV
LOGIC_DROP
LOGIC
BOOST SWITCHING REGULATOR
SS
Soft-Start
16
ms
A
SW
Boost FET Current Limit
Internal Boost Switch ON-Resistance
T = +25°C to +85°C
3.0
4.7
ILimit
A
r
130
m
DS(ON)
FN6996 Rev.2.00
Sep 13, 2017
Page 5 of 24
ISL97677
Electrical Specifications
All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V, I = 36kΩ, unless
SET
A
IN
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Eff_peak
DESCRIPTION
Peak Efficiency
CONDITION
(Note 7)
TYP
(Note 7) UNIT
V
= 24V, 96LEDs,
20mA each, L = 10µH
with DCR 100m
92.4
%
%
%
%
%
%
IN
f
= 600kHz,
SW
T = +25°C
A
V
= 12V, 96 LEDs,
20mA each, L = 10µH
with DCR 100m
=600kHz,
T = +25°C
91.5
81.6
93.4
90.7
IN
f
SW
A
V
= 6V, 96 LEDs,
20mA each, L = 10µH
with DCR 100m
IN
f
= 600kHz,
SW
T = +25°C
A
V
= 24V, 80 LEDs,
40mA each, L = 10µH
with DCR 100m
IN
f
= 600kHz,
SW
T = +25°C
A
V
= 12V, 80 LEDs,
40mA each, L = 10µH
with DCR 100m
IN
f
= 600kHz,
SW
T = +25°C
A
D
D
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
Boost Switching Frequency
f
f
= 500kHz
= 500kHz
= 100k
= 33k
90
MAX
MIN
SW
10
0.55
1.65
10
%
SW
f
R
R
0.45
1.35
0.5
1.5
MHz
MHz
µA
SW
fsw
fsw
ILX_leakage
Lx Leakage Current
VLX = 45V, /SHUT = 0V
REFERENCE
I
I
Channel-to-Channel CurrentMatching I
= 20mA
-1.1
-1.5
±0.7
+1.1
+1.5
%
%
MATCH
ACC
LED
Absolute Current Accuracy
I
= 36k
RSET
T = +25°C
A
I
= 36k
-2
+2
%
RSET
A
T = -40°C to +80°C
FAULT DETECTION
V
Channel Short Circuit Threshold
SMBus Register0x0F,
SC[1:0] = 01
2.4
3.3
4.2
3.6
4.6
5.6
V
V
V
SC
SMBus Register0x0F,
SC[1:0] = 10
SMBus Register0x0F,
SC[1:0] = 11
V
V
Over-Temperature Threshold
150
5
°C
°C
temp
Over-Temperature Threshold
Accuracy
temp_acc
V
Overvoltage Limit on OVP Pin
1.18
1.22
1.24
V
OVP
FN6996 Rev.2.00
Sep 13, 2017
Page 6 of 24
ISL97677
Electrical Specifications
All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V, I = 36kΩ, unless
SET
A
IN
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 7)
TYP
(Note 7) UNIT
SMBus INTERFACE (SMBus Mode, 1D_EN = 0)
V
V
V
Logic Input Low Voltage -
SMBCLK/SCL, SMBDAT/SDA
0.8
5.5
0.4
V
V
V
IL
Logic Input High Voltage -
SMBCLK/SCL, SMBDAT/SDA
1.5
IH
OL
SMBus Data Line Logic Low Voltage
with 1.1kseries resistor from data
bus to SMBDAT pin
I
I
= 350µA
= 4mA
PULLUP
PULLUP
SMBus Data Line Logic Low Voltage
without series resistor from data bus
to SMBDAT pin
0.17
250
V
SMBus TIMING SPECIFICATIONS
f
SMBus Clock Frequency
kHz
µs
SMB
t
Bus Free Time Between Stop and
Start Condition
4.7
4.0
BUF
t
Hold Time After (Repeated) START
Condition. After this Period, the First
Clock is Generated
µs
HD:STA
t
t
t
t
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time (Note 9)
Data Setup Time (Note 9)
Clock Low Period
4.7
4.0
300
250
4.7
4.0
µs
µs
ns
ns
µs
µs
ns
SU:STA
SU:STO
HD:DAT
SU:DAT
LOW
Clock High Period
HIGH
Clock/Data Fall Time (Note 9)
300
F
CURRENT SOURCES
V
V
V
Dominant Channel Current Source
Headroom at CH Pin
I
= 50mA
LED
A
1.0
(Note 10)
V
HEADROOM
HEADROOM_RANGE
ISET
T = +25°C
Dominant Channel Current Sink
Headroom Range at CHx Pin
I
= 50mA
90
mV
LED
T = +25°C
A
Voltage at ISET Pin
1.18
1.21
50
1.24
V
ILEDmax
Maximum LED Current per Channel
LED config = 8P10S
with VF = 3.4V and
mA
V
= 11V
IN
PWM GENERATOR
FPWM
Generated PWM Frequency
R
R
= 330k
= 3.3k
180
18
200
20
220
22
Hz
kHz
%
FPWM
FPWM
Dimming Range
VFSW
PWM Dimming Duty Cycle Limits
(Note 9)
f
30kHz
0.4
100
PWM
FSW Voltage
R
= 33k
1.18
1.21
1.24
V
FSW
FN6996 Rev.2.00
Sep 13, 2017
Page 7 of 24
ISL97677
Electrical Specifications
All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V, I = 36kΩ, unless
SET
A
IN
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
FPWMI
DESCRIPTION
CONDITION
(Note 7)
TYP
(Note 7) UNIT
PWMI Input Frequency Range
(Note 9)
200
20k
Hz
VFPWM
NOTES:
VFPWM Voltage
R
= 3.3k
1.18
1.21
1.25
V
FPWM
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. At maximum V of 26V, minimum V
IN OUT
is 28V. Minimum V
OUT
can be lower at lower V
IN
9. Limits established by characterization and are not production tested.
10. Varies within range specified by V
.
HEADROOM_RANGE
Typical Performance Curves
100
95
90
85
80
75
70
100
20mA
8P11S
SW
50mA
8P11S
SW
-40°C
f
= 600kHz
95
90
85
80
75
70
f
= 600kHz
0°C
0°C
-40°C
+85°C
+85°C
+25°C
+25°C
10
0
5
10
15
(V)
20
25
30
0
5
15
(V)
20
25
30
V
V
IN
IN
FIGURE 3. EFFICIENCY vs V
50mA
vs TEMPERATURE AT
FIGURE 4. EFFICIENCY vs V
20mA
vs TEMPERATURE AT
IN
IN
100
95
94
93
50mA
8P11S
8P10S
95
90
85
80
75
70
65
60
55
50
45
40
35
30
92
12V/50mA
24V
91
90
89
88
87
24V/50mA
12V
1k
86
85
84
0
10
20
I
30
(mA)
40
50
400
600
800
1.2k
1.4k
1.6k
SWITCHING FREQUENCY (Hz)
LED
FIGURE 5. EFFICIENCY vs I
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY
LED
FN6996 Rev.2.00
Sep 13, 2017
Page 8 of 24
ISL97677
Typical Performance Curves(Continued)
1.0
1.0
0.8
20mA - 8P12S
50mA - 8P11S
50mA
8P11
0.8
0.6
0.6
0°C
12V/20mA
0.4
0.4
0.2
0.2
0.0
0.0
+25°C
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
+85°C
12V/50mA
-40°C
15
1
2
3
4
5
6
7
8
0
5
10
20
25
30
CHANNEL
V
(V)
IN
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT
MATCHING EXAMPLE
FIGURE 8. CURRENT MATCHING vs V
TEMPERATURE
vs
IN
2.0
2.0
20mA - 8P12S
50mA - 8P11S
20mA - 8P12S
50mA - 8P11S
1.8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
12V/50mA
1.6
12V/50mA
1.4
24V/50mA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5V/20mA
12V/20mA
HEADROOM CONTROL CHANNEL
24V/20mA
1
2
3
4
5
6
7
8
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
PWM DIMMING DUTY CYCLE (%)
CHANNEL
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM
DIMMING DUTY CYCLE
FIGURE 10. TYPICAL CHANNEL VOLTAGE EXAMPLE
1.0
1.00
20mA
50mA
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
8P11S
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
8P11S
+25°C
+85°C
+85°C
+25°C
0°C
20
0°C
0
5
10
15
IN
25
30
0
5
10
15
(V)
20
25
30
V
(V)
V
IN
IN
FIGURE 12. V
vs V
vs TEMPERATURE AT
HEADROOM
20mA
FIGURE 11. V
vs V
vs TEMPERATURE AT
IN
HEADROOM
50mA
FN6996 Rev.2.00
Sep 13, 2017
Page 9 of 24
ISL97677
Typical Performance Curves(Continued)
10
/SHUT = HIGH
9
8
7
6
5
4
3
2
1
0
PWM DUTY CYCLE = 0%
LX (20V/DIV)
+85°C
V
(100mV/DIV)
O
-40°C
I
(20mA/DIV)
LED
0
5
10
15
(V)
20
25
vs
30
V
IN
FIGURE 13. QUIESCENT CURRENT vs V
IN
FIGURE 14. V
RIPPLE VOLTAGE
OUT
TEMPERATURE WITH /SHUT ENABLE
V
(20V/DIV)
O
V
(20V/DIV)
O
EN (5V/DIV)
EN (5V/DIV)
I
(1A/DIV)
IN
I
(1A/DIV)
IN
I
(50mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 16. IN-RUSH CURRENT AND LED CURRENT
AT V = 26V
FIGURE 15. IN-RUSH CURRENT and LED CURRENT AT
= 12V
IN
V
IN
V
(10V/DIV)
IN
V
(10V/DIV)
IN
I
(500mA/DIV)
IN
I
(500mA/DIV)
IN
I
(50mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 17. LINE REGULATION WITH V
CHANGES
FROM 12V TO 26V DISABLE PROFILE
FIGURE 18. LINE REGULATION WITH V
FROM 26V TO 12V
CHANGES
IN
IN
FN6996 Rev.2.00
Sep 13, 2017
Page 10 of 24
ISL97677
Typical Performance Curves(Continued)
V
(1V/DIV)
O
V
(1V/DIV)
O
I
(20mA/DIV)
LED
I
(20mA/DIV)
LED
FIGURE 19. LOAD REGULATION WITH I
CHANGES
FIGURE 20. LOAD REGULATION WITH I
CHANGES
LED
FROM 0.4% TO 100% PWM DIMMING
LED
FROM 100% TO 0.4% PWM DIMMING
V
(1V/DIV)
V
(500mV/DIV)
O
O
I
(20mA/DIV)
LED
I
(20mA/DIV)
LED
FIGURE 22. LOAD REGULATION WITH I
CHANGES
FIGURE 21. LOAD REGULATION WITH I
CHANGES
LED
LED
FROM 0% TO 100% PWM DIMMING
FROM 100% to 0% PWM DIMMING
V
(20V/DIV)
O
EN (5V/DIV)
I
(1A/DIV)
IN
I
(50mA/DIV)
LED
FIGURE 23. DISABLE PROFILE
FN6996 Rev.2.00
Sep 13, 2017
Page 11 of 24
ISL97677
short circuit threshold, V , such voltage will be used as
SC
Theory of Operation
PWM Boost Converter
the feedback signal for the boost regulator. The boost
makes the output to the correct level such that the
lowest CH pin is at the target headroom voltage. Since all
LED strings are connected to the same output voltage,
the other CH pins will have a higher voltage, but the
regulated current source circuit on each channel will
ensure that each channel has the same programmed
current. The output voltage will regulate cycle by cycle
and is always referenced to the highest forward voltage
string in the architecture.
The current mode PWM boost converter produces the
minimal voltage needed to enable the LED string with the
highest forward voltage drop to run at the programmed
current. The ISL97677 employs current mode control
boost architecture that has a fast current sense loop and
a slow voltage feedback loop. Such architecture achieves
a fast transient response that is essential for the
notebook backlight application where the power can be
several Li-ion cell batteries or instantly change to an
AC/DC adapter without rendering a noticeable visual
nuisance. The number of LEDs that can be driven by
ISL97677 depends on the type of LED chosen in the
application. The ISL97677 is capable of boosting up to
45V and drive 8 channels of LEDs at maximum of 45mA
per channel.
OVP and V
Requirement
OUT
The Overvoltage Protection (OVP) pin has a function of
setting the overvoltage trip level as well as limiting the
V
regulation range.
OUT
The ISL97677 OVP threshold is set by R
and
UPPER
R
as shown in Equation 1:
LOWER
Current Matching and Current Accuracy
V
= 1.21V R
+ R
R
LOWER LOWER
(EQ. 1)
OUT_OVP
UPPER
Each channel of the LED current is regulated by the
current source circuit, as shown in Figure 24.
V
V
can only regulate between 64% and 100% of the
OUT
_
such that:
OUT OVP
The LED peak current is set by translating the R
current to the output with a scaling factor of 707.9/R
SET
.
Allowable V
OUT
= 64% to 100% of V
_
SET
OUT OVP
The sink terminals of the current source MOSFETs are
designed to operate within a range at about 500mV to
optimize power loss versus accuracy requirements. The
sources of errors of the channel-to-channel current
matching come from the op amps offset, internal layout,
reference, and current source resistors. These
parameters are optimized for current matching and
absolute current accuracy. However, the absolute
accuracy is additionally determined by the external R
A 0.1% tolerance resistor is recommended.
For example, if 10 LEDs are used with the worst case
of 35V. If R and R are chosen such that the OVP
V
OUT
1
2
level is set at 40V, then the V
is allowed to operate
OUT
between 25.6V and 40V. If the requirement is changed to
a 6 LEDs 21V V application, then the OVP level must
OUT
be reduced and users should follow V
= (64%
OUT
~100%)OVP requirement. Otherwise, the headroom
control will be disturbed such that the channel voltage
can be much higher than expected and sometimes it can
prevents the driver from operating properly.
.
SET
.
The ratio of the OVP capacitors should be the inverse of
the OVP resistors. For example, if R
/R =
UPPER LOWER
33/1, then C
and C
/C
= 3.3nF.
=1/33 with C = 100pF
UPPER LOWER
UPPER
LOWER
Dimming Controls
The ISL97677 allows two ways of controlling the LED
current, and therefore, the brightness. They are:
+
-
1. DC current adjustment
+
REF
-
2. PWM chopping of the LED current defined in Step 1.
There are various ways to achieve DC or PWM current
control, which will be described in the following.
RSET
+
-
In any dimming controls, the EN pin must be high. EN is
a high voltage pin that can be applied with a digital signal
PWM DIMMING
or tied directly to V for enable function.
IN
MAXIMUM DC CURRENT SETTING
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
The initial brightness should be set by choosing an
Dynamic Headroom Control
appropriate value for R
. This should be chosen to fix
SET
The ISL97677 features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage
string or effectively the lowest voltage from any of the
the maximum possible LED current:
707.9
--------------
I
=
LEDmax
(EQ. 2)
R
SET
CH pins. When this lowest I voltage is lower than the
IN
FN6996 Rev.2.00
Sep 13, 2017
Page 12 of 24
ISL97677
Alternatively, the R
can be replaced by digital
limit level is set to one ninth of the full current limit, with
subsequent steps increasing this by a ninth every 2ms.
In the event that no LEDs have been conducting during
the interval since the last step (for example, if the LEDs
are running at low duty cycle at low PWM frequency)
then the step will be delayed until the LEDs are
conducting. If the LEDs are disabled and re-enabled
again then soft start will be restarted when the LEDs are
enabled.
SET
potentiometer for adjustable current. On the other hand,
the current accuracy is designed when RSET is set at
20m to 40mA.
PWM CONTROL
The ISL97677 also provides PWM dimming by PWM
chopping of the current in the LEDs for all 8 channels to
provide an average LED current. During the On periods,
the LED current will be defined by the value of R
described in Equation 1.
, as
SET
Fault Protection and Monitoring
The ISL97677 features extensive protection functions to
cover all the perceivable failure conditions. The failure
mode of a LED can be either open circuit or as a short.
The behavior of an open circuited LED can additionally
take the form of either infinite resistance or, for some
LEDs, a zener diode, which is integrated into the device
in parallel with the now opened LED.
PWM Dimming Frequency Adjustment
The dimming frequencies of all modes are set by an
external resistor at the FPWM pin as shown in
Equation 3:
7
6.6610
-----------------------
=
(EQ. 3)
f
PWM
RPWM
For basic LEDs (which do not have built-in zener diodes),
an open circuit failure of an LED will only result in the loss
of one channel of LEDs without affecting other channels.
Similarly, a short circuit condition on a channel that
results in that channel being turned off does not affect
other channels unless a similar fault is occurring. All LED
faults are reported via the SMBus interface to Register
0x02 (Fault/Status register).
where f
is the desirable PWM dimming frequency and
is the setting resistor.
PWM
R
FPWM
External PWM Dimming
The ISL97677 can operate as basic PWM dimming LED
driver with or without the need of SMBus/I C interface.
To do so, users need to set EN = high and SMBCLK/SCL
= grounded or floating, SMBDAT/SDA = grounded or
floating. The EN is a high voltage pin that can be applied
with a digital I/O signal or tie to V . The PWM output will
follow the PWM input and the dimming frequency will be
set by R
2
Due to the lag in boost response to any load change at its
output, certain transient events (such as significant step
changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97677 uses feedback from the LEDs
to determine when it is in a stable operating region and
prevents apparent faults during these transient events
from allowing any of the LED strings to fault out. See
Table 1 for more details.
IN
.
PWM
Switching Frequency
The boost switching frequency can be adjusted by a
resistor as shown in Equation 4:
10
Short Circuit Protection (SCP)
510
-----------------------
(EQ. 4)
f
=
SW
R
The short circuit detection circuit monitors the voltage on
each channel and disables faulty channels which are
detected above the programmed short circuit threshold.
There are three selectable levels of short circuit threshold
(3V, 4V, and 5V) that can be programmed through the
Configuration Register 0x0F. When an LED becomes
shorted, the action taken is described in Table 1. The
default short circuit threshold is 4V. The detection of this
failure mode can be disabled by SMBus interface via
Register 0x0F.
OSC
where f
is the desirable boost switching frequency
is the setting resistor.
SW
and R
OSC
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop
the necessary low voltage supply, which is used by the
chips internal control circuitry. Because VDC is an LDO
pin, it requires a bypass capacitor of 1µF or more for the
regulation. The VDC pin can be used for a coarse
regulator or reference but do not pull more than few mA
from it.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can
behave as either an infinite resistance or a gradually
increasing finite resistance. The ISL97677 monitors the
current in each channel such that any string which
reaches the intended output current is considered
“good”. Should the current subsequently fall below the
target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97677
reach the OVP limit or should the lower over-temperature
threshold be reached, all channels which are not “good”
will immediately be considered as “open circuit”.
Similarly, a 2.3V LDO regulator is present at the
VLOGIC pin to develop the necessary low voltage supply
for the chip’s internal logic control circuitry. A 1µF
bypass capacitor or more is needed for regulation. The
VLOGIC pin can be used as a coarse regulator or
reference but do not pull more than few mA from it.
Soft-Start
The ISL97677 uses a digital soft-start where the boost
current limit is stepped up in 8 steps. The initial current
FN6996 Rev.2.00
Sep 13, 2017
Page 13 of 24
ISL97677
Detection of an “open circuit” channel will result in a
time-out before disabling of the affected channel.
Fault/Status register 0x02. Unless disabled via the /SHUT
pin, the device stays in an active state throughout,
allowing the external processor to interrogate the fault
condition.
Some users employ some special types of LEDs that
have zener diode structure in parallel with the LED for
ESD enhancement, thus enabling open circuit operation.
When this type of LED goes open circuit, the effect is as
if the LED forward voltage has increased, but no light
will be emitted. Any affected string will not be disabled,
unless the failure results in the boost OVP limit being
reached, allowing all other LEDs in the string to remain
functional. Care should be taken in this case that the
boost OVP limit and SCP limit are set properly, so as to
make sure that multiple failures on one string do not
cause all other good channels to be faulted out. This is
due to the increased forward voltage of the faulty
channel making all other channel look as if they have
LED shorts. See Table 1 for details for responses to fault
conditions.
For the extensive fault protection conditions, please refer
to Figure 25 and Table 1 for details.
Shutdown
When the EN pin is low the entire chip is shut down to
give close to zero shutdown current. The digital
interfaces will not be active during this time.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage
and keeps the voltage at a safe level. The OVP threshold
is set as shown in Equation 5:
OVP = 1.21V R
+ R
R
LOWER LOWER
(EQ. 5)
UPPER
These resistors should be large to minimize the power
loss. For example, a 1Mk R and 30k R
UPPER LOWER
sets OVP to 41.2V. Large OVP resistors also allow C
discharges slowly during the PWM Off time. Parallel
OUT
capacitors should be placed across the OVP resistors
such that R /R = C /C . Using a
UPPER LOWER LOWER UPPER
value of at least 30pF is recommended. These
C
UPPER
capacitors reduce the AC impedance of the OVP node,
which is important when using high value resistors.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the
device will stop switching and be reset. Operation will
restart only if the device control interface re-enables it
once the input voltage is back in the normal operating
range. Also all digital settings will be reset to their default
states.
Over-Temperature Protection (OTP)
The ISL97677 includes two over-temperature thresholds.
The lower threshold is set to +130°C. When this
threshold is reached, any channel which is outputting
current at a level significantly below the regulation target
will be treated as “open circuit” and disabled after a
time-out period. The intention of the lower threshold is to
allow bad channels to be isolated and disabled before
they cause enough power dissipation (as a result of other
channels having large voltages across them) to hit the
upper temperature threshold.
The upper threshold is set to +150°C. Each time this is
reached, the boost will stop switching and the output
current sources will be switched off and stay off until the
control interface disables and re-enables it. Hitting of the
upper threshold will also set the thermal fault bit of the
FN6996 Rev.2.00
Sep 13, 2017
Page 14 of 24
ISL97677
LX
VIN
VOUT
LX
FAULT
O/P
DRIVER
SHORT
OVP
FET
LOGIC
IMAX
ILIMIT
DRIVER
CH1
VSC
CH8
VSET/2
REG
THRM
SHDN
REF
T2
TEMP
SENSOR
OTP
T1
+
+
-
VSET
VSET
Q1
Q8
-
PWM1/OC1/SC1
PWM8/OC8/SC8
SMBUS
CONTROL
LOGIC
FAULT/
STATUS
REGISTER
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
TABLE 1. PROTECTIONS TABLE
V
OUT
REGULATED
BY
CASE FAILURE MODE DETECTION MODE
FAILED CHANNEL ACTION GOOD CHANNELS ACTION
1
CH1 Short Circuit Upper
Over-Temperature
CH1 ON and burns power
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
Protection limit (OTP)
not triggered and
VI
< VSC
IN0
2
3
CH1 Short Circuit Upper OTP triggered
but V < VSC
CH1 goes off
Same as CH1
Highest VF of
CH2 through
CH8
IN1
CH1 Short Circuit Upper OTP not
CH1 disabled after 6 PWM
cycles time-out.
If 3 channels are already
shut down, all channels will CH2 through
be shut down. Otherwise
Highest VF of
triggered but VI
VSC
>
IN1
CH8
CH2-8 will remain as normal
4
CH1 Open Circuit Upper OTP not
V
will ramp to OVP. CH1 will CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
OUT
time-out after 6 PWM cycles
with infinite
resistance
triggered and VIIN1
< VSC
and switch off. V
to normal level.
will drop
OUT
5
6
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not
triggered and VI
VSC
CH1 remains ON and has
CH2 through CH8 ON, Q2
through Q8 burn power
VF of CH1
VF of CH1
< highest VF, thus V
increases
IN1
OUT
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered CH1 goes off
but VI < VSC
Same as CH1
IN1
FN6996 Rev.2.00
Sep 13, 2017
Page 15 of 24
ISL97677
TABLE 1. PROTECTIONS TABLE (Continued)
V
OUT
REGULATED
BY
CASE FAILURE MODE DETECTION MODE
FAILED CHANNEL ACTION GOOD CHANNELS ACTION
7
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not
triggered but VIIN1 >
VSC
CH1 OFF
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
Upper OTP not
triggered but VIINx > highest VF, thus V
VSC
CH1 remains ON and has
V
increases then CH-X
VF of CH1
OUT
switches OFF. This is an
unwanted shut off and can
be prevented by setting OVP
and/or VSC at an
OUT
increases.
appropriate level.
8
9
Channel-to-
Channel VF too
high
Lower OTP triggered Any channel at below the target current will fault out after
Highest VF of
CH1 through
CH8
but VIINx < VSC
6 PWM cycles.
Remaining channels driven with normal current.
Channel-to-
Channel VF too
high
Upper OTP triggered All channels switched off
but VIINx < VSC
Highest VF of
CH1 through
CH8
10
11
Output LED string
voltage too high
V
> VOVP
Driven with normal current. Any channel that is below the
target current will time-out after 6 PWM cycles.
Highest VF of
CH1 through
CH8
OUT
V
/LX shorted
LX will not switch
OUT
to GND
t
t
F
R
SMBCLK
t
LOW
V
IH
V
IL
t
HIGH
t
SU:STA
t
HD:DAT
t
HD:STA
t
t
SU:STO
SU:DAT
SMBDAT
V
IH
V
IL
t
BUF
P
P
S
S
NOTES:
SMBus Description
S = Start condition
P = Stop condition
A = Acknowledge
A = Not acknowledge
R/W = Read enable at high; Write enable at low
FIGURE 26. SMBUS INTERFACE
FN6996 Rev.2.00
Sep 13, 2017
Page 16 of 24
ISL97677
1
S
7
1
1
A
8
1
A
8
1
A
1
P
SLAVE ADDRESS
W
COMMAND CODE
DATA BYTE
Master to Slave
Slave to Master
FIGURE 27. WRITE BYTE PROTOCOL
1
S
7
1
1
A
8
1
A
1
S
8
1
1
A
8
1
A
1
P
SLAVE
ADDRESS
W
COMMAND
CODE
SLAVE ADDRESS
R
DATA BYTE
Master to Slave
Slave to Master
FIGURE 28. READ BYTE PROTOCOL
FN6996 Rev.2.00
Sep 13, 2017
Page 17 of 24
ISL97677
confusion. Therefore, if the device is in the write mode
where bit 0 is 0, the slave address byte is 0x58 or
01011000b. If the device is in the read mode where bit 0
is 1, the slave address byte is 0x59 or 01011001b.
Write Byte
The Write Byte protocol is only three bytes long. The first
byte starts with the slave address followed by the
“command code,” which translates to the “register index”
being written. The third byte contains the data byte that
must be written into the register selected by the
“command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives”
the Data line. All other cycles are driven by the “host
master.”
The backlight controller may sense the state of the pins
at POR or during normal operation—the pins will not
change state while the device is in operation.
MSB
LSB
Read Byte
0
1
0
1
1
0
0
R/W
As shown in the Figure 28, the four byte long Read Byte
protocol starts out with the slave address followed by
the “command code” which translates to the “register
index.” Subsequently, the bus direction turns around
with the rebroadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains
the data being returned by the backlight controller. That
byte value in the data byte reflects the value of the
register being queried at the “command code” index.
Note the bus directions, which are highlighted by the
shaded label that is used on cycles during which the
slaved backlight controller “owns” or “drives” the Data
line. All other cycles are driven by the “host master.”
DEVICE
IDENTIFIER
DEVICE
ADDRESS
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION
SMBus Register Definitions
The backlight controller registers are Byte wide and
accessible via the SMBus Read/Write Byte protocols.
Their bit assignments are provided in the following
sections with reserved bits containing a default value
of “0”.
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W
bit, but these 8 bits are usually called Slave Address
bytes. As shown in Figure 29, the high nibble of the slave
address byte is 0x5 or 0101b to denote the “backlight
controller class.” Bit 3 in the lower nibble of the slave
address byte is 1. Bit 0 is always the R/W bit, as specified
by the SMBus protocol. Note: In this document, the
device address will always be expressed as a full 8-bit
address instead of the shorter 7-bit address typically
used in other backlight controller specifications to avoid
TABLE 2A. REGISTER LISTING
DEFAULT
VALUE
SMBUS
PROTOCOL
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x00
PWM Brightness
Control Register
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
0xFF
0x00
0x00
0xC8
Read and Write
Read and Write
Read Only
0x01
0x02
0x03
Device Control
Register
Reserved Reserved Reserved Reserved Reserved PWM_MD
PWM_SEL
BL_CTL
Fault/Status
Register
Reserved Reserved 2_CH_SD 1_CH_S BL_STAT OV_CURR THRM_SHDN FAULT
D
Identification
Register
LED
PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
Read Only
FN6996 Rev.2.00
Sep 13, 2017
Page 18 of 24
ISL97677
TABLE 2B. DATA BIT DESCRIPTIONS
DATA BIT DESCRIPTIONS
ADDRESS
REGISTER
0x00
PWM Brightness Control
Register
BRT[7..0] = 256 steps of DPWM duty cycle brightness control
0x01
Device Control Register
PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change),
default = 0
PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by
SMBus), default = 0
BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0
PWM_MD PWM_SEL
MODE
X
1
0
1
0
0
PWMI Mode
SMBus Mode
SMBus and PWMI mode with
DPST
0x02
0x03
Fault/Status Register
Identification Register
2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK)
1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK)
BL_STAT = BL status (1 = BL On, 0 = BL Off)
OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK)
THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK)
FAULT = Fault occurred (Logic “OR” of all of the fault conditions)
MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9)
REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
unless otherwise written. Bits 7 and 6 are not
implemented and will always read low.
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM
duty cycle adjustment. The bit assignment is shown in
Tables 2A and 2B. All of the bits in this Brightness Control
Register can be read or write. Step 0 corresponds to the
minimum step where the current is less than 10µA. Steps
1 to 255 represent the linear steps between 0.39% and
100% duty cycle with approximately 0.39% duty cycle
adjustment per step.
TABLE 3. OPERATING MODES SELECTED BY DEVICE
CONTROL REGISTER BITS 1 AND 2
PWM_MD PWM_SEL
MODE
X
1
0
1
0
0
PWMI Mode
SMBus Mode
SMBus and PWMI Mode with DPST
• An SMBus Write Byte cycle to Register 0x00 sets the
PWM brightness level only if the backlight controller
is in SMBus mode (see Table 3 “Operating Modes
selected by Device Control Register Bits 1 and 2”).
The PWM_SEL bit determines whether the SMBus or
PWMI input should drive the output brightness in terms
of PWM dimming. When PWM_SEL bit is 1, the PWMI
drives the output brightness regardless of what the
PWM_MD is.
• An SMBus Read Byte cycle to Register 0x00 returns
the programmed PWM brightness level, regardless of
the value of PWM_SEL.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted;
when this bit is 1, the PWM dimming is based on the
SMBus brightness setting. When this bit is 0, the PWM
dimming reflects a percentage change in the current
brightness programmed in the SMBus Register 0x00, i.e.
DPST (Display Power Saving Technology) mode, as
shown in Equation 6:
• An SMBus setting of 0xFF for Register 0x00 sets the
backlight controller to the maximum brightness.
• An SMBus setting of 0x00 for Register 0x00 sets the
backlight controller to the minimum brightness
output in which the LED current is guaranteed to be
less than 10µA.
• Default value for Register 0x00 is 0xFF.
(EQ. 6)
DPST Brightness = Cbt PWMI
Device Control Register (0x01)
Where:
This register has 2 bits that control the operating mode
of the backlight controller and a single bit that controls
the BL ON/OFF state. The remaining bits are reserved.
The bit assignment is shown in Tables 2A and 2B. All
other bits in the Device Control Register will read as low
Cbt = Current brightness setting from SMBus Register
0x00 without influence from the PWMI
PWMI = is the percent duty cycle of the PWMI
FN6996 Rev.2.00
Sep 13, 2017
Page 19 of 24
ISL97677
For example, the Cbt = 50% duty cycle programmed in
the SMBus Register 0x00 and the PWM frequency is
tuned to be 200Hz with an appropriate capacitor at the
FPWM pin. On the other hand, PWMI is fed with a 1kHz
30% high PWM signal. When PWM_SEL = 0 and
PWM_MD = 0, the device is in DPST operation where
DPST brightness = 15% PWM dimming at 200Hz.
read-only, with the exception of bit 0, which can be
cleared by writing to it.
• A Read Byte cycle to Register 0x02 indicates the
current BL on/off status in BL_STAT (1 if the BL is on,
0 if the BL is off).
• A Read Byte cycles to Register 0x2 also returns
FAULT as the logical OR of THRM_SHDN, OV_CURR,
2_CH_SD, and 1_CH_SD should these events occur.
• All reserved bits return a “0” when read.
• All reserved bits have no functional effect when
written.
• 1_CH_SD returns a 1 if one or more channels have
faulted out.
• All defined control bits return their current, latched
value when read.
• 2_CH_SD returns a 1 if two or more channels have
faulted out.
• A value of 1 written to BL_CTL turns on the BL in 4ms
or less after the write cycle completes. The BL is
deemed to be on when Bit 3 BL_STAT of Register 0x02
is 1 and Register 0x09 is not 0. See Tables 2A and 2B.
• A fault will not be reported in the event that the BL is
commanded on and then immediately off by the
system.
• When FAULT is set to 1, it will remain at 1 even if the
signal which sets it goes away. FAULT will be cleared
when the BL_CTL bit of the Device Control Register is
toggled or when written low. At that time, if the fault
condition is still present or reoccurs, FAULT will be
set to 1 again. BL_STAT will not cause FAULT to be
set.
• A value of 0 written to BL_CTL immediately turns off the
BL. The BL is deemed to be off when Bit 3 BL_STAT of
Register 0x02 is 0 and Register 0x09 is 0. See Tables 2A
and 2B.
• **Note that the behavior of Register 0x00
(Brightness Control Register) is affected by certain
combinations of the control bits, as shown in Table 3
“Operating Modes Selected by Device Control
Register Bits 1 and 2.”
• The controller will not indicate a fault if the VBL+
goes away, whether or not the LEDs were on at the
time of the power loss. This can occur if there is
some hang condition that causes the user to force
the system off by holding the power button down
for 4s.
• When an SMBus mode is selected, Register 0x00
reflects the last value written to it. But, when any
non-SMBus mode is selected, Register 0x00 reflects
the current brightness value based on the current
mode of operation, with the exception of SMBus
mode with DPST, where PWM_MD = 0 and
PWM_SEL = 0.
• The default value for Register 0x02 is 0x00.
Identification Register (0x03)
The ID register contains 3-bit fields to denote the LED
driver (always set to 1), manufacturer and the silicon
revision of the controller IC. The bit field widths allow up
to 16 vendors with up to 8 silicon revisions each. In order
to keep the number of silicon revisions low, the revision
field will not be updated unless the part will make it out
to the user’s factory. Thus, if during the engineering
development process, 3 silicon spins were needed, the
next available revision ID would be used for all 3 spins
until that same ID made it to the factory. Except Bit 7,
which has to be 1, all of the bits in this register are
read-only.
• When SMBus mode with DPST is selected, Register
0x00 reflects the last value written to it from SMBus.
• When a write to Register 0x01 (Device Control
Register) causes the backlight controller to transition
to an SMBus mode, the brightness of the BL does not
change. On the other hand, when a write to Register
0x01causes the backlight controller to transition to a
non-SMBus mode, the brightness of the BL changes
as appropriate for the new mode.
• The default value for Register 0x01 is 0x00.
• Vendor ID 9 represents Intersil Corporation.
• The default value for Register 0x03 is 0xC8.
Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of
the backlight controller’s operating state. Bit 0 is a logical
“OR” of all fault codes to simplify error detection. Not all
of the bits in this register are fault related (Bit 3 is a
simple BL status indicator). The remaining bits are
reserved and return a “0” when read and ignore the bit
value when written. All of the bits in this register are
The initial value of REV shall be 0. Subsequent values of
REV will increment by 1.
Components Selections
According to the inductor Voltage-Second Balance
principle, the change of inductor current during the
switching regulator On-time is equal to the change of
inductor current during the switching regulator Off-time.
FN6996 Rev.2.00
Sep 13, 2017
Page 20 of 24
ISL97677
Because the voltage across an inductor is as shown in
Equation 7:
It is recommended that an input capacitor of at least
10µF be used. Ensure the voltage rating of the input
capacitor is suitable to handle the full supply range.
(EQ. 7)
V
= L I t
L
L
Inductor
and I @ On = I @ Off, therefore:
The selection of the inductor should be based on its
L
L
maximum and saturation current (I
) characteristics,
SAT
(EQ. 8)
V – 0 L D t = V – V – V L 1 – D t
S
I
S
O
D
I
power dissipation (DCR), EMI susceptibility (shielded vs
unshielded), and size. Inductor type and value influence
many key parameters, including ripple current, current
limit, efficiency, transient performance and stability.
where D is the switching duty cycle defined by the
turn-on time over the switching periods. V is Schottky
D
diode forward voltage that can be neglected for
approximation.
The inductor’s maximum current capability must be
adequate enough to handle the peak current at the worst
case condition. Additionally if an inductor core is chosen
with too low a current rating, saturation in the core will
cause the effective inductor value to fall, leading to an
increase in peak to average current level, poor efficiency
and overheating in the core. The series resistance, DCR,
within the inductor causes conduction loss and heat
dissipation. A shielded inductor is usually more suitable
for EMI susceptible applications, such as LED
Rearranging the terms without accounting for V gives
D
the boost ratio and duty cycle respectively as Equations 9
and 10:
(EQ. 9)
V
V = 1 1 – D
I
O
(EQ. 10)
D = V – V V
O
O
I
Input Capacitor
Switching regulators require input capacitors to deliver
peak charging current and to reduce the impedance of
the input supply. This reduces interaction between the
regulator and input supply, thereby improving system
stability. The high switching frequency of the loop causes
almost all ripple current to flow in the input capacitor,
which must be rated accordingly.
backlighting.
The peak current can be derived from the voltage across
the inductor during the Off-period, as expressed in
Equation 11:
IL
= V I 85% V + 1 2V V – V L V f
peak
O
O
I
I
O
I
O
SW
(EQ. 11)
A capacitor with low internal series resistance should be
chosen to minimize heating effects and improve system
efficiency, such as X5R or X7R ceramic capacitors, which
offer small size and a lower value of temperature and
voltage coefficient compared to other ceramic capacitors.
The choice of 85% is just an average term for the
efficiency approximation. The first term is the average
current, which is inversely proportional to the input
voltage. The second term is the inductor current change,
which is inversely proportional to L and f . As a result,
SW
for a given switching.
PWM BRIGHTNESS CONTROL
REGISTER 0x00
REGISTER
BRT7
BRT6
BRT5
BRT4
BRT3
BRT2
BRT1
BRT0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
= 256 steps of PWM brightness levels
BRT[7..0]
FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
FN6996 Rev.2.00
Sep 13, 2017
Page 21 of 24
ISL97677
REGISTER 0x01
DEVICE CONTROL REGISTER
RESERVED RESERVED RESERVED RESERVED RESERVED PWM_MD PWM_SEL
BL_CTL
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
PWM_MD
= PWM mode select bit (1 = absolute
brightness, 0 = % change) default = 0
PWM_SEL
BL_CTL
= Brightness control select bit (1 = control
by PWMI, 0 = control by SMBus) default = 0
= BL On/Off (1 = On, 0 = Off) default = 0
FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
REGISTER 0x02
FAULT/STATUS REGISTER
RESERVED RESERVED 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN
Bit 7 (R) Bit 6 (R) Bit 5 (R) Bit 4 (R) Bit 3 (R) Bit 2 (R) Bit 1 (R)
FAULT
Bit 0 (R)
BIT
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BIT ASSIGNMENT
2_CH_SD
BIT FIELD DEFINITIONS
= Two LED output channels are shutdown (1 = shutdown, 0 = OK)
= One LED output channel is shutdown (1 = shutdown, 0 = OK)
= BL Status (1 = BL On, 0 = BL Off)
1_CH_SD
BL_STAT
OV_CURR
= Input Overcurrent (1 = Overcurrent condition, 0 = Current OK)
= Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK)
= Fault occurred (Logic “OR” of all of the fault conditions)
THRM_SHDN
FAULT
FIGURE 32. DESCRIPTIONS OF FAULT/STATUS REGISTER
ID REGISTER
REGISTER 0x03
LED
PANEL
MFG3
MFG2
MFG1
MFG0
REV2
REV1
REV0
Bit 7 = 1
Bit 6 (R)
Bit 5 (R)
Bit 4 (R)
Bit 3 (R)
Bit 2 (R)
Bit 1 (R)
Bit 0 (R)
BIT ASSIGNMENT
BIT FIELD DEFINITIONS
= Manufacturer ID. See “Identification
Register (0x03)” on page 20.
MFG[3..0]
Data 0 to 8 in decimal correspond to other
vendors data 9 in decimal represents Intersil
ID data 10 to 14 in decimal are reserved
data 15 in decimal Manufacturer ID is not
implemented
REV[2..0]
= Silicon rev (Rev 0 through Rev 7 allowed
for silicon spins)
FIGURE 33. DESCRIPTIONS OF ID REGISTER
FN6996 Rev.2.00
Sep 13, 2017
Page 22 of 24
ISL97677
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit
our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
09/13/17
FN6996.2
Added VHEADROOM_RANGE spec to the Electrical Specifications table.
Added Note 10.
In “Current Matching and Current Accuracy” on page 12, updated the second sentence in the
second paragraph for clarification.
Applied new header/footer.
Added Related Literature section.
Replaced Products section with About Intersil section.
Updated the POD to revision 3.
Changes since the last revision:
-Changed Note 4 from “Dimension b applies...” to “Dimension applies..”
-Added triangles around Notes 4, 5, and 6
11/13/09
FN6996.1
Changed in OVP and VOUT Requirement
Changed from:
VOUT can only regulate between 61% and 100% of the VOUT_OVP such that:
To:
VOUT can only regulate between 64% and 100% of the VOUT_OVP such that
From:
Allowable VOUT = 61% to 100% of VOUT_OVP
To:
Allowable VOUT = 64% to 100% of VOUT_OVP
From:
...then the VOUT is allowed to operate between 24.4V and 40V.
To:
...then the VOUT is allowed to operate between 25.6V and 40V.
From:
...should follow VOUT = (61% ~100%)OVP requirement
To:
...should follow VOUT = (64% ~100%)OVP requirement.
Changed VSC spec from “2.5Vmin, 3.4Vmax, 3.3min, 4.4max, 4.2min, 5.4max to “2.4Vmin,
3.6Vmax, 3.3min, 4.6max, 4.2min, 5.6max”.
10/21/09
FN6996.0
Initial release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's
products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end
consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product
information page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2009-2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6996 Rev.2.00
Sep 13, 2017
Page 23 of 24
ISL97677
Package Outline Drawing
For the most recent package outline drawing, see L32.5x5B.
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 5/10
4X
3.5
0.50
5.00
28X
A
6
B
PIN #1 INDEX AREA
32
25
6
1
24
PIN 1
INDEX AREA
3 .30 ± 0 . 15
17
8
(4X)
0.15
9
16
0.10 M
C
A B
0.07
+
32X 0.40 ± 0.10
4
32X 0.23
- 0.05
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10
C
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08
C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 30 )
(32X 0 . 23 )
( 32X 0 . 60)
5
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6996 Rev.2.00
Sep 13, 2017
Page 24 of 24
相关型号：
ISL976787IBZ
LED DISPLAY DRIVER, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AE, SOIC-28
RENESAS
ISL976787IBZ-T
LED DISPLAY DRIVER, PDSO28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AE, SOIC-28
RENESAS
©2020 ICPDF网 联系我们和版权申明