ISL97678 [INTERSIL]
8-Channel 45V 50mA LED Driver; 8通道45V 50毫安LED驱动器
| 型号： | ISL97678 |
| 厂家： | 
Intersil |
| 描述： | 8-Channel 45V 50mA LED Driver |
| 文件： | 总18页 (文件大小：922K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel 45V 50mA LED Driver
ISL97678
Features
• 8 Channels
The ISL97678 is an 8-channel PWM dimming LED driver
for LCD backlight applications. The ISL97678 is capable
of driving up to 96 pieces of 3.4V/50mA LEDs but larger
numbers of LEDs is possible if the LED forward voltage
combined is less than 45V. The ISL97678 has 8 channels
of voltage controlled current sources with typical currents
matching to ±1%, which compensate for the
non-uniformity effect of forward voltages variance in the
LED strings. To minimize the voltage headroom and
power loss in the typical multi-string operation, the
ISL97678 features dynamic headroom control that
monitors the highest LED forward voltage string and uses
its feedback signal for output regulation.
• 4.75V ~ 26V Input
• 45V Maximum Output
• Drive Typically 96 LEDs (3.4V/50mA each)
• External PWM Input up to 25kHz Dimming
• Dimming range 0.8%~100% up to 30kHz
• Current Matching ±0.7%
• Protections
- String Open Circuit and Short Circuit Detections,
OVP, and OTP
• Adjustable Dimming Frequency
• Adjustable Switching Frequency
• 32 Ld (5mmx5mm) QFN Package
The ISL97678 features PWM dimming up to 30kHz with
0.8%~100% duty cycle and maintains ±1% current
matching across all ranges. The PWM dimming frequency
can be adjusted between 100Hz and 30kHz. The boost
switching frequency can also be adjusted between
600kHz and 1.5MHz.
Applications
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
The ISL97678 features extensive protection functions
that include string open and short circuit detections, OVP,
and OTP.
ISL97678 is available in the 32 Leads QFN 5mmx5mm
and operate from -40°C to +85°C with input voltage
ranges from 4.75V to 26V.
November 5, 2009
FN6998.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL97678
Typical Application Circuit
8x12 = 96 LEDs
Output 45V*, 50mA per string max
L1
D1
VIN* = 4.75V~26V
Ci
10uH/3A
Co
3x4.7uF
ISL97678
10uF
LX1 20
VIN
16
18
10
LX2 21
806kΩ
VDC
1uF
100pF
3.3nF
OVP
23
VLOGIC
22kΩ
1uF
4
PWM
EN
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
25
26
27
17
14
COMP
RSET
FSW
3.3nF
15kΩ
13
11
12
14.2kΩ
28
29
30
31
50kΩ
FPWM
333kΩ
AGND
AGND
2
3
32
6
7
8
AGND
PGND
1
AGND
AGND
* Vin > = 12V for 45V/50mA
Applications
PGND 19
PGND 22
AGND
AGND
9
5
15 AGND
FIGURE 1. ISL97678 TYPICAL APPLICATION DIAGRAM
FN6998.1
November 5, 2009
2
ISL97678
Block Diagram
45V*, 50mA per string
96 (8x12) LEDs
VIN* = 4.75V~26V
10uH/3A
EN
2x4.7uF/50V
VIN
LX
VDC
Analog Bias
Logic Bias
REG1
O/P Short
VLOGIC
OVP
REG2
OVP
Fault
Boost SW
fsw
OSC &
RAMP
fSW
Comp
FET
Drivers
Σ=0
Logic
Imax
ILIMIT
PGND
pe
Open Ckt, Short Ckt
Detects
Fault Control
COMP
GM
AMP
CH1
CH2
Highest VF
String Detect
CH8
Temp
1
VSET
+
-
Sensor
+
-
REF
GEN
RSET
AGND
Fault
Control
REF_OVP
REF_VSC
2
+
-
* Vin >=12V for 45V/50mA apps
PWM
fPWM
PWM
Dimming
Controller
+
-
8
ISL97678
FIGURE 2. ISL97678 BLOCK DIAGRAM
Ordering Information
PACKAGE
(Pb-free)
PKG.
DWG. #
PART NUMBER
PART MARKING
ISL9767 8IRZ
ISL97678IRZ (Notes 1, 2)
NOTES:
32 Ld 5x5 QFN
L32.5x5B
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97678. For more information on MSL please
see techbrief TB363.
FN6998.1
November 5, 2009
3
ISL97678
Pin Configuration
ISL97678
(32 LD 5X5 QFN)
TOP VIEW
32 31 30 29 28 27 26 25
PGND
AGND
AGND
PWM
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OVP
PGND
LX
EXPOSED THERMAL PAD
AGND
AGND
AGND
AGND
LX
PGND
VDC
EN
9
10 11
12 13 14 15 16
Pin Descriptions (I = Input, O = Output, S = Supply)
PIN
NAME
PGND
AGND
TYPE
DESCRIPTION
1, 19, 22
S
S
Power Ground
Analog Ground
2, 3, 5, 6, 7,
8, 9, 15
4
PWM
VLOGIC
FSW
I
O
I
PWM Brightness Control
10
11
Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation
When R
When R
is 100kΩ, f
is 33kΩ, f
SW
is 500kHz.
is 1.5MHz
FSW
FSW
SW
12
FPWM
I
When R
When R
is 333kΩ, FPWM is 200Hz.
is 3.3kΩ, FPWM is 20kHz.
FPWM
FPWM
13
14
RSET
COMP
VIN
I
O
S
I
Resistor Connection for Setting LED Current
Boost compensation
16
Main Power
17
EN
Enable
18
VDC
S
O
I
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation
Boost MOSFET Drain Terminal Switching Node
Overvoltage Protection Input as well as Output Voltage FB Monitoring
No Connect
20, 21
23
LX
OVP
24
NC
I/O
I
25 ~ 32
CH1 ~ CH8
LED Driver PWM Dimming Monitoring
FN6998.1
November 5, 2009
4
ISL97678
Absolute Maximum Ratings
Thermal Information
Voltage ratings are all with respect to AGND pin
Thermal Resistance (Typical)
θ
(°C/W)
θ
(°C/W)
3
JA
JC
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
VLOGIC. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
VDC, PWM. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . -0.3V to min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . (VDC + 0.3V, 5.75V)
CH1 - CH8, LX, OVP . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
32 Ld QFN (Notes 4, 5) . . . . . . . . .31
Thermal Characterization (Typical, Note 6)
PSI (°C/W)
JT
32 Ld QFN. . . . . . . . . . . . . . . . . . . . . . . . .
0.2
Maximum Continuous Junction Temperature . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Power Dissipation
T < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W
A
T < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W
A
T < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
A
Recommended Operating Conditions
T < +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
A
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. PSI is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with
JT
this rating then the die junction temperature can be estimated more accurately than the θ and θ thermal resistance
JC JC
ratings.
5.
Electrical Specifications All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V,
A
IN
I
= 36kΩ, unless otherwise noted. Boldface limits apply over the operating
SET
temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
GENERAL
DESCRIPTION
CONDITION
(Note 7) TYP (Note 7) UNIT
V
Backlight Supply Voltage
4.75
26
(Note 8)
V
IN
I
VIN Shutdown Current
/SHUT = 0
5
µA
V
VIN_SHDN
V
V
V
Output Voltage
45
3.3
OUT
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
2.9
4.8
2.3
V
UVLO
300
mV
UVLO_HYS
LINEAR REGULATOR
V
V
5V Analog Bias Regulator
VDC LDO Dropout Voltage
Active Current
V
> 6V
5
5.1
V
DC
IN
I
= 30mA
71
10
2.4
31
100
mV
mA
V
DC_DROP
VDC
VDC
I
/SHUT = 5V, R = 33kΩ
> 6V
V
V
2.5V Logic Bias Regulator
VLOGIC LDO Dropout Voltage
V
2.5
LOGIC
IN
I
= 30mA
100
mV
LOGIC_DROP
VLOGIC
BOOST SWITCHING REGULATOR
SS
Soft-Start
16
ms
A
SW
Boost FET Current Limit
Internal Boost Switch ON-Resistance
T = +25°C to +85°C
3.0
4.7
ILimit
A
r
130
mΩ
DS(ON)
FN6998.1
November 5, 2009
5
ISL97678
Electrical Specifications All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V,
A
IN
I
= 36kΩ, unless otherwise noted. Boldface limits apply over the operating
SET
temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Eff_peak
DESCRIPTION
Peak Efficiency
CONDITION
(Note 7) TYP (Note 7) UNIT
V
= 24V, 96LEDs,
20mA each, L = 10µH
with DCR ≤100mΩ,
92.4
91.5
81.6
93.4
90.7
%
%
%
%
%
IN
F
= 600kHz,
SW
T = +25°C
A
V
= 12V, 96 LEDs,
20mA each, L = 10µH
with DCR ≤100mΩ,
IN
F
= 600kHz,
SW
T = +25°C
A
V
= 6V, 96 LEDs,
20mA each, L = 10µH
with DCR ≤100mΩ,
IN
F
= 600kHz,
SW
T = +25°C
A
V
= 24V, 80 LEDs,
40mA each, L = 10µH
with DCR ≤100mΩ,
=600kHz,
T = +25°C
IN
F
SW
A
V
= 12V, 80 LEDs,
40mA each, L = 10µH
IN
with DCR ≤100mΩ,
F
= 600kHz,
SW
T = +25°C
A
D
D
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
Boost Switching Frequency
f
f
= 500kHz
= 500kHz
= 100kΩ
= 33kΩ
90
%
%
MAX
MIN
SW
10
0.55
1.65
10
SW
f
R
R
0.45
1.35
0.5
1.5
MHz
MHz
µA
SW
fsw
fsw
ILX_leakage
Lx Leakage Current
VLX = 45V, /SHUT = 0V
REFERENCE
I
I
Channel-to-Channel Current Matching
Absolute Current Accuracy
I
I
= 20mA
-1.1
±0.7
+1.1
%
%
MATCH
ACC
LED
= 36kΩ,
-1.5
+1.5
RSET
T = +25°C
A
I
= 36kΩ,
-2
+2
%
RSET
T = -40°C to +80°C
A
FAULT DETECTION
V
V
V
V
Channel Short Circuit Threshold
Over-Temperature Threshold
3.3
4.6
V
°C
°C
V
SC
150
5
temp
temp_acc
OVP
Over-Temperature Threshold Accuracy
Overvoltage Limit on OVP Pin
1.18
1.5
1.22
1.24
DIGITAL INTERFACE
V
V
Logic Input Low Voltage
Logic Input High Voltage
0.8
5.5
V
V
IL
IH
CURRENT SOURCES
V
Dominant Channel Current Source
Headroom at CH Pin
I
= 50mA
1.0
V
HEADROOM
LED
T = +25°C
A
FN6998.1
November 5, 2009
6
ISL97678
Electrical Specifications All specifications below are characterized at T = -40°C to +85°C; V = 12V, /SHUT = 5V,
A
IN
I
= 36kΩ, unless otherwise noted. Boldface limits apply over the operating
SET
temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
Voltage at ISET Pin
CONDITION
(Note 7) TYP (Note 7) UNIT
V
1.18
1.21
50
1.24
V
ISET
ILEDmax
Maximum LED Current per Channel
LED config = 8P10S
with VF = 3.4V and
mA
V
= 11V
IN
PWM GENERATOR
FPWM
Generated PWM Frequency
R
R
= 330kΩ
= 3.3kΩ
180
18
200
20
220
22
Hz
kHz
%
FPWM
FPWM
Dimming Range
PWM Dimming Duty Cycle Limits (Note 9)
f
≤ 30kHz
= 33kΩ
0.4
100
1.24
20k
PWM
VFSW
FPWMI
VFPWM
NOTES:
f
Voltage
R
R
1.18
200
1.18
1.21
1.21
V
SW
FSW
PWMI Input Frequency Range (Note 9)
VFPWM Voltage
Hz
V
= 3.3kΩ
1.25
FPWM
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
8. At maximum V of 26V, minimum V
IN OUT
is 28V. Minimum V can be lower at lower V
OUT IN
9. Limits established by characterization and are not production tested.
Typical Performance Curves
100
95
90
85
80
75
70
100
20mA
8P11S
SW
50mA
8P11S
SW
-40°C
f
= 600kHz
95
90
85
80
75
70
f
= 600kHz
0°C
0°C
-40°C
+85°C
+85°C
+25°C
+25°C
10
0
5
10
15
(V)
20
25
30
0
5
15
(V)
20
25
30
V
V
IN
IN
FIGURE 3. EFFICIENCY vs V
50mA
vs TEMPERATURE AT
FIGURE 4. EFFICIENCY vs V
20mA
vs TEMPERATURE AT
IN
IN
FN6998.1
November 5, 2009
7
ISL97678
Typical Performance Curves(Continued)
95
94
93
92
91
90
89
88
87
86
85
84
100
50mA
8P11S
8P10S
95
90
85
80
75
70
65
60
55
50
45
40
35
30
12V/50mA
24V
24V/50mA
12V
1k
0
10
20
I
30
(mA)
40
50
400
600
800
1.2k
1.4k
1.6k
SWITCHING FREQUENCY (Hz)
LED
FIGURE 6. EFFICIENCY vs SWITCHING FREQUENCY
FIGURE 5. EFFICIENCY vs I
LED
1.0
1.0
0.8
20mA - 8P12S
50mA - 8P11S
50mA
0.8
8P11
0.6
0°C
0.4
0.6
12V/20mA
0.4
0.2
0.2
0.0
0.0
+25°C
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
+85°C
-0.4
-0.6
12V/50mA
-0.8
-1.0
-40°C
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
V
(V)
CHANNEL
IN
FIGURE 8. CURRENT MATCHING vs V
TEMPERATURE
vs
FIGURE 7. CHANNEL-TO-CHANNEL CURRENT
MATCHING EXAMPLE
IN
2.0
2.0
20mA - 8P12S
50mA - 8P11S
20mA - 8P12S
50mA - 8P11S
1.8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
12V/50mA
1.6
12V/50mA
1.4
24V/50mA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5V/20mA
12V/20mA
HEADROOM CONTROL CHANNEL
24V/20mA
1
2
3
4
5
6
7
8
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
PWM DIMMING DUTY CYCLE (%)
CHANNEL
FIGURE 9. CURRENT LINEARITY vs LOW LEVEL PWM
DIMMING DUTY CYCLE
FIGURE 10. TYPICAL CHANNEL VOLTAGE EXAMPLE
FN6998.1
November 5, 2009
8
ISL97678
Typical Performance Curves(Continued)
1.00
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
20mA
8P11S
50mA
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
8P11S
+25°C
+85°C
+85°C
+25°C
0°C
20
0°C
0
5
10
15
(V)
20
25
30
0
5
10
15
IN
25
30
V
V
(V)
IN
IN
FIGURE 12. V
vs V
vs TEMPERATURE AT
FIGURE 11. V
vs V
vs TEMPERATURE AT
IN
HEADROOM
20mA
HEADROOM
50mA
10
9
8
7
6
5
4
3
2
1
0
/SHUT = HIGH
PWM DUTY CYCLE = 0%
LX (20V/DIV)
+85°C
V
(100mV/DIV)
O
-40°C
I
(20mA/DIV)
LED
0
5
10
15
VIN (V)
20
25
vs
30
FIGURE 14. V
RIPPLE VOLTAGE
FIGURE 13. QUIESCENT CURRENT vs V
IN
OUT
TEMPERATURE WITH /SHUT ENABLE
V
(20V/DIV)
V
(20V/DIV)
O
O
EN (5V/DIV)
EN (5V/DIV)
I
(1A/DIV)
IN
I
(1A/DIV)
IN
I
(50mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 15. IN-RUSH CURRENT and LED CURRENT AT
= 12V
FIGURE 16. IN-RUSH CURRENT AND LED CURRENT
AT V = 26V
V
IN
IN
FN6998.1
November 5, 2009
9
ISL97678
Typical Performance Curves(Continued)
V
(10V/DIV)
IN
V
(10V/DIV)
IN
I
(500mA/DIV)
IN
I
(500mA/DIV)
IN
I
(50mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 18. LINE REGULATION WITH V
FROM 26V TO 12V
CHANGES
FIGURE 17. LINE REGULATION WITH V
CHANGES
FROM 12V TO 26V DISABLE PROFILE
IN
IN
V
(1V/DIV)
O
V
(1V/DIV)
O
I
(20mA/DIV)
LED
I
(20mA/DIV)
LED
FIGURE 19. LOAD REGULATION WITH I
CHANGES
FIGURE 20. LOAD REGULATION WITH I
CHANGES
LED
FROM 0.4% TO 100% PWM DIMMING
LED
FROM 100% TO 0.4% PWM DIMMING
V
(1V/DIV)
V
(500mV/DIV)
O
O
I
(20mA/DIV)
LED
I
(20mA/DIV)
LED
FIGURE 22. LOAD REGULATION WITH I
CHANGES
FIGURE 21. LOAD REGULATION WITH I
CHANGES
LED
FROM 100% to 0% PWM DIMMING
LED
FROM 0% TO 100% PWM DIMMING
FN6998.1
November 5, 2009
10
ISL97678
Typical Performance Curves(Continued)
V
(20V/DIV)
O
EN (5V/DIV)
I
(1A/DIV)
IN
I
(50mA/DIV)
LED
FIGURE 23. DISABLE PROFILE
.
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the
minimal voltage needed to enable the LED string with the
highest forward voltage drop to run at the programmed
current. The ISL97678 employs current mode control
boost architecture that has a fast current sense loop and
a slow voltage feedback loop. Such architecture achieves
a fast transient response that is essential for the
notebook backlight application where the power can be
several Li-ion cell batteries or instantly change to an
AC/DC adapter without rendering a noticeable visual
nuisance. The number of LEDs that can be driven by
ISL97678 depends on the type of LED chosen in the
application. The ISL97678 is capable of boosting up to
45V and drive 8 channels of LEDs at maximum of 45mA
per channel.
+
-
+
REF
-
RSET
+
-
PWM DIMMING
FIGURE 24. SIMPLIFIED CURRENT SOURCE CIRCUIT
Current Matching and Current Accuracy
Dynamic Headroom Control
Each channel of the LED current is regulated by the
current source circuit, as shown in Figure 24.
The ISL97678 features a proprietary Dynamic Headroom
Control circuit that detects the highest forward voltage
string or effectively the lowest voltage from any of the
The LED peak current is set by translating the R
current to the output with a scaling factor of 707.9/R
SET
.
SET
CH pins. When this lowest I voltage is lower than the
IN
The source terminals of the current source MOSFETs are
designed to run at 500mV to optimize power loss versus
accuracy requirements. The sources of errors of the
channel-to-channel current matching come from the
op amps offset, internal layout, reference, and current
source resistors. These parameters are optimized for
current matching and absolute current accuracy.
However, the absolute accuracy is additionally
short circuit threshold, V , such voltage will be used as
SC
the feedback signal for the boost regulator. The boost
makes the output to the correct level such that the
lowest CH pin is at the target headroom voltage. Since all
LED strings are connected to the same output voltage,
the other CH pins will have a higher voltage, but the
regulated current source circuit on each channel will
ensure that each channel has the same programmed
current. The output voltage will regulate cycle-by-cycle
and is always referenced to the highest forward voltage
string in the architecture.
determined by the external R
resistor is recommended.
. A 0.1% tolerance
SET
FN6998.1
November 5, 2009
11
ISL97678
OVP and V
Requirement
PWM Dimming Frequency Adjustment
OUT
The dimming frequencies are set by an external
resistor at the FPWM pin as shown by Equation 3:
The Overvoltage Protection (OVP) pin has a function of
setting the overvoltage trip level as well as limiting the
7
V
regulation range.
6.66×10
RPWM
OUT
-----------------------
=
(EQ. 3)
f
PWM
The ISL97678 OVP threshold is set by R
and
UPPER
R
as shown in Equation 1:
LOWER
where f
and R
is the desirable PWM dimming frequency
PWM
is the setting resistor.
V
= 1.21V × (R
+ R
) ⁄ R
LOWER LOWER
(EQ. 1)
FPWM
OUT_OVP
UPPER
Switching Frequency
The boost switching frequency can be adjusted by a
resistor as shown in Equation 4:
V
V
can only regulate between 64% and 100% of the
OUT
_
such that:
OUT OVP
Allowable V
OUT
= 64% to 100% of V
_
OUT OVP
10
(5×10
R
)
-----------------------
(EQ. 4)
f
=
SW
For example, if 10 LEDs are used with the worst case
of 35V. If R and R are chosen such that the OVP
OSC
V
OUT
1
2
level is set at 40V, then the V
is allowed to operate
OUT
between 25.6V and 40V. If the requirement is changed to
a 6 LEDs 21V V application, then the OVP level must
where f
and R
OSC
is the desirable boost switching frequency
is the setting resistor.
SW
OUT
be reduced and users should follow V
5V and 2.3V Low Dropout Regulators
= (64%
OUT
~100%)OVP requirement. Otherwise, the headroom
control will be disturbed such that the channel voltage
can be much higher than expected and sometimes it can
prevents the driver from operating properly.
A 5V LDO regulator is present at the VDC pin to develop
the necessary low voltage supply, which is used by the
chips internal control circuitry. Because VDC is an LDO
pin, it requires a bypass capacitor of 1µF or more for the
regulation. The VDC pin can be used for a coarse
regulator or reference but do not pull more than few mA
from it.
The ratio of the OVP capacitors should be the inverse of
the OVP resistors. For example, if R
/R =
UPPER LOWER
33/1, then C
and C
/C
= 3.3nF.
=1/33 with C = 100pF
UPPER LOWER
UPPER
LOWER
Similarly, a 2.3V LDO regulator is present at the
VLOGIC pin to develop the necessary low voltage supply
for the chip’s internal logic control circuitry. A 1µF
bypass capacitor or more is needed for regulation. The
VLOGIC pin can be used as a coarse regulator or
reference but do not pull more than few mA from it.
Dimming Controls
The ISL97678 allows two ways of controlling the LED
current, and therefore, the brightness. They are:
1. DC current adjustment
Soft-Start
2. PWM chopping of the LED current defined in Step 1.
The ISL97678 uses a digital soft-start where the boost
current limit is stepped up in 8 steps. The initial current
limit level is set to one ninth of the full current limit, with
subsequent steps increasing this by a ninth every 2ms.
In the event that no LEDs have been conducting during
the interval since the last step (for example if the LEDs
are running at low duty cycle at low PWM frequency)
then the step will be delayed until the LEDs are
conducting. If the LEDs are disabled and re-enabled
again then soft start will be restarted when the LEDs are
enabled.
There are various ways to achieve DC or PWM current
control, which will be described in the following.
In any dimming controls, the EN pin must be high. EN
is a high voltage pin that can be applied with a digital
signal or tied directly to V for enable function.
IN
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an
appropriate value for R
. This should be chosen to fix
SET
the maximum possible LED current:
707.9
Fault Protection and Monitoring
--------------
I
=
LEDmax
(EQ. 2)
R
SET
The ISL97678 features extensive protection functions to
cover all the perceivable failure conditions. The failure
mode of a LED can be either open circuit or as a short.
The behavior of an open circuited LED can additionally
take the form of either infinite resistance or, for some
LEDs, a zener diode, which is integrated into the device
in parallel with the now opened LED.
Alternatively, the R
SET
potentiometer for adjustable current.
can be replaced by a digital
PWM CONTROL
The ISL97678 provides PWM dimming by PWM chopping
of the current in the LEDs for all 8 channels. To achieve
PWM dimming, the users need to apply a PWM signal at
the PWM pin. The PWM output will follow the PWM input
For basic LEDs (which do not have built-in zener diodes),
an open circuit failure of an LED will only result in the loss
of one channel of LEDs without affecting other channels.
Similarly, a short circuit condition on a channel that
and the dimming frequency will be set by R
. During
PWM
the On periods, the LED current will be defined by the
value of R , as described in Equation 1.
SET
FN6998.1
November 5, 2009
12
ISL97678
results in that channel being turned off does not affect
other channels unless a similar fault is occurring.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage
and keeps the voltage at a safe level. The OVP threshold
is set as shown in Equation 5:
Due to the lag in boost response to any load change at its
output, certain transient events (such as significant step
changes in LED duty cycle) can transiently look like LED
fault modes. The ISL97678 uses feedback from the LEDs
to determine when it is in a stable operating region and
prevents apparent faults during these transient events
from allowing any of the LED strings to fault out. See
Table 1 for more details.
OVP = 1.21V × (R
+ R
) ⁄ R
LOWER LOWER
(EQ. 5)
UPPER
These resistors should be large to minimize the power
loss. For example, a 1MkΩ R and 30kΩ R
UPPER LOWER
sets OVP to 41.2V. Large OVP resistors also allow C
OUT
discharges slowly during the PWM Off time. Parallel
capacitors should be placed across the OVP resistors
such that R /R = C /C . Using a
Short Circuit Protection (SCP)
UPPER LOWER LOWER UPPER
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels which are detected
above the programmed short circuit threshold. When an LED
becomes shorted, the action taken is described in Table 1. The
short circuit threshold is 4V.
C
value of at least 30pF is recommended. These
UPPER
capacitors reduce the AC impedance of the OVP node,
which is important when using high value resistors.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the
device will stop switching and be reset. Operation will
restart only if the device control interface re-enables it
once the input voltage is back in the normal operating
range. Also all digital settings will be reset to their default
states.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can
behave as either an infinite resistance or a gradually
increasing finite resistance. The ISL97678 monitors the
current in each channel such that any string which
reaches the intended output current is considered
“good”. Should the current subsequently fall below the
target, the channel will be considered an “open circuit”.
Furthermore, should the boost output of the ISL97678
reach the OVP limit or should the lower over-temperature
threshold be reached, all channels which are not “good”
will immediately be considered as “open circuit”.
Detection of an “open circuit” channel will result in a
time-out before disabling of the affected channel.
Over-Temperature Protection (OTP)
The ISL97678 includes two over-temperature thresholds.
The lower threshold is set to +130°C. When this
threshold is reached, any channel which is outputting
current at a level significantly below the regulation target
will be treated as “open circuit” and disabled after a
time-out period. The intention of the lower threshold is to
allow bad channels to be isolated and disabled before
they cause enough power dissipation (as a result of other
channels having large voltages across them) to hit the
upper temperature threshold.
Some users employ some special types of LEDs that
have zener diode structure in parallel with the LED for
ESD enhancement, thus enabling open circuit operation.
When this type of LED goes open circuit, the effect is as
if the LED forward voltage has increased, but no light
will be emitted. Any affected string will not be disabled,
unless the failure results in the boost OVP limit being
reached, allowing all other LEDs in the string to remain
functional. Care should be taken in this case that the
boost OVP limit and SCP limit are set properly, so as to
make sure that multiple failures on one string do not
cause all other good channels to be faulted out. This is
due to the increased forward voltage of the faulty
channel making all other channel look as if they have
LED shorts. See Table 1 for details for responses to fault
conditions.
The upper threshold is set to +150°C. Each time this is
reached, the boost will stop switching and the output
current sources will be switched off and stay off until the
control driver is power off and and re-enables it. Also
unless disabled via the /SHUT pin, the device stays in an
active state throughout.
For the extensive fault protection conditions, please refer
to Figure 25 and Table 1 for details.
Shutdown
When the EN pin is low the entire chip is shut down to
give close to zero shutdown current. The digital
interfaces will not be active during this time.
FN6998.1
November 5, 2009
13
ISL97678
VIN
VOUT
LX
FAULT
O/P
SHORT
DRIVER
OVP
FET
DRIVER
LOGIC
IMAX
ILIMIT
CH1
VSC
CH8
VSET/2
REG
THRM
SHDN
REF
T2
TEMP
SENSOR
OTP
T1
+
+
-
VSET
VSET
Q1
Q8
-
PWM1/OC1/SC1
PWM8/OC8/SC8
CONTROL
LOGIC
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS
TABLE 1. PROTECTIONS TABLE
V
OUT
REGULATED
BY
CASE FAILURE MODE DETECTION MODE
FAILED CHANNEL ACTION GOOD CHANNELS ACTION
1
CH1 Short Circuit Upper
Over-Temperature
CH1 ON and burns power
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
Protection limit (OTP)
not triggered and
VI
< VSC
IN0
2
3
CH1 Short Circuit Upper OTP triggered
but V < VSC
CH1 goes off
Same as CH1
Highest VF of
CH2 through
CH8
IN1
CH1 Short Circuit Upper OTP not
CH1 disabled after 6 PWM
cycles time-out.
If 3 channels are already
shut down, all channels will CH2 through
be shut down. Otherwise
Highest VF of
triggered but VI
VSC
>
IN1
CH8
CH2-8 will remain as normal
4
CH1 Open Circuit Upper OTP not
V
will ramp to OVP. CH1 will CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
OUT
time-out after 6 PWM cycles
with infinite
resistance
triggered and VIIN1
< VSC
and switch off. V
to normal level.
will drop
OUT
5
6
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not
triggered and VI
VSC
CH1 remains ON and has
CH2 through CH8 ON, Q2
through Q8 burn power
VF of CH1
VF of CH1
< highest VF, thus V
increases
IN1
OUT
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered CH1 goes off
Same as CH1
but VI
< VSC
IN1
FN6998.1
November 5, 2009
14
ISL97678
TABLE 1. PROTECTIONS TABLE (Continued)
V
OUT
REGULATED
BY
CASE FAILURE MODE DETECTION MODE
FAILED CHANNEL ACTION GOOD CHANNELS ACTION
7
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not
triggered but VIIN1 >
VSC
CH1 OFF
CH2 through CH8 Normal
Highest VF of
CH2 through
CH8
Upper OTP not
triggered but VIINx > highest VF, thus V
VSC
CH1 remains ON and has
V
increases then CH-X
VF of CH1
OUT
switches OFF. This is an
unwanted shut off and can
be prevented by setting OVP
and/or VSC at an
OUT
increases.
appropriate level.
8
9
Channel-to-
Channel ΔVF too
high
Lower OTP triggered Any channel at below the target current will fault out after
Highest VF of
CH1 through
CH8
but VIINx < VSC
6 PWM cycles.
Remaining channels driven with normal current.
Channel-to-
Channel ΔVF too
high
Upper OTP triggered All channels switched off
but VIINx < VSC
Highest VF of
CH1 through
CH8
10
11
Output LED string
voltage too high
V
> VOVP
Driven with normal current. Any channel that is below the
target current will time-out after 6 PWM cycles.
Highest VF of
CH1 through
CH8
OUT
V
/LX shorted
OUT
LX will not switch
to GND
FN6998.1
November 5, 2009
15
ISL97678
offer small size and a lower value of temperature and
voltage coefficient compared to other ceramic capacitors.
Components Selections
According to the inductor Voltage-Second Balance
principle, the change of inductor current during the
switching regulator On-time is equal to the change of
inductor current during the switching regulator Off-time.
Since the voltage across an inductor is as shown in
Equation 6:
It is recommended that an input capacitor of at least
10µF be used. Ensure the voltage rating of the input
capacitor is suitable to handle the full supply range.
Inductor
The selection of the inductor should be based on its
(EQ. 6)
V
= L × ΔI ⁄ Δt
L
L
maximum and saturation current (I
) characteristics,
SAT
power dissipation (DCR), EMI susceptibility (shielded vs
unshielded), and size. Inductor type and value influence
many key parameters, including ripple current, current
limit, efficiency, transient performance and stability.
and ΔI @ On = ΔI @ Off, therefore:
L
L
(EQ. 7)
(V – 0) ⁄ L × D × t = (V – V – V ) ⁄ L × (1 – D) × t
S
I
S
O
D
I
where D is the switching duty cycle defined by the
The inductor’s maximum current capability must be
adequate enough to handle the peak current at the worst
case condition. Additionally, if an inductor core is chosen
with too low a current rating, saturation in the core will
cause the effective inductor value to fall, leading to an
increase in peak to average current level, poor efficiency
and overheating in the core. The series resistance, DCR,
within the inductor causes conduction loss and heat
dissipation. A shielded inductor is usually more suitable
for EMI susceptible applications, such as LED
turn-on time over the switching periods. V is Schottky
D
diode forward voltage that can be neglected for
approximation.
Rearranging the terms without accounting for V gives
D
the boost ratio and duty cycle respectively as Equations 8
and 9:
(EQ. 8)
V
⁄ V = 1 ⁄ (1 – D)
I
O
(EQ. 9)
D = (V – V ) ⁄ V
O
O
I
backlighting.
Input Capacitor
The peak current can be derived from the voltage across
the inductor during the Off-period, as expressed in
Equation 10:
Switching regulators require input capacitors to deliver
peak charging current and to reduce the impedance of
the input supply. This reduces interaction between the
regulator and input supply, thereby improving system
stability. The high switching frequency of the loop causes
almost all ripple current to flow in the input capacitor,
which must be rated accordingly.
IL
= (V × I ) ⁄ (85% × V ) + 1 ⁄ 2[V × (V – V ) ⁄ (L × V × f
)
peak
O
O
I
I
O
I
O
SW
(EQ. 10)
The choice of 85% is just an average term for the
efficiency approximation. The first term is the average
current, which is inversely proportional to the input
voltage. The second term is the inductor current change,
A capacitor with low internal series resistance should be
chosen to minimize heating effects and improve system
efficiency, such as X5R or X7R ceramic capacitors, which
which is inversely proportional to L and f . As a result,
SW
for a given switching.
FN6998.1
November 5, 2009
16
ISL97678
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
11/5/09
10/26/09
REVISION
FN6998.1
FN6998.0
CHANGE
Changed VSC spec from Changed VSC spec from “3.3min, 4.4max” to “3.3min, 4.6max”.
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL97678
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
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patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6998.1
November 5, 2009
17
ISL97678
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
4X
3.5
0.50
5.00
28X
A
6
B
PIN #1 INDEX AREA
32
25
6
1
24
PIN 1
INDEX AREA
3 .30 ± 0 . 15
17
8
(4X)
0.15
9
16
0.10 M
C
A B
0.07
+
32X 0.40 ± 0.10
4
32X 0.23
- 0.05
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08
C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 30 )
(32X 0 . 23 )
( 32X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6998.1
November 5, 2009
18
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